1 Memory market and memory complexity Notation Faults and failures MATS+ March Test Memory fault models March test algorithms Inductive fault analysis Summary Lecture 15 Memory Test Original slides copyright by Mike Bushnell and Vishwani Agrawal
65
Embed
1 n Memory market and memory complexity n Notation n Faults and failures n MATS+ March Test n Memory fault models n March test algorithms n Inductive fault.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1
Memory market and memory complexity
Notation Faults and failures MATS+ March Test Memory fault models March test algorithms Inductive fault analysis Summary
Lecture 15Memory Test
Lecture 15Memory Test
Original slides copyright by Mike Bushnell and Vishwani Agrawal
2
Density and Cost TrendsDensity and Cost Trends
1970 -- DRAM Invention (Intel) 1024 bits 1993 -- 1st 256 Mb DRAM papers 1997 -- 1st 256 Mb DRAM samples
Univ.) -- Invented Virtual Memory IBM 360/85 - cache memory (to hide slow core) 1997 -- Cache DRAM -- SRAM cache + DRAM now
on 1 chip
¢ ¢
3
Memory Cells Per ChipMemory Cells Per Chip
4
Test Time in Seconds(Memory Size - n Bits)Test Time in Seconds(Memory Size - n Bits)
n
1 Mb4 Mb
16 Mb64 Mb
256 Mb1 Gb2 Gb
n
0.060.251.014.03
16.1164.43128.9
n X log2n
1.265.5424.16104.7451.0
1932.83994.4
n3/2
64.5515.41.2 hr9.2 hr
73.3 hr586.4 hr
1658.6 hr
n2
18.3 hr293.2 hr
4691.3 hr75060.0 hr
1200959.9 hr19215358.4 hr76861433.7 hr
Size Number of Test Algorithm Operations
5
NotationNotation 0 -- A cell is in logical state 0 1 -- A cell is in logical state 1 X -- A cell is in logical state X A -- A memory address ABF -- AND Bridging Fault AF -- Address Decoder Fault B -- Memory # bits in a word BF -- Bridging Fault C -- A Memory Cell CF -- Coupling Fault
another cell to change coupled cell – cell forced to change by a
coupling cell DRF -- RAM Data Retention Fault k -- Size of a neighborhood M -- memory cells, words, or address set n -- # of Memory bits N -- Number of address bits: n = 2N
NPSF -- Neighborhood Pattern Sensitive Fault
7
Notation (Continued)Notation (Continued)
OBF -- OR Bridging Fault SAF -- Stuck-at Fault SCF -- State Coupling Fault SOAF -- Stuck-Open Address
Decoder Fault TF -- Transition Fault
8
FaultsFaults
System -- Mixed electronic, electromechanical, chemical, and photonic system (MEMS technology)
Failure -- Incorrect or interrupted system behavior
Error -- Manifestation of fault in system Fault -- Physical difference between
good & bad system behavior
9
Fault TypesFault Types
Fault types: Permanent -- System is broken and
stays broken the same way indefinitely Transient -- Fault temporarily affects
the system behavior, and then the system reverts to the good machine -- time dependency, caused by environmental condition
Intermittent -- Sometimes causes a failure, sometimes does not
(timing faults) Physical Irregularities (narrow wire -- high
resistance) Electrical Noise (memory state changes)
13
Physical Failure Mechanisms
Physical Failure Mechanisms
Corrosion Electromigration Bonding Deterioration -- Au package wires
interdiffuse with Al chip pads Ionic Contamination -- Na+ diffuses through
package and into FET gate oxide Alloying -- Al migrates from metal layers into
Si substrate Radiation and Cosmic Rays -- 8 MeV, collides
with Si lattice, generates n - p pairs, causes soft memory error
14
Memory Test LevelsMemory Test Levels
Chip, Array, & Board
15
March Test NotationMarch Test Notation r -- Read a memory location
w -- Write a memory location
r0 -- Read a 0 from a memory location
r1 -- Read a 1 from a memory location
w0 -- Write a 0 to a memory location
w1 -- Write a 1 to a memory location
-- Write a 1 to a cell containing 0
-- Write a 0 to a cell containing 1
16
March Test Notation (Continued)
March Test Notation (Continued)
-- Complement the cell contents
-- Increasing memory addressing
-- Decreasing memory addressing
-- Either increasing or decreasing
17
More March Test NotationMore March Test Notation -- Any write operation < ... > -- Denotes a particular fault, ... <I / F > -- I is the fault sensitizing condition,
F is the faulty cell value <I1, ..., In-1 ; In / F> -- Denotes a fault
covering n cells I1, ..., In-1 are fault sensitization
conditions in cells 1 through n - 1 for cell n In gives sensitization condition for cell n If In is empty, write In / F as F
A
18
MATS+ March TestMATS+ March TestM0: { March element (w0) }
for cell := 0 to n - 1 (or any other order) dowrite 0 to A [cell];
M1: { March element (r0, w1) }for cell := 0 to n - 1 do
read A [cell]; { Expected value = 0}write 1 to A [cell];
M2: {March element (r1, w0) }for cell := n – 1 down to 0 do
read A [cell]; { Expected value = 1 }write 0 to A [cell];
19
Fault ModelingFault Modeling
Behavioral (black-box) Model -- State machine modeling all memory content combinations -- Intractable
Functional (gray-box) Model -- Used Logic Gate Model -- Not used
Inadequately models transistors & capacitors
Electrical Model -- Very expensive Geometrical Model -- Layout Model
Used with Inductive Fault Analysis
20
Functional ModelFunctional Model
21
Simplified Functional ModelSimplified Functional Model
Refresh -- Read all bits in 1 row and simultaneously refresh them
23
Subset Functional FaultsSubset Functional Faults
abcdefgh
Functional faultCell stuckDriver stuckRead/write line stuckChip-select line stuckData line stuckOpen circuit in data lineShort circuit between data linesCrosstalk between data lines
24
Subset Functional Faults (Continued)
Subset Functional Faults (Continued)
ijklmnop
Functional faultAddress line stuckOpen circuit in address lineShorts between address linesOpen circuit in decoderWrong address accessMultiple simultaneous address accessCell can be set to 0 but not to 1 (or vice versa)Pattern sensitive cell interaction
Functional faultCell stuckDriver stuckRead/write line stuckChip-select line stuckData line stuckOpen circuit in data lineShort circuit between data linesCrosstalk between data linesAddress line stuckOpen circuit in address lineShorts between address linesOpen circuit in decoderWrong address accessMultiple simultaneous address accessCell can be set to 0 (1) but not to 1 (0)Pattern sensitive cell interaction
43
Fault Modeling Example 1Fault Modeling Example 1
SCF<0;0>
SA0
SCF<1;1>
AF+SAFSAF
SA0SA0
TF< /1> TF< /0>
44
Fault Modeling Example 2Fault Modeling Example 2
ABF
ABF
SA0
ABF
SA1 SA1+SCF
SCF
gg
45
Multiple Fault ModelsMultiple Fault Models Coupling Faults: In real manufacturing, any #
DRAM or SRAM FaultsShorts & opens in memory cell arrayShorts & opens in address decoderAccess time failures in address decoderCoupling capacitances between cellsBit line shorted to word lineTransistor gate shorted to channelTransistor stuck-open faultPattern sensitive fault Diode-connected transistor 2 cell short Open transistor drain Gate oxide short Bridging fault
ModelSAF,SCF
AFFunctional
CFIDDQIDDQSOFPSF
49
SRAM Only Fault ModelingSRAM Only Fault Modeling
Faults found only in SRAMOpen-circuited pull-up deviceExcessive bit line coupling capacitance
ModelDRFCF
50
DRAM Only Fault Modeling
Faults only in DRAMData retention fault (sleeping sickness)Refresh line stuck-at faultBit-line voltage imbalance faultCoupling between word and bit lineSingle-ended bit-line voltage shiftPrecharge and decoder clock overlap
ModelDRFSAFPSFCFPSFAF
51
Test Influence on SRAM Fault Coverage
Test Influence on SRAM Fault Coverage
52
Influence of Addressing Order on Fault Coverage
Influence of Addressing Order on Fault Coverage
53
Critical Path LengthCritical Path Length Length of parallel wires separated by
dimension of spot defect size TFs and CFids happen only on long wires