1 Microwave & RF Dernières évolutions des technologies dassemblage microélectronique en 3D Presented by Dr Christian Val Founder of 3D Plus 408 rue Hélène.

11

Microwave & RFMicrowave & RF

Dernières évolutions des technologies Dernières évolutions des technologies d’assemblage microélectronique en 3Dd’assemblage microélectronique en 3D

Presented by Dr Christian ValPresented by Dr Christian ValFounder of 3D PlusFounder of 3D Plus

408 rue Hélène Boucher408 rue Hélène Boucher78532 BUC (France)78532 BUC (France)[email protected]@3d-plus.com

Paris 5 Avril 2012Paris 5 Avril 2012

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PLANPLAN

- - IntroductionIntroduction- Technology of the Stacking of - Technology of the Stacking of Rebuilt WafersRebuilt Wafers- Comparison between PoP/W2W - Comparison between PoP/W2W and WDoD and WDoD - Applications- Applications- Conclusion- Conclusion

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Company HighlightsCompany Highlights Spin off from Thales (1996), from September 2011, 3D Spin off from Thales (1996), from September 2011, 3D

Plus is a 100% subsidiary of HEICO companyPlus is a 100% subsidiary of HEICO company Strong R&D from the 3D Plus launchingStrong R&D from the 3D Plus launching Active patenting policyActive patenting policy Space certifications from CNES, ESA, NASA, Space certifications from CNES, ESA, NASA,

JPL,JAXA, CAST etc…JPL,JAXA, CAST etc… ISO 9001 from 2003ISO 9001 from 2003 Exportation: 90% Exportation: 90% Workforce : 115 Workforce : 115 R and D : 12 including 6 PhDR and D : 12 including 6 PhD

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PLANPLAN

- Introduction- Introduction- - Technology to Stack the Rebuilt Technology to Stack the Rebuilt WafersWafers- Comparison between PoP/W2W - Comparison between PoP/W2W and WDoD Technologies and WDoD Technologies- Applications- Applications- Conclusion- Conclusion

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3D Existing Packaging Technology3D Existing Packaging Technology

Chip-on-Chip

Wire bonding

Edge connection

Bus metal Bus silver epoxy

Wafer Level Stacking

Rebuilt Wafer to Rebuilt wafer

Wafer to wafer

Thru-Polymer Via

« TPV »

Thru-Si Via « TSV »

-Amkor-ASE-STATS-SPIL-…

-3D Plus-Irvine Sensors

-VCI -Samsung-IBM-INTEL-ST Micro-Micron-Toshiba-- Etc…

-3D Plus

-Freescale-Infineon-Etc…

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Limits of Wafer to Wafer with TSVLimits of Wafer to Wafer with TSV

Non multi sourcing wafers Non multi sourcing wafers Need for smallest possible Via (2µm Need for smallest possible Via (2µm Ø, leads Ø, leads

to a thickness of 20 µm or less to a thickness of 20 µm or less Yield of these Yield of these filled via is low (redondancy is expected)filled via is low (redondancy is expected)

Difficulties with SiP, since die of different sizesDifficulties with SiP, since die of different sizes TSV stresses (keep out zone between 20 to 200 TSV stresses (keep out zone between 20 to 200

µm)µm) Unfortunately impossible to have 100% good Unfortunately impossible to have 100% good

wafer wafer very low global yield very low global yield

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WDoD WDoD ™™(1)(1) initial criteria initial criteria

Use of multi sourcing wafersUse of multi sourcing wafers Stacking of 10 levels per mm, now Stacking of 10 levels per mm, now 20 levels/mm in development20 levels/mm in development Size: 100µm around the larger DieSize: 100µm around the larger Die Stacking of Known Good Rebuilt Wafer (KGRW)Stacking of Known Good Rebuilt Wafer (KGRW) Possibility to stack Known Good Burn-In Rebuilt WaferPossibility to stack Known Good Burn-In Rebuilt Wafer Parallel processing/Panelization from A to ZParallel processing/Panelization from A to Z

(1) Wirefree Die on Die – Trade Mark from 3D Plus(1) Wirefree Die on Die – Trade Mark from 3D Plus

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1010

3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 1212

3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 1313

PoP and WDoD package

10/04/2310/04/239 February 20099 February 2009 3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 1515

10/04/2310/04/23 9 February 20099 February 2009 3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 1616

10/04/2310/04/239 February 20099 February 2009 3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 1717

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PLANPLAN

- Introduction- Introduction- Stacking of Rebuilt Wafers- Stacking of Rebuilt Wafers- Comparison between PoP/W2W - Comparison between PoP/W2W and WDoD Technologies and WDoD Technologies- Applications- Applications- Conclusion- Conclusion

PoP and WDoD package

2020

PLANPLAN

- Introduction- Introduction- Stacking of Rebuilt Wafers- Stacking of Rebuilt Wafers- Comparison between PoP/W2W - Comparison between PoP/W2W and WDoD Technologies and WDoD Technologies- Applications- Applications- Conclusion- Conclusion

MEDICAL APPLICATIONS:

- Micro camera for Endoscopy (2,6 x 2,6 mm)- Modules for Pacemaker, Neuro stimulator- Module for 40 silicon capacitors on 20 levels- Earing aids

- X Ray camera with Philips/ Germany- European program/ e-CUBES with pacemaker- European program/ e-BRAINS with MEMS

INDUSTRIAL APPLICATIONS“Structural Health Monitoring”

- Abandoned Sensors for avionics- Stacking of FPGA (bare die) + DDR3 + PROM for military and industrial applications

NICHE APPLICATIONS

10/04/2310/04/239 February 20099 February 2009 3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 2222

10/04/2310/04/239 February 20099 February 2009 3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 2323

Contribution to e-Cubes – Program(from NXP Belgium)

Going further than flip-chip – 3D SiP integration for hearing aids– Through Silicon Vias (TSV)– Edge Vertical Routing (Based on 3DPlus

technology)

CARRIER

Redistribution Layer(RDL)

Edge vertical routing (3Dplus technology)

PICS & CMOS dies thinned to ~100um

APPLICATION FLEX

CMOS

CMOS

PICS

Through Silicon Via (TSV)

10/04/2310/04/239 February 20099 February 2009 3D PLUS Proprietary and Confidential3D PLUS Proprietary and Confidential 3030

3200-1951-2

3D PLUS / 02-2009

Dicing Line Active components (Asic.....)

Test Pad

Ni Lid

Resin

MemsFe Ni Co Alloy Ring Alumina substrate(2 layers)

"OPPOSITE TWIN CAVITIES TECHNOLOGY"Zero Stress, Full Hermeticity

Cavity 1

Stackingof "n" levels

WDoD

Cavity 2

Application WDoD with MEMS – Opposite Twin Cavities Technology for MEMS

(Zero Stress, Full Hermeticity)

Structural Health Monitoring

Abandoned Sensors

A n ten n a 1

Antenna 2A

nten

na 3

d ia g ram a t tim e Ti

d ia g ram a t tim e Ti + 1

In te r ro g a tin g U n it(p ro g r a m m in ga n d d o w n lo a d )

ca b le

v ib ra tin gp la tfo rm

Aero Demonstrator Partnership workflow –e-CUBES Program

3D+

TAS

IZM

Existing components

+ energy scavenger

U. Paderborn

TyndallEPFL Philips

Alcatel

IMEC

Very complex problemfor 100s sensors

To be checked by simulations

Innovationproof of concept OKDemonstration for

Y3 TBC

RTOS

WUB

dies

chipsetDelay lines

Flexfoil

Specs

3D PLUS Demonstrator e-CUBES Program

w ire le s sin te rfac e

sm a rt c lo ck(au ton o m o u s andsy nc h ron isab le )

ev en ts sto rag em e m o ry

u ltra low p o w e rm ic ro c on tro lle r

P o w e rM a n a g e m e n t

b lo c k

A cc e le ron° 1

A cc e le ron° 2

A cc e le ron° 3

Tsen so r

R Hsen so r

Psen so r

mic

ro-b

atte

ry

Te m p e r a tu r e

A c c e le r a t io n X

low

pow

erA

DC

inte

rfac

e

vibr

atio

ns e

nerg

ysc

aven

gers

V ib ra t io n s an d s h o ck s

A c c e le r a t io n Y

A c c e le r a t io n Z

R H fa c to r

P re s su rew a k e -u p

b lo c k

s w itc h in gb lo c k

3D PLUS Module

Abandoned Sensors e-CUBES Program

• 1 RH and 1 P transducers on top

• 1 T transducer on each face

• Pads on bottom for connexions to the RF block

• Pads at the top (energy + “rescue operations”)

• Specific anti-screwing fixation

• Internal cube = 8 mm X 8 mm X 14 mm (Target: 6 x 6 x 6 mm/ 0,22 cm3)

L F e le c tro n icsin te rn a l cu b e

ep o x yF lex fo il

re c h a rg e a b le m ic ro -b a tte ry

v ib ra tio n sc a v e n g e r

3636

WDoDWDoD™™ Status Status Proof of Concept – completed (2002-2005) Proof of Concept – completed (2002-2005)

– European funding (25 M$) with CEA/LETI, European funding (25 M$) with CEA/LETI, AXALTO, ST Microelectronics, 3D PLUS, …AXALTO, ST Microelectronics, 3D PLUS, …

Process Development & Optimization of Process Development & Optimization of WDoD (from 2006 up to Feb 2009) with WDoD (from 2006 up to Feb 2009) with NXP/Philips semiconductorNXP/Philips semiconductor

From Feb 2009 Prototyping with the RCP From Feb 2009 Prototyping with the RCP Process from Freescale/PhoenixProcess from Freescale/Phoenix

Functional Prototypes with Nanium. Stack of Functional Prototypes with Nanium. Stack of 4 DDR3/JEDEC Qualification (end of 2011)4 DDR3/JEDEC Qualification (end of 2011)

3737

PLANPLAN

- Introduction- Introduction- Stacking of Rebuilt Wafers- Stacking of Rebuilt Wafers- Comparison between PoP/W2W - Comparison between PoP/W2W and WDoD Technologies and WDoD Technologies- Applications- Applications- - ConclusionConclusion

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Conclusion and perspectivesConclusion and perspectives

Miniaturization for Consumer, Medical and security domains demands Miniaturization for Consumer, Medical and security domains demands very high interconnection densities and low costs .very high interconnection densities and low costs . ReconsideringReconsidering former former experiences: Hybrids,Multichip Modules, Wafer Scale Integration (20 experiences: Hybrids,Multichip Modules, Wafer Scale Integration (20 years ago), PoP instead of PiP; we learned that the yield constitued an years ago), PoP instead of PiP; we learned that the yield constitued an important part of the production costs.important part of the production costs.

The WDoD process only allows to stack Known Good Rebuilt Wafers .The WDoD process only allows to stack Known Good Rebuilt Wafers .

Several applications in the medical and industrial and large volume areas Several applications in the medical and industrial and large volume areas have been presented.have been presented.

This important densification of 10, soon 20 levels per mm, allows to launch This important densification of 10, soon 20 levels per mm, allows to launch extremely ambitious applications in the field of System in Package for extremely ambitious applications in the field of System in Package for Memory-only and SiP for Smart cards and Mobile phone.Memory-only and SiP for Smart cards and Mobile phone.

Thank you for your attentionThank you for your attention

www.3d-plus.comwww.3d-plus.com 3939

Ultra Dense 3-D Micro system with WDoD