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Integrated Silicon Solution, Inc. — www.issi.com 1Rev. G7/30/2014
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:a.) the risk of injury or damage has been minimized;b.) the user assume all such risks; andc.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
• OperatingTemperatureRange Commercial (0oC to +70oC) Industrial (-40oC to +85oC) AutomotiveGradeA1(-40oC to +85oC) AutomotiveGradeA2(-40oC to +105oC)
OVERVIEWISSI's64MbSynchronousDRAMisorganizedas1,048,576bits x 16-bit x 4-bank for improved performance. Thesynchronous DRAMs achieve high-speed data transferusing pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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GENERAL DESCRIPTIONThe 64Mb SDRAM is a high speed CMOS, dynamicrandom-access memory designed to operate in 3.3Vmemory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronousinterface.Each16,777,216-bitbankisorganizedas4,096rows by 256 columns by 16 bits.
The64MbSDRAMincludesanAUTOREFRESHMODE,and a power-saving, power-down mode. All signals are registeredonthepositiveedgeoftheclocksignal,CLK.AllinputsandoutputsareLVTTLcompatible.
The64MbSDRAMhastheabilitytosynchronouslyburstdata at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.
A self-timed row precharge initiated at the end of the burst sequenceisavailablewiththeAUTOPRECHARGEfunctionenabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. Theregistration of an ACTIVE command begins accesses,followedbyaREADorWRITEcommand.TheACTIVEcommand in conjunction with address bits registered are usedtoselect thebankandrowtobeaccessed(BA0,BA1selectthebank;A0-A11selecttherow).TheREADor WRITE commands in conjunction with address bitsregistered are used to select the starting column location for the burst access.
ProgrammableREADorWRITEburstlengthsconsistof1, 2, 4 and 8 locations, or full page, with a burst terminate option.
CLKCKECSRASCASWEA10
A9A8A7A6A5A4A3A2A1A0
BA0BA1
A11
COMMANDDECODER
&CLOCK
GENERATOR MODEREGISTER
REFRESHCONTROLLER
REFRESHCOUNTER
SELF
REFRESH
CONTROLLER
ROWADDRESS
LATCH MU
LTIP
LEX
ER
COLUMNADDRESS LATCH
BURST COUNTER
COLUMNADDRESS BUFFER
COLUMN DECODER
DATA INBUFFER
DATA OUTBUFFER
DQM
DQ 0-15
VDD/VDDQ
GND/GNDQ
12
12
8
12
12
8
16
16 16
16
256K(x 16)
4096
4096
4096
RO
W D
EC
OD
ER 4096
MEMORY CELLARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROWADDRESSBUFFER
FUNCTIONAL BLOCK DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com 3Rev. G7/30/2014
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PIN CONFIGURATIONPACKAge Code: B 54 BALL Tf-BgA (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
GNDQ
VDDQ
GNDQ
VDDQ
GND
CKE
A9
A6
A4
VDDQ
GNDQ
VDDQ
GNDQ
VDD
CAS
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
DQML
RAS
BA1
A1
A2
GND
DQ14
DQ12
DQ10
DQ8
DQMH
NC
A8
GND
VDD
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
VDD
PIN DESCRIPTIONSA0-A11 Row Address InputA0-A7 Column Address InputBA0, BA1 Bank Select AddressesdQ0 to dQ15 data I/oCLK System Clock InputCKe Clock enableCS Chip SelectRAS Row Address Strobe CommandCAS Column Address Strobe Command
WE Write enableLdQM, UdQM x16 Input/output MaskVdd PowergNd groundVddq Power Supply for I/o PingNdQ ground for I/o PinNC No Connection
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22, 35 with A10 defining auto precharge) to select one location out of the memory array intherespectivebank.A10issampledduringaPRECHARGEcommandtodeter-mineifallbanksaretobeprecharged(A10HIGH)orbankselectedby BA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOADMODEREGISTERcommand.
CLK 38 Input Pin CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdeviceare acquired in synchronization with the rising edge of this pin.
CS 19 InputPin TheCS input determines whether command input is enabled within the device. Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.Thedevice remains in the previous state when CSisHIGH.
UDQM mode,LDQMandUDQMcontroltheoutputbuffer.WhenLDQMorUDQMisLOW,thecorrespondingbufferbyteisenabled,andwhenHIGH,disabled.TheoutputsgototheHIGHimpedancestatewhenLDQM/UDQMisHIGH.Thisfunctioncor-responds to OEinconventionalDRAMs.Inwritemode,LDQMandUDQMcontroltheinputbuffer.WhenLDQMorUDQMisLOW,thecorrespondingbufferbyteisen-abled,anddatacanbewrittentothedevice.WhenLDQMorUDQMisHIGH,inputdata is masked and cannot be written to the device.
RAS 18 Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the "Com-mandTruthTable"itemfordetailsondevicecommands.
WE 16 Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the "Com-mandTruthTable"itemfordetailsondevicecommands.
Vddq 3,9,43,49 PowerSupplyPin Vddq is the output buffer power supply.
Vdd 1, 14, 27 Power Supply Pin Vdd is the device internal power supply.
GNdq 6, 12, 46, 52 Power Supply Pin GNdq is the output buffer ground.
GNd 28, 41, 54 Power Supply Pin GNd is the device internal ground.
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READTheREADcommandselectsthebankfromBA0,BA1inputsand starts a burst read access to an active row. Inputs A0-A7providesthestartingcolumnlocation.WhenA10isHIGH,thiscommandfunctionsasanAUTOPRECHARGEcommand.Whentheautoprechargeisselected,therowbeingaccessedwillbeprechargedattheendoftheREADburst.TherowwillremainopenforsubsequentaccesseswhenAUTOPRECHARGE isnot selected. DQ’s readdata is subject to the logic level on the DQM inputs two clocksearlier.WhenagivenDQMsignalwasregisteredHIGH,thecorrespondingDQ’swillbeHigh-Ztwoclockslater.DQ’swillprovidevaliddatawhentheDQMsignalwasregisteredLOW.
WRITEA burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank,and the starting column location is provided by inputs A0-A7.Whether or notAUTO-PRECHARGE is used isdetermined by A10.
TherowbeingaccessedwillbeprechargedattheendoftheWRITEburst, ifAUTOPRECHARGE isselected. IfAUTOPRECHARGEisnotselected,therowwillremainopen for subsequent accesses.
A memory array is written with corresponding input data onDQ’sandDQMinputlogiclevelappearingatthesametime. Data will be written to memory when DQM signal is LOW.WhenDQMisHIGH,thecorrespondingdatainputswillbeignored,andaWRITEwillnotbeexecutedtothatbyte/column location.
PRECHARGEThePRECHARGEcommandisusedtodeactivatetheopenrowinaparticularbankortheopenrowinallbanks.BA0,BA1canbeusedtoselectwhichbankisprechargedortheyaretreatedas“Don’tCare”.A10determineswhetheroneor all banks are precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period tRP, which is the period required for bankprecharging.Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITEcommandsbeingissuedtothatbank.
AUTO PRECHARGEThe AUTO PRECHARGE function ensures that theprecharge is initiated at the earliest valid stage within a burst.Thisfunctionallowsforindividual-bankprechargewithout requiring an explicit command. A10 can be used toenabletheAUTOPRECHARGEfunction inconjunc-tionwithaspecificREADorWRITEcommand.ForeachindividualREADorWRITEcommand,autoprechargeiseitherenabledordisabled.AUTOPRECHARGEdoesnot
applyexceptinfull-pageburstmode.UponcompletionoftheREADorWRITEburst,aprechargeofthebank/rowthat is addressed is automatically performed.
AUTO REFRESH COMMANDThiscommandexecutestheAUTOREFRESHoperation.Therowaddressandbanktoberefreshedareautomaticallygeneratedduringthisoperation. Thestipulatedperiod(trc) is required for a single refresh operation, and no other com-mandscanbeexecutedduringthisperiod. Thiscommandisexecutedatleast4096timeseveryTref.DuringanAUTOREFRESHcommand,addressbitsare“Don’tCare”.ThiscommandcorrespondstoCBRAuto-refresh.
SELF REFRESHDuringtheSELFREFRESHoperation,therowaddresstobe refreshed, the bank, and the refresh interval are gen-eratedautomaticallyinternally.SELFREFRESHcanbeusedtoretaindataintheSDRAMwithoutexternalclocking,eveniftherestofthesystemispowereddown.TheSELFREFRESHoperationisstartedbydroppingtheCKEpinfromHIGHtoLOW.DuringtheSELFREFRESHoperationallotherinputstotheSDRAMbecome“Don’tCare”.Thedevice must remain in self refresh mode for a minimum period equal to tras or may remain in self refresh mode foranindefiniteperiodbeyondthat.TheSELF-REFRESHoperationcontinuesaslongastheCKEpinremainsLOWand there is no need for external control of any other pins. Thenextcommandcannotbeexecuteduntilthedeviceinternal recovery period (trc) has elapsed. Once CKEgoesHIGH,theNOPcommandmustbeissued(minimum of two clocks) to provide time for the completion of any internal refresh in progress. After the self-refresh, since it is impossible to determine the address of the last row to berefreshed,anAUTO-REFRESHshouldimmediatelybeperformed for all addresses.
BURST TERMINATETheBURSTTERMINATEcommand forcibly terminatesthe burst read and write operations by truncating either fixed-length or full-page bursts and the most recently registeredREADorWRITEcommandpriortotheBURSTTERMINATE.
NO OPERATION WhenCSislow,theNOPcommandpreventsunwantedcommands from being registered during idle or wait states.
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LOAD MODE REGISTERDuringtheLOADMODEREGISTERcommandthemoderegisterisloadedfromA0-A11.Thiscommandcanonlybe issued when all banks are idle.
ACTIVE COMMANDWhen the ACTIVE COMMAND is activated, BA0, BA1inputs selects a bank to be accessed, and the address inputsonA0-A11selectstherow.UntilaPRECHARGEcommand is issued to the bank, the row remains open for accesses.
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TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION CS RAS CAS WE DQM ADDR DQs
COMMANDINHIBIT(NOP) H X X X X X X
NOOPERATION(NOP) L H H H X X X
ACTIVE(Selectbankandactivaterow)(3) L L H H X Bank/Row X
READ(Selectbank/column,startREADburst)(4) L H L H L/H(8) Bank/Col X
WRITE(Selectbank/column,startWRITEburst)(4) L H L L L/H(8) Bank/Col Valid
BURSTTERMINATE L H H L X X Active
PRECHARGE(Deactivaterowinbankorbanks)(5) L L H L X Code X
AUTOREFRESHorSELFREFRESH(6,7) L L L H X X X (Enter self refresh mode)
LOADMODEREGISTER(2) L L L L X Op-Code X
WriteEnable/OutputEnable(8) — — — — L — Active
WriteInhibit/OutputHigh-Z(8) — — — — H — High-ZNOTES:1. CKEisHIGHforallcommandsexceptSELFREFRESH.2. A0-A11 define the op-code written to the mode register.3. A0-A11providerowaddress,andBA0,BA1determinewhichbankismadeactive.4. A0-A7(x16)providecolumnaddress;A10HIGHenablestheautoprechargefeature(nonpersistent),whileA10LOWdisables
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TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENTSTATE COMMAND(ACTION) CS RAS CAS WE
Any COMMANDINHIBIT(NOP/Continuepreviousoperation) H X X X
NOOPERATION(NOP/Continuepreviousoperation) L H H H
Idle ACTIVE(Selectandactivaterow) L L H H
AUTOREFRESH(7) L L L H
LOADMODEREGISTER(7) L L L L
PRECHARGE(11) L L H L
RowActive READ(SelectcolumnandstartREADburst)(10) L H L H
WRITE(SelectcolumnandstartWRITEburst)(10) L H L L
PRECHARGE(Deactivaterowinbankorbanks)(8) L L H L
Read READ(SelectcolumnandstartnewREADburst)(10) L H L H
(Auto WRITE(SelectcolumnandstartWRITEburst)(10) L H L L
Precharge PRECHARGE(TruncateREADburst,startPRECHARGE)(8) L L H L
Disabled) BURSTTERMINATE(9) L H H L
Write READ(SelectcolumnandstartREADburst)(10) L H L H
(Auto WRITE(SelectcolumnandstartnewWRITEburst)(10) L H L L
Precharge PRECHARGE(TruncateWRITEburst,startPRECHARGE)(8) L L H L
Disabled) BURSTTERMINATE(9) L H H LNOTE: 1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(seeTruthTable-CKE)andaftertxsr has been met (if the
previous state was SELFREFRESH). 2.Thistableisbank-specific,exceptwherenoted;i.e.,thecurrentstateisforaspecificbankandthecommandsshownarethose
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
TRUTH TABLE – CKE (1-4)
CURRENT STATE COMMANDn ACTIONn CKEn-1 CKEn
Power-Down X MaintainPower-Down L L
SelfRefresh X MaintainSelfRefresh L L
ClockSuspend X MaintainClockSuspend L L
Power-Down(5) COMMANDINHIBITorNOP ExitPower-Down L H
SelfRefresh(6) COMMANDINHIBITorNOP ExitSelfRefresh L H
Clock Suspend(7) X ExitClockSuspend L H
AllBanksIdle COMMANDINHIBITorNOP Power-DownEntry H L
AllBanksIdle AUTOREFRESH SelfRefreshEntry H L
ReadingorWriting VALID ClockSuspendEntry H L
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n H HNOTES: 1. CKEnisthelogicstateofCKEatclockedgen;CKEn-1 wasthestateofCKEatthepreviousclockedge.2. CurrentstateisthestateoftheSDRAMimmediatelypriortoclockedgen.3. COMMANDnisthecommandregisteredatclockedgen,andACTONnisaresultofCOMMANDn.4. All states and sequences not shown are illegal or reserved.5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tcks is
met).6. Exiting self refresh at clock edge n will put the device in all banks idle state once txsrismet.COMMANDINHIBITorNOP
commands should be issued on clock edges occurring during the txsrperiod.AminimumoftwoNOPcommandsmustbesentduring txsr period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1.
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3. Current state definitions: Idle:Thebankhasbeenprecharged,andtrp has been met. RowActive:Arowinthebankhasbeenactivated,andtrcdhasbeenmet.Nodatabursts/accessesandnoregister
accesses are in progress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-mandstotheotherbankaredeterminedbyitscurrentstateandCURRENTSTATEBANKntruthtables.
Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentrpismet.Oncetrp is met, the bank will be in the idle state.
RowActivating:StartswithregistrationofanACTIVEcommandandendswhentrcdismet.Oncetrcd is met, the bank will be in the row active state.
Readw/Auto Precharge Enabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state. Writew/Auto Precharge Enabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state. 5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;COMMANDINHIBITorNOPcommandsmustbe
applied on each positive clock edge during these states. Refreshing:StartswithregistrationofanAUTOREFRESHcommandandendswhentrcismet.Oncetrc is met, the
tmrdismet,theSDRAMwillbeintheallbanksidlestate. Precharging All:StartswithregistrationofaPRECHARGEALLcommandandendswhentrpismet.Oncetrp is met, all
banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7.Notbank-specific;requiresthatallbanksareidle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9.Notbank-specific;BURSTTERMINATEaffectsthemostrecentREADorWRITEburst,regardlessofbank.10.READsorWRITEslistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabledand
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TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m (1-6)
CURRENTSTATE COMMAND(ACTION) CS RAS CAS WE
Any COMMANDINHIBIT(NOP/Continuepreviousoperation) H X X X
NOOPERATION(NOP/Continuepreviousoperation) L H H H
Idle AnyCommandOtherwiseAllowedtoBankm X X X X
Row ACTIVE(Selectandactivaterow) L L H H
Activating, READ(SelectcolumnandstartREADburst)(7) L H L H
Active,or WRITE(SelectcolumnandstartWRITEburst)(7) L H L L
Precharging PRECHARGE L L H L
Read ACTIVE(Selectandactivaterow) L L H H
(Auto READ(SelectcolumnandstartnewREADburst)(7,10) L H L H
Precharge WRITE(SelectcolumnandstartWRITEburst)(7,11) L H L L
Disabled) PRECHARGE(9) L L H L
Write ACTIVE(Selectandactivaterow) L L H H
(Auto READ(SelectcolumnandstartREADburst)(7,12) L H L H
Precharge WRITE(SelectcolumnandstartnewWRITEburst)(7,13) L H L L
Disabled) PRECHARGE(9) L L H L
Read ACTIVE(Selectandactivaterow) L L H H
(WithAuto READ(SelectcolumnandstartnewREADburst)(7,8,14) L H L H
Precharge) WRITE(SelectcolumnandstartWRITEburst)(7,8,15) L H L L
PRECHARGE(9) L L H L
Write ACTIVE(Selectandactivaterow) L L H H
(WithAuto READ(SelectcolumnandstartREADburst)(7,8,16) L H L H
Precharge) WRITE(SelectcolumnandstartnewWRITEburst)(7,8,17) L H L L
PRECHARGE(9) L L H L
NOTE: 1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(TruthTable-CKE)andaftertxsr has been met (if the previ-
ous state was self refresh). 2.Thistabledescribesalternatebankoperation,exceptwherenoted;i.e.,thecurrentstateisforbankn and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Excep-tions are covered in the notes below.
3. Current state definitions: Idle:Thebankhasbeenprecharged,andtrp has been met. RowActive:Arowinthebankhasbeenactivated,andtrcdhasbeenmet.Nodatabursts/accessesandnoregister
accesses are in progress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
nated. Readw/Auto Precharge Enabled:StartswithregistrationofaREADcommandwithautoprechargeenabled,andendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state. Writew/Auto Precharge Enabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabled,andendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state. 4.AUTOREFRESH,SELFREFRESHandLOADMODEREGISTERcommandsmayonlybeissuedwhenallbanksareidle. 5.ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;itappliestothebankrepresentedbythecurrentstate
only. 6. All states and sequences not shown are illegal or reserved. 7.READsorWRITEstobankmlistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabled
andREADsorWRITEswithautoprechargedisabled.
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16.ForaWRITEwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupttheWRITEonbanknwhenregistered,withthedata-outappearingCASlatencylater.ThePRECHARGEtobanknwillbeginafter tWR is met, where twrbeginswhentheREADtobankmisregistered.ThelastvalidWRITEtobanknwillbedata-inregis-teredoneclockpriortotheREADtobankm(FigCAP3).
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vdd max MaximumSupplyVoltage –1.0to+4.6 V Vddq max MaximumSupplyVoltageforOutputBuffer –1.0to+4.6 V ViN InputVoltage –1.0toVddq +0.5 V Vout OutputVoltage –1.0toVddq +0.5 V Pd max AllowablePowerDissipation 1 W Ics output Shorted Current 50 mA Topr operatingTemperature Com. 0 to +70 °C Ind. -40 to +85 °C A1 -40 to +85 °C A2 -40 to +105 °C Tstg StorageTemperature –65to+150 °C
DC RECOMMENDED OPERATING CONDITIONS(2) (AtTa=0to+70°Cforcommercialgrade.Ta=-40to+85°CforindustrialandA1grade.Ta=-40to+105°CforA2grade)
Symbol Parameter Min. Typ. Max. Unit
Vdd, Vddq SupplyVoltage 3.0 3.3 3.6 V Vih InputHighVoltage(3) 2.0 — Vdd +0.3 V Vil InputLowVoltage(4) -0.3 — +0.8 V
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
tref RefreshCycleTime(4096) Ta ≤ 70oC Com., Ind., A1, A2 — 64 — 64 — 64 ms Ta ≤ 85oC Ind., A1, A2 — — — 64 — 64 ms Ta > 85oC A2 — — — 16 — 16 msNotes:1. Whenpowerisfirstapplied,memoryoperationshouldbestarted200µsafterVddandVddq reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.2. measured with tt =1ns.3. Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming.RiseandfalltimesaremeasuredbetweenVih (min.)andVil
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FUNCTIONAL DESCRIPTIONThe64MbSDRAMs(1Megx16x4banks)arequad-bankDRAMswhichoperateat3.3Vandincludeasynchronousinterface (all signals are registered on the positive edge of theclocksignal,CLK).Eachofthe16,777,216-bitbanksisorganizedas4,096rowsby256columnsby16bits.
ReadandwriteaccessestotheSDRAMareburstoriented;accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC-TIVEcommandwhichisthenfollowedbyaREADorWRITEcommand.TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowtobe accessed (BA0andBA1selectthebank,A0-A11selecttherow).Theaddressbits(A0-A7) registered coincident with the READorWRITEcommandareusedtoselectthestartingcolumn location for the burst access.
Prior to normal operation, the SDRAM must be initial-ized.Thefollowingsectionsprovidedetailedinformationcovering device initialization, register definition, command descriptions and device operation.
InitializationSDRAMs must be powered up and initialized in a predefined manner.
The64MbSDRAMisinitializedafterthepowerisappliedtoVddandVddq (simultaneously), and the clock is stable withDQMHighandCKEHigh.
A100µsdelayisrequiredpriortoissuinganycommandother than a COMMANDINHIBIT or a NOP.TheCOMMANDINHIBITorNOPmaybeappliedduringthe100µsperiodandcontinue should at least through the end of the period.
WithatleastoneCOMMANDINHIBITorNOPcommandhavingbeenapplied,aPRECHARGEcommandshouldbeappliedoncethe100µsdelayhasbeensatisfied.Allbanksmustbeprecharged.Thiswill leaveallbanksinan idle state, afterwhichatleasttwoAUTOREFRESH cycles must be performed. After the AUTOREFRESH cycles are complete, the SDRAM is then ready for mode registerprogramming.
The mode register should be loaded prior to applyingany operational command because it will power up in an unknownstate.AftertheLoadModeRegistercommand,at least oneNOPcommandmust beassertedprior toany command.
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REGISTER DEFINITION
Mode RegisterThemode register isused todefine thespecificmodeofoperationof theSDRAM.Thisdefinition includestheselection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODEREGISTERDEFINITION.
ThemoderegisterisprogrammedviatheLOADMODEREGISTERcommandandwillretainthestoredinformationuntil it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4- M6 specify the CAS latency, M7 and M8 specify the operating mode,M9specifiestheWRITEburstmode,andM10andM11 are reserved for future use.
Themode registermustbe loadedwhenallbanksareidle, and the controller must wait the specified time before initiatingthesubsequentoperation.Violatingeitheroftheserequirements will result in unspecified operation.
Burst LengthReadandwriteaccessestotheSDRAMareburstoriented,with the burst length being programmable, as shown in MODEREGISTERDEFINITION.Theburstlengthdeter-mines the maximum number of column locations that can beaccessedforagivenREADorWRITEcommand.Burstlengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type.The full-pageburstisusedinconjunctionwiththeBURSTTERMINATEcommand to generate arbitrary burst lengths.
Reservedstatesshouldnotbeused,asunknownoperationor incompatibility with future versions may result.
WhenaREADorWRITEcommandisissued,ablockofcolumns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary isreached.TheblockisuniquelyselectedbyA1-A7(x16)when the burst length is set to two; by A2-A7 (x16) when the burst length is set to four; and by A3-A7 (x16) when the burstlengthissettoeight.Theremaining(leastsignificant)address bit(s) is (are) used to select the starting location withintheblock.Full-pageburstswrapwithinthepageifthe boundary is reached.
Burst TypeAccesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.
Theorderingofaccesseswithinaburstisdeterminedbythe burst length, the burst type and the starting column address,asshowninBURSTDEFINITIONtable.
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DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ NOP NOP NOP
CAS Latency - 3
tAC
tOH
DOUT
T0 T1 T2 T3 T4
tLZ
CLK
COMMAND
DQ
READ NOP NOP
CAS Latency - 2
tAC
tOH
DOUT
T0 T1 T2 T3
tLZ
CAS Latency
CAS LatencyTheCAS latency is thedelay, inclockcycles,betweenthe registrationofaREADcommandandtheavailabilityofthefirstpieceofoutputdata.Thelatencycanbesettotwoorthree clocks.
IfaREADcommandisregisteredatclockedgen,andthe latency is m clocks, the data will be available by clock edge n + m.TheDQswillstartdrivingasaresultoftheclock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m.Forexample,assumingthattheclockcycle time is such that all relevant access times are met, ifaREADcommandisregisteredatT0andthelatencyis programmed to two clocks, the DQs will start driving afterT1andthedatawillbevalidbyT2,asshowninCASLatencydiagrams.TheAllowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used.
Reservedstatesshouldnotbeusedasunknownoperationor incompatibility with future versions may result.
CAS LatencyAllowable Operating Frequency (MHz)
Speed CAS Latency = 2 CAS Latency = 3
-5 133 200
-6 133 166
-7 133 143
Operating ModeThenormaloperatingmodeisselectedbysettingM7andM8to zero; the other combinations of values for M7 and M8 are reservedforfutureuseand/ortestmodes.TheprogrammedburstlengthappliestobothREADandWRITEbursts.
Testmodesandreservedstatesshouldnotbeusedbe-cause unknown operation or incompatibility with future versions may result.
Write Burst ModeWhenM9=0,theburstlengthprogrammedviaM0-M2appliestobothREADandWRITEbursts;whenM9=1,theprogrammedburstlengthappliestoREADbursts,butwrite accesses are single-location (nonburst) accesses.
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CLK
CKEHIGH
ROW ADDRESS
BANK ADDRESS
CS
RAS
CAS
WE
A0-A11
BA0, BA1
Activating Specific Row Within Specific Bank
DON'T CARE
CLK
COMMAND ACTIVE NOP NOP
tRCD
T0 T1 T2 T3 T4
READ orWRITE
OPERATION
BANK/ROW ACTIVATIONBeforeanyREADorWRITEcommandscanbe issuedtoabankwithintheSDRAM,arowinthatbankmustbe“opened.”ThisisaccomplishedviatheACTIVEcommand,which selects both the bank and the row to be activated (see ActivatingSpecificRowWithinSpecificBank).
After opening a row (issuinganACTIVEcommand),aREADorWRITEcommandmaybeissuedtothatrow,subjecttothe trcd specification. Minimum trcd should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVEcommandonwhichaREADorWRITEcommandcanbeentered.Forexample,atrcd specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to3.Thisisreflectedinthefollowingexample,whichcov-ersanycasewhere2<[trcd(MIN)/tck] ≤3.(Thesameprocedure is used to convert other specification limits from time units to clock cycles).
AsubsequentACTIVEcommandtoadifferentrowinthesame bank can only be issued after the previous active rowhasbeen“closed”(precharged).TheminimumtimeintervalbetweensuccessiveACTIVEcommands to thesame bank is defined by trc.
AsubsequentACTIVEcommandtoanotherbankcanbeissued while the first bank is being accessed, which results inareductionoftotalrow-accessoverhead.TheminimumtimeintervalbetweensuccessiveACTIVEcommandstodifferent banks is defined by trrd.
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CLK
CKEHIGH
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
CS
RAS
CAS
WE
A0-A7
A10
BA0, BA1 BANK ADDRESS
A8, A9, A11
READ COMMANDREADSREAD bursts are initiated with a READ command, asshownintheREADCOMMANDdiagram.
ThestartingcolumnandbankaddressesareprovidedwiththeREADcommand,andautoprechargeiseitherenabledordisabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericREADcommandsusedinthefol-lowing illustrations, auto precharge is disabled.
DuringREADbursts,thevaliddata-outelementfromthestarting column address will be available following the CASlatencyaftertheREADcommand.Eachsubsequentdata-out element will be valid by the next positive clock edge.TheCASLatencydiagramshowsgeneral timing for each possible CAS latency setting.
Uponcompletionofaburst,assumingnoothercommandshavebeeninitiated,theDQswillgoHigh-Z.Afull-pageburstwill continue until terminated. (At the end of the page, it will wrap to column 0 and continue.)
DatafromanyREADburstmaybetruncatedwithasub-sequentREADcommand,anddatafromafixed-lengthREADburstmaybeimmediatelyfollowedbydatafromaREADcommand.Ineithercase,acontinuousflowofdatacanbemaintained.Thefirstdataelementfromthenewburst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
ThenewREADcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.ThisisshowninConsecutiveREADBurstsforCASlatenciesoftwo and three; data element n + 3 is either the last of a burstoffourorthelastdesiredofalongerburst.The64MbSDRAMusesapipelinedarchitectureandthereforedoesnot require the 2n rule associated with a prefetch architec-ture.AREADcommandcanbeinitiatedonanyclockcyclefollowingapreviousREADcommand.Full-speedrandomread accesses can be performed to the same bank, as showninRandomREADAccesses,oreachsubsequentREADmaybeperformedtoadifferentbank.
DatafromanyREADburstmaybetruncatedwithasub-sequentWRITE command, and data from a fixed-lengthREADburstmaybeimmediatelyfollowedbydatafromaWRITEcommand(subjecttobusturnaroundlimitations).TheWRITEburstmaybeinitiatedontheclockedgeim-mediately following the last (or last desired) data element fromtheREADburst,providedthatI/Ocontentioncanbeavoided. In a given system design, there may be a pos-sibilitythatthedevicedrivingtheinputdatawillgoLow-ZbeforetheSDRAMDQsgoHigh-Z.Inthiscase,atleasta single-cycle delay should occur between the last read dataandtheWRITEcommand.
TheDQMinputisusedtoavoidI/Ocontention,asshowninFiguresRW1andRW2.TheDQMsignalmustbeas-serted (HIGH)at least threeclocksprior to theWRITEcommand (DQM latency is two clocks for output buffers) tosuppressdata-out fromtheREAD.Once theWRITEcommandisregistered,theDQswillgoHigh-Z(orremainHigh-Z),regardlessofthestateoftheDQMsignal,providedtheDQMwasactiveontheclockjustpriortotheWRITEcommandthattruncatedtheREADcommand.Ifnot,thesecondWRITEwillbeaninvalidWRITE.Forexample,ifDQMwasLOWduringT4inFigureRW2,thentheWRITEsatT5andT7wouldbevalid,whiletheWRITEatT6wouldbe invalid.
TheDQMsignalmustbede-assertedpriortotheWRITEcommand (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked.
Afixed-lengthREADburstmaybefollowedby,ortruncatedwith, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst maybetruncatedwithaPRECHARGEcommandtothesamebank.ThePRECHARGEcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minusone.ThisisshownintheREADtoPRECHARGE
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DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ NOP NOP NOP
CAS Latency - 3
tAC
tOH
DOUT
T0 T1 T2 T3 T4
tLZ
CLK
COMMAND
DQ
READ NOP NOP
CAS Latency - 2
tAC
tOH
DOUT
T0 T1 T2 T3
tLZ
CAS Latency
diagram for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of alongerburst.FollowingthePRECHARGEcommand,asubsequent command to the same bank cannot be issued until trpismet.Notethatpartoftherowprechargetimeishidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at theoptimum time (as described above) provides the same operation that would result from the same fixed-length burstwithautoprecharge.ThedisadvantageofthePRE-CHARGEcommandisthatitrequiresthatthecommandand address buses be available at the appropriate time to issuethecommand;theadvantageofthePRECHARGEcommand is that it can be used to truncate fixed-length or full-page bursts.
Full-pageREADburstscanbetruncatedwiththeBURSTTERMINATE command, and fixed-length READ burstsmaybetruncatedwithaBURSTTERMINATEcommand,providedthatautoprechargewasnotactivated.TheBURSTTERMINATEcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.ThisisshownintheREADBurstTerminationdiagramforeachpossible CAS latency; data element n + 3 is the last desired data element of a longer burst.
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DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP READ NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b
BANK,COL n
BANK,COL b
CAS Latency - 2
x = 1 cycle
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP READ NOP NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b
BANK,COL n
BANK,COL b
CAS Latency - 3
x = 2 cycles
Consecutive READ Bursts
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DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
READ READ READ READ NOP NOP
DOUT n DOUT b DOUT m DOUT x
BANK,COL n
BANK,COL b
CAS Latency - 2
BANK,COL m
BANK,COL x
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ READ READ READ NOP NOP NOP
DOUT n DOUT b DOUT m DOUT x
BANK,COL n
BANK,COL b
CAS Latency - 3
BANK,COL m
BANK,COL x
Random READ Accesses
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DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
READ NOP NOP NOP NOP WRITE
BANK,COL n
BANK,COL b
DOUT n DIN b
tDS
tHZ
CAS Latency - 3
RW1 - READ to WRITE
RW2 - READ to WRITE
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP NOP NOP WRITE
BANK,COL n
DIN b
tDS
tHZ
BANK,COL b
CAS Latency - 2
DOUT n DOUT n+1 DOUT n+2
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP NOP NOP ACTIVE
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK a,COL n
BANK a,ROW
BANK(a or all)
CAS Latency - 2
x = 1 cycle
tRP
PRECHARGE
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP NOP NOP ACTIVE
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK,COL n
BANK,COL b
CAS Latency - 3
x = 2 cycles
tRP
BANK a,ROW
PRECHARGE
READ to PRECHARGE
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DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK a,COL n
CAS Latency - 2
x = 1 cycle
BURSTTERMINATE
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ NOP NOP NOP NOP NOP NOP
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
BANK,COL n
CAS Latency - 3
x = 2 cycles
BURSTTERMINATE
READ Burst Termination
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CLK
CKEHIGH
COLUMN ADDRESS
AUTO PRECHARGE
BANK ADDRESS
CS
RAS
CAS
WE
A0-A7
A10
BA0, BA1
NO PRECHARGE
A8, A9, A11
WRITE Command
ThestartingcolumnandbankaddressesareprovidedwiththeWRITEcommand,andautoprechargeiseitherenabledor disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericWRITEcommandsusedinthefollowing illustrations, auto precharge is disabled.
DuringWRITEbursts,thefirstvaliddata-in element will be registered coincident with the WRITEcommand. Subsequent data elements will be registered on each successive posi-tiveclockedge.Uponcompletionofafixed-lengthburst,assuming no other commands have been initiated, the DQswillremainHigh-Zandanyadditionalinputdatawillbeignored(seeWRITEBurst).Afull-pageburstwillcon-tinue until terminated. (At the end of the page, it will wrap to column 0 and continue.)
DataforanyWRITEburstmaybetruncatedwithasubse-quentWRITEcommand,anddataforafixed-lengthWRITEburstmaybe immediately followedbydata foraWRITEcommand.ThenewWRITEcommandcanbe issuedonanyclockfollowingthepreviousWRITEcommand,andthedata provided coincident with the new command applies to the new command.
AnexampleisshowninWRITEtoWRITEdiagram.Datan + 1 is either the last of a burst of two or the last desired of a longer burst.The 64Mb SDRAM uses a pipelinedarchitecture and therefore does not require the 2n rule as-sociatedwithaprefetcharchitecture.AWRITEcommandcan be initiated on any clock cycle following a previous WRITEcommand.Full-speedrandomwriteaccesseswithina page can be performed to the same bank, as shown in RandomWRITECycles,oreachsubsequentWRITEmaybe performed to a different bank.
DataforanyWRITEburstmaybetruncatedwithasubse-quentREADcommand,anddataforafixed-lengthWRITEburstmaybeimmediatelyfollowedbyasubsequentREADcommand.OncetheREADcommandisregistered,thedatainputswillbeignored,andWRITEswillnotbeex-ecuted.AnexampleisshowninWRITEtoREAD.Datan + 1 is either the last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followedby,or truncatedwith,aPRECHARGEcommandto thesame bank (provided that auto precharge was not acti-vated), anda full-pageWRITEburstmaybe truncatedwithaPRECHARGEcommand to thesamebank.ThePRECHARGEcommandshouldbeissuedtwr after the clock edge at which the last desired input data element isregistered.Theautoprechargemoderequiresatwr of at least one clock plus time, regardless of frequency. In addition,whentruncatingaWRITEburst,theDQMsignalmust be used to mask input data for the clock edge prior to,andtheclockedgecoincidentwith,thePRECHARGEcommand.AnexampleisshownintheWRITEtoPRE-CHARGEdiagram.Datan+1 is either the last of a burst oftwoorthelastdesiredofalongerburst.FollowingthePRECHARGEcommand,asubsequentcommandtothesame bank cannot be issued until trp is met.
In the case of a fixed-length burst being executed to comple-tion,aPRECHARGEcommand issuedat theoptimumtime (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge.ThedisadvantageofthePRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantageofthePRECHARGEcommandisthatitcanbeused to truncate fixed-length or full-page bursts.
Fixed-lengthorfull-pageWRITEburstscanbetruncatedwiththeBURSTTERMINATEcommand.Whentruncat-ingaWRITEburst,theinputdataappliedcoincidentwiththeBURSTTERMINATEcommandwillbeignored.Thelastdatawritten(providedthatDQMisLOWatthattime)will be the input data applied one clock previous to the BURSTTERMINATEcommand.ThisisshowninWRITEBurstTermination,wheredatan is the last desired data element of a longer burst.
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3
WRITE NOP NOP NOP
DIN n DIN n+1
BANK,COL n
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2
WRITE NOP WRITE
DIN n DIN n+1 DIN b
BANK,COL n
BANK,COL b
DON'T CARE
WRITE Burst
WRITE to WRITE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3
WRITE WRITE WRITE WRITE
DIN n DIN b DIN m DIN x
BANK,COL n
BANK,COL b
BANK,COL m
BANK,COL x
Random WRITE Cycles
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DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
WRITE NOP READ NOP NOP NOP
DIN n DIN n+1 DOUT b DOUT b+1
BANK,COL n
BANK,COL b
CAS Latency - 2
WRITE to READ
WP1 - WRITE to PRECHARGE
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
WRITE NOP NOP ACTIVE NOP NOP
BANK a,COL n
BANK a,ROW
BANK(a or all)
tWR
tRP
PRECHARGE
DIN n DIN n+1
CAS Latency - 2
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2
WRITE
DIN n (DATA)
BANK,COL n
DON'T CARE
(ADDRESS)
BURSTTERMINATE
NEXTCOMMAND
WRITE Burst Termination
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
WRITE NOP NOP NOP ACTIVE NOP
BANK a,COL n
BANK a,ROW
BANK(a or all)
tWR
tRP
PRECHARGE
DIN n DIN n+1
CAS Latency - 3
WP2 - WRITE to PRECHARGE
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CLK
CKEHIGH
ALL BANKS
BANK SELECT
BANK ADDRESS
CS
RAS
CAS
WE
A0-A9, A11
A10
BA0, BA1
DON'T CARE
CLK
CKE
COMMAND NOP NOP ACTIVE
≥ tCKStCKS
All banks idle
Enter power-down mode Exit power-down mode
tRCD
tRAS
tRC
Input buffers gated off
PRECHARGE Command
POWER-DOWN
POWER-DOWNPower-downoccursifCKEisregisteredLOWcoincidentwithaNOPorCOMMANDINHIBITwhennoaccessesare in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers,excludingCKE,formaximumpowersavingswhileinstandby.Thedevicemaynotremaininthepower-downstate longer than the refresh period (64ms) since no refresh operations are performed in this mode.
Thepower-downstateisexitedbyregisteringaNOPorCOMMANDINHIBITandCKEHIGHatthedesiredclockedge (meeting tcks). See figure below.
PRECHARGEThePRECHARGEcommand(seefigure)isusedtodeac-tivate the open row in a particular bank or the open row in allbanks.Thebank(s)willbeavailableforasubsequentrowaccess some specified time (trp)afterthePRECHARGEcommand is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only onebankistobeprecharged,inputsBA0,BA1selectthebank.Whenallbanksaretobeprecharged,inputsBA0,BA1aretreatedas“Don’tCare.”Onceabankhasbeenprecharged, it is in the idle state and must be activated priortoanyREADorWRITEcommandsbeingissuedtothat bank.
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DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
NOP WRITE NOP NOP
BANK a,COL n
DIN n DIN n+1 DIN n+2
INTERNALCLOCK
DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ NOP NOP NOP NOP NOP
BANK a,COL n
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
INTERNALCLOCK
CLOCK SUSPENDClock suspend mode occurs when a column access/burst is inprogressandCKEisregisteredLOW.In theclocksuspendmode,theinternalclockisdeactivated,“freezing”the synchronous logic.
ForeachpositiveclockedgeonwhichCKEissampledLOW,thenextinternalpositiveclockedgeissuspended.Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See following examples.)
ClocksuspendmodeisexitedbyregisteringCKEHIGH;the internal clock and related operation will resume on the subsequent positive clock edge.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
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DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DOUT a DOUT a+1 DOUT b DOUT b+1
BANK n,COL a
BANK m,COL b
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
tRP - BANK n tRP - BANK m
READ - APBANK n
READ - APBANK m
Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active READ with Burst of 4 Precharge
Internal States
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DOUT a DIN b DIN b+1 DIN b+2 DIN b+3
BANK n,COL a
BANK m,COL b
CAS Latency - 3 (BANK n)
tRP - BANK n tRP - BANK m
WRITE - APBANK n
WRITE - APBANK m
READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active WRITE with Burst of 4 Write-Back
Internal States Page Active
BURST READ/SINGLE WRITETheburstread/singlewritemodeisenteredbyprogrammingthe write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of theprogrammedburstlength.READcommandsaccess columns according to the programmed burst length and sequence,justasinthenormalmodeofoperation(M9=0).
CONCURRENT AUTO PRECHARGEAnaccesscommand(READorWRITE)toanotherbankwhile an access command with auto precharge enabled is executingisnotallowedbySDRAMs,unlesstheSDRAMsupports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMssupportCONCURRENTAUTOPRECHARGE.FourcaseswhereCONCURRENTAUTOPRECHARGEoccurs are defined below.
READ with Auto Precharge1.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankmwill interruptaREADonbankn,CAS latency later.The PRECHARGE to bank n willbeginwhentheREADtobankmisregistered.
2.InterruptedbyaWRITE(withorwithoutautoprecharge):AWRITEtobankmwillinterruptaREADonbanknwhen registered. DQM should be used two clocks prior totheWRITEcommandtopreventbuscontention.ThePRECHARGEtobanknwillbeginwhentheWRITEtobank m is registered.
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
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DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DIN a DIN a+1 DOUT b DOUT b+1
BANK n,COL a
BANK m,COL b
CAS Latency - 3 (BANK m)
tRP - BANK ntRP - BANK m
WRITE - APBANK n
READ - APBANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active READ with Burst of 4 Precharge
Internal States tWR - BANK n
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
BANK n,COL a
BANK m,COL b
tRP - BANK ntRP - BANK m
WRITE - APBANK n
WRITE - APBANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active WRITE with Burst of 4 Write-Back
Internal States tWR - BANK n
DIN a DIN a+1 DIN a+2 DIN b DIN b+1 DIN b+2 DIN b+3
WRITE with Auto Precharge3.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankmwill interruptaWRITEonbanknwhen registered, with the data-out appearing CAS latency later.ThePRECHARGEtobanknwillbeginaftertwr is met, where twrbeginswhentheREADtobankmisregistered.ThelastvalidWRITE to bank n will be data-in registeredoneclockpriortotheREADtobankm.
4.InterruptedbyaWRITE(withorwithoutautoprecharge):AWRITE to bank m will interrupt a WRITE on bank n when registered.ThePRECHARGEtobanknwillbeginaftertwr is met, where twrbeginswhentheWRITEtobankmisregistered.ThelastvaliddataWRITEtobanknwillbedataregisteredoneclockpriortoaWRITEtobank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
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INITIALIzE AND LOAD MODE REGISTER(1)
DON'T CARE
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tCH tCLtCK
tCMS tCMH tCMS tCMH tCMS tCMH
tCKS tCKH
T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3
tMRDtRCtRCtRP
ROW
ROW
BANK
tAS tAH
tAS tAH
CODE
CODEALL BANKS
SINGLE BANK
ALL BANKS
AUTOREFRESH
AUTOREFRESH
Load MODEREGISTER
T = 100µs Min.
Power-up: VCC
and CLK stablePrechargeall banks
AUTO REFRESH Program MODE REGISTER
NOP PRECHARGE NOP NOP NOP ACTIVE
T
(2, 3, 4)AUTO REFRESH
At least 2 Auto-Refresh Commands
Notes:1. If CSisHighatclockHightime,allcommandsappliedareNOP.2.TheModeregistermaybeloadedpriortotheAuto-Refreshcyclesifdesired.3. JEDEC and PC100 specify three clocks.4.OutputsareguaranteedHigh-Zafterthecommandisissued.
Integrated Silicon Solution, Inc. — www.issi.com 39Rev. G7/30/2014
IS42S16400JIS45S16400J
POWER-DOWN MODE CYCLE
CASlatency=2,3
DON'T CARE
CLK
CKE
COMMAND
DQM/DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tAS tAH
BANK
tCHtCLtCK
tCMS tCMH
tCKS tCKH
PRECHARGE NOP NOP NOP ACTIVE
ALL BANKS
SINGLE BANK
ROW
ROW
BANK
tCKStCKS
Precharge allactive banks
All banks idleTwo clock cycles Input buffers gatedoff while in