1 Lecture 6 Lecture 6 The CPU and Memory The CPU and Memory ITEC 1000 “Introduction to Information Technology” [Prof. Peter Khaiter] Pitxot, Antoni Figures of the Allegory of Memory 1981 Oil on canvas 180.30 x 90.40 cm. TEATRE-MUSEU DALI http://www.salvador-dali.org/dali/coleccio
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1 Lecture 6 The CPU and Memory ITEC 1000 “Introduction to Information Technology” [Prof. Peter Khaiter] Pitxot, Antoni Figures of the Allegory of Memory.
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Lecture 6Lecture 6
The CPU and The CPU and MemoryMemory
ITEC 1000 “Introduction to Information Technology”
[Prof. Peter Khaiter]
Pitxot, Antoni Figures of the Allegory of Memory
1981Oil on canvas
180.30 x 90.40 cm. TEATRE-MUSEU DALI
http://www.salvador-dali.org/dali/coleccio
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Lecture Template:Lecture Template:
CPUCPU RegistersRegisters Register operationsRegister operations Memory implementationMemory implementation Computer BusesComputer Buses InstructionsInstructions Using the StacksUsing the Stacks Multiple Data InstructionsMultiple Data Instructions
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Computer unitComputer unit
ALU
CPU
Input/outputinterface
Control unit
Program counter
HighestAddress
Memory
Lowest Address
Memory is separated from the CPU
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Components of the CPU (1 of 2)Components of the CPU (1 of 2)
CUCU (control unit): functionsperforms fetch/execute cycle Accesses and retrieves program instructions from the memory and issues commands to the ALUMoves data to and from CPU registers and other hardware components (no change in data)
RegistersRegistersExample: Program counter (PC) or instruction pointer determines next instruction for execution
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Components of the CU (2 of 2)Components of the CU (2 of 2)
Program counter (instruction pointer)Contains the address of the current or next instruction Normally instructions are executed sequentially
Memory management unitSupervises fetching of instructions and data from memory
I/O InterfaceProvides mechanism for input/output of datasometimes combined with memory management unit in a single Bus Interface Unit
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Concept of RegistersConcept of Registers
Single storage locations within the CPU used for a particular purpose
Used to hold a binary value temporarily Manipulated directly by the Control Unit Each register is wired within the CPU
directly (no address needed) for specific function
Size in bits or bytes (not MB like memory) Can hold data, an address or an instruction
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Registers: what they doRegisters: what they do
Hold data being processed Hold instruction being executed Memory or I/O address being
accessed Keep status of the computer Conditional branch instructions
Random Access Memory (RAM) Read Only Memory (ROM) EEPROM Flash ROM Volatile Nonvolatile
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RAM: Random Access MemoryRAM: Random Access Memory
Random – any piece of data can be accessed in a constant time regardless of physical location (unlike tapes, magnetic or optical discs)
Difference – in technical design DRAM (Dynamic RAM)
Most common, cheapVolatile: must be refreshed (recharged with power) 1000’s of times each second
SRAM (static RAM)Faster to access than DRAM and more expensive than DRAMVolatilesmall amount used in cache memory for high-speed access
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RAM: SampleRAM: Sample
DRAM modules used as primary memory in PCs, workstations, servers.
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ROM - Read Only MemoryROM - Read Only Memory
Implemented in early stored-program computers (e.g., ENIAC, after 1948)
If write protected, becomes read-only memory Non-volatile memory to hold built-in software that is not expected to change over
the life of the computer (e.g., initial program that runs computer)
• BIOS: initial boot instructions and diagnostics Data are physically encoded into chips EEPROM
Electrically Erasable Programmable ROMCan be erased and reprogrammed, 1 byte at a time (up to 1000 times)Slower and less flexible than Flash ROM
Flash ROM Modern type of EEPROM (invented in 1984), faster (erase and write in blocks of bytes)Higher endurance (up to 1,000,000 cycles)E.g., USB Flash Drives
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ROM: SampleROM: Sample
First erasable ROM, Intel 1702; erase window – in the middle
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Memory MapsMemory Maps
The usage of memory space on a system is commonly depicted in a “memory map”
The height of the map is determined by the number of addresses
The width of the map is usually 8 bits E.g.,
a system with a capacity of 216 bytes…
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7 6 5 4 3 2 1 0
FFFF
000200010000
Hexadecimaladdress
Data bitposition
The “bottom” of memory
Memory Map: Sample 1Memory Map: Sample 1
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Use of Memory MapsUse of Memory Maps
Memory maps are usually drawn to show “what is where” on a system
“what” can be:RAM, ROM, I/O, empty space
“Where”:Determined by the starting/ending addresses for each “block” of RAM, ROM, I/O,…,
E.g., a memory map for a system with a capacity of 224 bytes with two 1 MB RAM modules residing consecutively at the bottom of memory….
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Memory Map: Sample 2Memory Map: Sample 2
FFFFFF
2000001FFFFF
1000000FFFFF
000000
224 bytes = 16 MB “capacity”
1 MB RAM
14 MB
empty
1 MB RAM
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Memory Space: Exercise 1Memory Space: Exercise 1
Q: A system with a memory capacity of 128 GB has four 32 MB memory modules installed. The rest of the memory is unused. How much memory space is available for future expansion? (Give your answer in decimal in megabytes.)
A: ?
Skip answer Answer
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Memory Space: Exercise 1Memory Space: Exercise 1
Answer
Q: A system with a memory capacity of 128 GB has four 32 MB memory modules installed. The rest of the memory is unused. How much memory space is available for future expansion? (Give your answer in decimal in megabytes.)
Draw a memory map for a system with a capacity of 2 GB. Assume the system has three 32 MB memory modules residing consecutively at the bottom of memory. Illustrate the size of each block in MB and the starting and ending address of each block of memory in hexadecimal.
Skip answer Answer
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Memory Space: Exercise 2Memory Space: Exercise 2
Answer
7FFFFFFF
0600000005FFFFFF
0400000003FFFFFF
0200000001FFFFFF
00000000
231 bytes = 2 GB “capacity”
32 MB RAM
1,952 MB
empty
32 MB RAM
32 MB RAM
Note:2 GB = 2,048 MB
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Fetch-Execute CycleFetch-Execute Cycle
Two-step process because both instructions and data are in memory
FetchDecode or find instruction, load the code of the instruction from memory
ExecutePerforms operation that instruction requiresMove/transform data
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Fetch-part of the CycleFetch-part of the Cycle
The value in the PC (program counter) register is the address of the memory location that holds instruction to be executed
First step is always: transfer (copy) the value in the PC to the MAR
Then computer can retrieve the instruction located at that address and place it in the MDR
PC MAR (step 1) Memory MDR Next step: transfer instruction to the IR MDR IR (step 2) Remaining steps – instruction dependent
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Load InstructionLoad Instruction
Next step: the address partaddress part of the instruction located in the IR is copied and placed in the MAR
Computer retrieves actual data located at the address in memory and places it in the MDR
IR [address] MAR (step 3) Memory MDR Next step: MDR copies data to the “accumulator”
register MDR A (step 4) Last step: PC is incremented PC + 1 PC (step 5)
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Load Accumulator: Sample (1 of 12)Load Accumulator: Sample (1 of 12)
Task: Simple Eight bit system.
Thirty-two memory locations (0 to 31).
“Load” instruction is 010.
Value in location 15 is ten (i.e.: binary 00001010)
PC is at 5, about to increment.
The instruction, 01001111, is in location 6.
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Load Accumulator: Sample (2 of 12)Load Accumulator: Sample (2 of 12)
PC: 00101
IR: (previous)
A: (previous)
MAR: (previous)
MDR: (previous)
CPU Before PC increments
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (3 of 12)Load Accumulator: Sample (3 of 12)
Increment PC: PC = PC + 1
PC: 00110
IR: (previous)
A: (previous)
MAR: (previous)
MDR: (previous)
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (4 of 12)Load Accumulator: Sample (4 of 12)
PC: 00110
IR: (previous)
A: (previous)
MAR: 00110
MDR: (previous)
MAR loaded with PC: PC -> MAR
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (5 of 12)Load Accumulator: Sample (5 of 12)
PC: 00110
IR: (previous)
A: (previous)
MAR: 00110
MDR: (previous)
Memory Location 00110 Accessedand Contents Placed in MDR:
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (6 of 12)Load Accumulator: Sample (6 of 12)
PC: 00110
IR: (previous)
A: (previous)
MAR: 00110
MDR: 01001111
Memory Location 00110 Accessedand Contents Placed in MDR:
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (7 of 12)Load Accumulator: Sample (7 of 12)
PC: 00110
IR: 01001111
A: (previous)
MAR: 00110
MDR: 01001111
MDR copied to IR: MDR -> IR
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (8 of 12)Load Accumulator: Sample (8 of 12)
PC: 00110
IR: 01001111
A: (previous)
MAR: 01111
MDR: 01001111
IR [ address part ] -> MAR
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (9 of 12)Load Accumulator: Sample (9 of 12)
PC: 00110
IR: 01001111
A: (previous)
MAR: 01111
MDR: 01001111
Location in MAR (01111) Accessed
Location 31
15: 00001010
06: 01001111
Location 0
Memory
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Load Accumulator: Sample (10 of 12)Load Accumulator: Sample (10 of 12)
Memory
PC: 00110
IR: 01001111
A: (previous)
MAR: 01111
MDR: 00001010
Contents of 01111 loaded into MDR
Location 31
15: 00001010
06: 01001111
Location 0
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Load Accumulator: Sample (11 of 12)Load Accumulator: Sample (11 of 12)
Memory
PC: 00110
IR: 01001111
A: 00001010
MAR: 01111
MDR: 00001010
IR [op code] executed: MDR -> A
Location 31
15: 00001010
06: 01001111
Location 0
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Load Accumulator: Sample (12 of 12)Load Accumulator: Sample (12 of 12)
Memory
PC: 00110
IR: 01001111
A: 00001010
MAR: 01111
MDR: 00001010
Finished !
Location 31
15: 00001010
06: 01001111
Location 0
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Load Fetch/Execute CycleLoad Fetch/Execute Cycle
1. PC -> MAR Transfer the address from the PC to the MAR
2. MDR -> IR Transfer the instruction to the IR
3. IR(address) -> MAR Address portion of the instruction loaded in MAR
4. MDR -> A Actual data copied into the accumulator
5. PC + 1 -> PC Program Counter incremented
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Store Fetch/Execute Cycle (1 of 2)Store Fetch/Execute Cycle (1 of 2)
1. PC -> MAR Transfer the address from the PC to the MAR
2. MDR -> IR Transfer the instruction to the IR
3. IR(address) -> MAR Address portion of the instruction loaded in MAR
4. A -> MDR* Accumulator copies data into MDR
5. PC + 1 -> PC Program Counter incremented
*Notice how Step #4 differs for LOAD and STORE
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Store Fetch/Execute Cycle (2 of 2)Store Fetch/Execute Cycle (2 of 2)
PC MAR
MDR IR
IR[address] MAR
A MDR
PC + 1 PC
Fetch
Execute
time
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ADD Fetch/Execute CycleADD Fetch/Execute Cycle (1 of 2)(1 of 2)
1. PC -> MAR Transfer the address from the PC to the MAR
2. MDR -> IR Transfer the instruction to the IR
3. IR(address) -> MAR Address portion of the instruction loaded in MAR
4. A + MDR -> A Contents of MDR added to contents of accumulator
5. PC + 1 -> PC Program Counter incremented
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ADD Fetch/Execute CycleADD Fetch/Execute Cycle (2 of 2)(2 of 2)
PC MAR
MDR IR
IR[address] MAR
A + MDR A
PC + 1 PC
Fetch
Execute
time
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Add Instruction: Sample (1 of 10)Add Instruction: Sample (1 of 10)
New:
Task: Value in location 7 is 10110010.
“Add” instruction is 101.
Value in location 18 is seventy-one
(i.e.: binary 01000111)
Everything else is as we left it!
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Add Instruction: Sample (2 of 10)Add Instruction: Sample (2 of 10)
PC: 00111
IR: 01001111
A: 00001010
MAR: 01111
MDR: 00001010
PC = PC + 1
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
Memory
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Add Instruction: Sample (3 of 10)Add Instruction: Sample (3 of 10)
Memory
PC: 00111
IR: 01001111
A: 00001010
MAR: 00111
MDR: 00001010
PC -> MAR
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
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Add Instruction: Sample (4 of 10)Add Instruction: Sample (4 of 10)
Memory
PC: 00111
IR: 01001111
A: 00001010
MAR: 00111
MDR: 00001010
MAR Accesses Location 00111
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
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Add Instruction: Sample (5 of 10)Add Instruction: Sample (5 of 10)
Memory
PC: 00111
IR: 01001111
A: 00001010
MAR: 00111
MDR: 10110010
Contents of 00111 -> MDR
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
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Add Instruction: Sample (6 of 10)Add Instruction: Sample (6 of 10)
Memory
PC: 00111
IR: 10110010
A: 00001010
MAR: 00111
MDR: 10110010
MDR -> IR
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
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Add Instruction: Sample (7 of 10)Add Instruction: Sample (7 of 10)
Memory
PC: 00111
IR: 10110010
A: 00001010
MAR: 10010
MDR: 10110010
IR [address] -> MAR
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
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Add Instruction: Sample (8 of 10)Add Instruction: Sample (8 of 10)
Memory
PC: 00111
IR: 10110010
A: 00001010
MAR: 10010
MDR: 10110010
Location 10010 [MAR] Accessed
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
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Add Instruction: Sample (9 of 10)Add Instruction: Sample (9 of 10)
Memory
PC: 00111
IR: 10110010
A: 00001010
MAR: 10010
MDR: 01000111
Contents of [10010] -> MDR
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
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Add Instruction: Sample (10 of 10)Add Instruction: Sample (10 of 10)
PC: 00111
IR: 10110010
A: 01010001
MAR: 10010
MDR: 01000111
IR [opcode] executed: A = A + MDR
Location 31
18: 01000111
15: 00001010
07: 10110010
06: 01001111
Location 0
Memory
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Computer BusesComputer Buses
PCI Express BUS Card Slots (from top to bottom: x4, x16, x1, x16) compared to a traditional 32-bit PCI bus card slot.
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Buses (1 of 3)Buses (1 of 3)
Group of electrical conductors (wires) for carrying signals from one location to another
Line: each conductor (or wire) in the busThe physical connection that makes it
possible to transfer data from one location in the computer system to another
4 kinds of signalsData (alphanumeric, numerical, instructions)AddressesControl signalsPower (sometimes)
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Buses (2 of 3)Buses (2 of 3)
Ports
CPU
RAM
Diskcontroller
Graphicscard
Soundcard
Networkcard
Printer
Mouse
Keyboard
ModemMonitor
Speakers
bus
Computer
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Buses (3 of 3)Buses (3 of 3)
Connect CPU and Memory I/O peripherals: on same bus as
CPU/memory or separate bus If connect CPU, Memory and I/O
modules in the same Physical package, called backplanebackplane
Also called system bussystem bus or external busexternal busExample of broadcast busbroadcast busCommon method of connecting CPU, Memory and I/O modules: to a printed circuit board called motherboardmotherboard
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MotherboardMotherboard
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Types of Buses (1 of 2)Types of Buses (1 of 2)
Point-to-pointPoint-to-point When connect plug-in devices,
called portsports
Serialport
Modem
Controlunit ALU
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Types of Buses (2 of 2)Types of Buses (2 of 2)
MultipointMultipoint: to connect several points together
Computer
CPU
Disk controller
Computer
Computer Computer
Memory
Video controller
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Point-to-point vs. MultipointPoint-to-point vs. Multipoint
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Bus InterfaceBus Interface
Bus interface bridgesBus interface bridges: provide communication between different buses
Special buses provide interconnections within the CPU chip
Buses that form the backplanebackplaneExternal CPU busPeripheral control interface (PCI) busAccelerated graphic processor (AGP)Accelerated graphic processor (AGP)Industrial standard architecture (ISA)Industrial standard architecture (ISA)
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Typical bus and port connectionsTypical bus and port connections
Bus interface bridgesBus interface bridges connect different bus types
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Bus CharacteristicsBus Characteristics
ProtocolProtocolDocumented agreement for communicationSpecification that spells out the meaning of each line and each signal on each line
ThroughputThroughput, i.e., data transfer rate in bits per second
Data widthData width in bits carried simultaneously DistanceDistance between two end points Type of signalsType of signals: unique/specialized or
shared Addressing capacityAddressing capacity Etc.
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Buses Inside a ComputerBuses Inside a Computer
Data busAddress busControl bus
MemoryI/O Module
I/O Device
CPU
Motherboard• Many
configurations possible
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Data BusData Bus
Carries data between the CPU and memory or I/O devices
Bi-directionalData transferred “out of” the CPU for write operationsData transferred “into” the CPU for read operations
Typical sizes: 8, 16, 32, 64 lines Signal names:
D0, D1, D2, D3, etc.
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Address BusAddress Bus
Carries an address from the CPU to Memory or I/O devices
UnidirectionalThe address is always supplied by the CPU
(There is one exception to this, which we’ll discuss later.)
Typical sizes: 16, 20, 24 lines Signal names:
A0, A1, A2, A3, etc.
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Control BusControl Bus
Collection of signals for coordinating CPU activities Each signal has a unique purpose Typical sizes: 10-20 lines Signals are output, input, or bi-directional Typical signals
CPUPlug-in I/O (serial and parallel ports, sound cards, disc drives
Lines are non-specialized: carry addresses and data, labeled AD00 to AD31 (or AD63)
Additional lines: control and power lines
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InstructionsInstructions
InstructionDirection given to a computerCauses electrical signals to be sent through specific circuits for processing
Instruction setDesign defines functions performed by the processorDifferentiates computer architecture by the
Number of instructionsComplexity of operations performed by individual instructionsData types supportedFormat (layout, fixed vs. variable length)Use of registersAddressing (size, modes)
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InstructionInstruction ElementsElements
OPCODE: task Source OPERAND(s) Result OPERAND
Location of data (register, memory)Explicit: included in instructionImplicit: default assumed
OPCODE SourceOPERAND
Result OPERAND
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Instruction FormatInstruction Format
Machine-specificMachine-specific template that specifies Length of the op code Number of operands Length of operands
Simple 32-bit Instruction Format
28 = 256 different instructions
224 = 16 million memory addresses
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Instruction Format: IBM MainframeInstruction Format: IBM Mainframe
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Instruction Types (1 of 2)Instruction Types (1 of 2)
Data Transfer (load, store)Most common, greatest flexibilityInvolve memory and registersWhat’s a word ? 16? 32? 64 bits?
ArithmeticOperators + - / * ^Integers and floating point
Logical or Boolean Relational operators: > < = Boolean operators AND, OR, XOR, NOR, and NOT
Single operand manipulation instructionsNegating, decrementing, incrementing
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Instruction Types (2 of 2)Instruction Types (2 of 2)
PrivilegedPrivilegedSecurityAccess controlNot available to the application programs
Bit manipulation instructionsFlags to test for conditions
Shift and rotate Program control Stack instructions Multiple data instructions I/O and machine control
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Register Shifts and RotatesRegister Shifts and Rotates
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Program Control InstructionsProgram Control Instructions
Program controlJump and branchSubroutine call and return
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Stack InstructionsStack Instructions
Stack instructionsLIFO method for organizing information Items removed in the reverse order from that in which they are added