1 Lanwave Technology, Inc. SATURN Silicon Architecture.

1

Lanwave Technology, Inc.

SATURN Silicon Architecture

LanwaveTechnology, Inc. © 2001 2

SATURN Chip Set Goals

10,000 feet consumer cordless phone 100 dollars on the shelf 10 hours talk time >10dB processing gain


System Block Diagram

RF Unit

Keyboard& Display

G.721Codec

TelcoInterfaceMicrocontroller

PowerCircuit

SATURN

L9002VX2

900/2.4GHz Digital Cordless Telephone & Wireless PBX


Typical Cordless Telephones

CPU4-bit

ReceiverMic46/49MHz

Single chipCT controller

CPU4-bit

ReceiverMic

LCD

SATURNL9002VX2

CODECRF

circuit

battery mgmt

46/49/900MHzAnalog

900MHz/2.4GHzDigital Phone


Silicon Architecture

De-spreader

Spreader

data out FIFO

data in FIFO

ErrorDetection

ProgrammableClock Generator

General PurposeTimer

ProgrammableProtocol

Controller

DataEncryption

MPUInterface

I/O PortExpansion

To Codec

From Codec

RF

CPUBus

I/OPort

L9002VX2 SATURN

Power Management

Status


Silicon Architecture

De-spreader

Spreader

data out FIFO

data in FIFO

ErrorDetection

ProgrammableClock Generator

General PurposeTimer

MPUInterface

I/O PortExpansion

RF

CPUBus

I/O Port&

CoprocessorExtension

L9002DX2 SATURN

Power Management

Status

ProgrammableProtocol

Controller

DataEncryption


Coding

VoiceCoding

SymbolCoding

LineCoding

OrdinarySpeech

RadioWave

Coding Scheme / Standard

Coding Rate

Compression

Frequency/ Bandwidth

ADPCMCCITT G.721ANSI T1.301

8K samples/second8-bit/sample

50%

32Kbps

Code DivisionSpread Spectrumwith Time-Division

Duplex (TDD)

3-bit/symbol32-chip/symbol

10.667 chips/bit+10.3dB processing gain

1.365M chips/second

GMSK/MSK

1-chip/line code

1.5Hz per chip

2.048MHz pervoice channel

ADC PCMPN code

Spreading


SATURN Wireless Modem Chip

Telegraphing

Framing

Protocol

Symbol to alphabet (PN) code translation

Recognition Encryption Error control

Network flow control


Telegraph with Color Filtering What is CD/SS™ ?

..110100110111000111101011000111100010101..

110 011 000 111 101 100 000

* Code Division/Spread Spectrum, or CD/SS is a registered trademark of Lanwave Technology, Inc.


Lanwave 1-bit DSP CoreBenefits of Code Division Spread Spectrum (CD/SS™)

“Morse Code” modem - 8 symbol alphabet - Alphabet selection optimized by DSP criteria - >10dB processing gain for Part 15 compliance

1-bit DSP allows non-linear RF design- Class C power amplifier - No

automatic gain control - No I-Q mis-matching issues

Simplified timing reference - Independent clocks in each node


Implementation

Each symbol (alphabet) is assigned a 32-bit color code (8x32chip PN sequence)

Symbol boundary alignment - Search&Lock - programmable thresholds

Color separation - Minimum Hamming distance - parallel processing design - VMSK mode – Morse code with pulse width modulation

Framing, Error Protection, Encryption - TDD, Parity/BCH, (11,3)MRL Encryptor - programmable


Spreader & De-spreader

ProgrammablePN Sequences

PN SequencesEncoder

PN SequencesDecoder

TransmitSymbol

ReceivedSymbol

Transmit chip(to TX_DATA)

Received chip(from RX_DATA)

Spreader

De-spreader

1-bit

1-bit

4 sets of PN code (PN000, PN001, PN010, PN011)Opposite phase encodes data field conjugate

3-bit dataSelect 1 out of 8 sequences

Parallel correlation with 8 possible PN sequences

Select 1 out of 8 data patternbased on correlator output within the chip detection window


Framing for Flexible Protocol Data Encapsulation, Encryption, Error and Flow Control

Preamble: 18 symbols of “000”. 54 bit time.

UID/UST field 18 symbols (Fully encrypted)UID: User definable ID field - 24 bit time. 22-bit user programmable.UST: Command & Status. 24-bit (3 bytes) per frame.CRC: 6-bit Error detection code for the UID/UST subframe.

Subframes: 18 encrypted symbolsData: 48 bits CRC: 6-bit

Preamble UID & UST Subframe 1 Subframe 4Subframe 2 Subframe 3

110 011 000 111 101 100 000..


Digital Signaling

Acquisition Burst Frame (abf)

Empty Burst Frame (ebf)

Data Burst Frame (dbf)

Preamble UID&UST

Preamble UID&UST

Preamble UID&UST

UIDx2 .. UIDx2

data data..

..scrambles

Protocol & Data Frames


Link Acquisition Sequence

Training sequence

Base Station Mobile Station

* Sends abf to all mobile stations * abf detected by all mobiles with same UID ASSERT LOCK* Mobile respond with abf

* Base ASSERT LOCK* responds with ebf

* Mobile receive ebf ASSERT RLOCK* Respond with ebf

* Base receive ebf ASSERT RLOCK* commence dbf transmission

* Mobile receive dbf* commence dbf transmission


Retraining Sequence

Station A Station B

* Sends dbf * Receiving party failed to correctly receive dbf* Check STICKY bit counter. If not exceeded:* Continue to send dbf

- OR -

* Receives dbf* responds with dbf

* If STICKY bit count has been exceeded: DEASSERT LOCK, RLOCK* Sends abf

* Ignores dbf (after retraining has started.)* Continue to send abf

* Receives abf - loss of data frame* Check STICKY bit counter. If not exceeded:* Continue to send dbf

* STICKY bit counter exceeded.* initiates training sequence DEASSERT LOCK. RLOCK* Base unit takes over at this point* Sends abf

Unlocking & Relocking

Relocked

Unlocked

* Base unit takes over at this point.* Standard training sequence starts


Multicasting

Base Station Mobile Station

* Sends abf to all mobile stations * abf detected by all mobiles with same UID Software examines Link_Status byte - implemented in UST. Alert paging request to upper layer software. At the control of upper layer timing, deassert Listen_only mode bit. * Mobile responds with abf* Base

* responds with ebf* Send updated Link_Statue byte

* Base * commence dbf transmission

* Active Mobile responds with ebf

* Mobile respond with dbf

* Non-active Mobiles continue to back off from information in the Link_Status byte.

* Hardware mechanism to avoid mutual detection among mobiles, as well as contention resolution due to simultaneous mobile responses are implemented in SATURN chip design.* Implementation of Link_Status byte, and back-off mechanism is dependent on upper layer software.


Link_Status Byte

A B S X N[3:0]

A: 1: unit asserted LOCK0: un-LOCKed

B: 1: Frame initiated from Base Unit (master)0: Frame initiated from Mobile Unit (slave)

S: reserved

X: 1: Frame Error detected in the last received frame0: Last frame reception normal

N[3:0] 4-bit subgroup ID (units sharing the same UID)

UST[23:16]* UST[15:8] UST[7:0]

* Suggested implementation for multi-handset systems. Other implementations are possible.


Time Division Duplexing

Transmit Frame

Transmit FrameReceive Frame

Receive Frame

3ms

6ms

handset receiver output

telco line signal

Transmit Frame

Receive FrameBase Unit

Handset

Voice transmission delay = Receive frame (6 subframes) + G1 + G2 + Transmit preamble & control (2 subframes)= 4.313 ms (at 19.2MHz Mclk. Reduced to 2.15ms at 38.4MHz Mclk.)

G1 G2


System Interface

HardwareBus Interface Unit

SoftwareMemory Map

MPUInterface

AD[0:7]

CS#

RD#WR#ALE

0x00

0x47

CSR1

CSR20x01


Status Output Signals

Interrupt

&

StatusGeneration

StateMachine

INTR#

LOCK

RLOCK

CER#

ID_DET#

Active low Interrupt for CPU processing.

Indicate the state of the TDD (time division duplex) machine. See Training & Retraining sequence timing for details.

Active low when CRC error has been detected.

Active low when a valid UID has been detected in the prior frame.


Interrupt Classification

Pr U S1 S2 S3 S4

Transmit Frame Receive Frame

Transmit End

Receive End

Subframe

INTR#

Frame Error

(TND=1, RND=0, SUBF=1) (TND=0, RND=1, SUBF=1)

(TND=1, RND=0, SUBF=0)

(TND=0, RND=1, SUBF=0)

(FER=1, others undefined)


Voice Mode Implementation

Pr UID/UST

Transmit Frame Receive Frame

Receive End (RND)

INTR#

Frame Error(FER)

DATA

An example: Voice Mode implementation


Clock Generation Unit

ClockGeneration

Unit

OSC_IN

OSC_OUT

OSCEN#

CLK_OUT

CLK_IN

CHIP_EN

CPU_CLK

Independent external oscillatorcontrol circuit. Not affected bySATURN Reset or Power Downmodes.

SATURN clock input

Divide down clock for external CPU

Enables normal processing. Reset to low to enter Idle Mode.


ADPCM Codec Interface

ADPCMInterface

COD_SYN

COD_CLK

DR

DT

8KHz

1.2MHz


RF Interface

TX_ENV

RF_PWR

PLLSW

ANT_SW

TX_DATA

4.0us 4.0us

4.0us extensionof last chip*

Transition at Received End only - synchronous with PLLSW

470us - typical

RFInterface

* Control signal window is inversely proportional to input clock. 4.0us is calibrated at 19.2MHz. ** Connect BSYNC_IN to BSYNC_OUT for single master operation. See details in the data sheet for multi-master timing.

BSYNC_IN**

BSYNC_OUT**


I/O Expansion Block

I/O PortExpansion

A

B

C

D

PA[7:0] 2mA Totem pole outputs.bit and byte addressable.

PB[3:0] 4mA Totem pole outputs. Power up to high. PB[7:4] 4mA Open drain outputs.

bit and byte addressable

OEA# Port A output enable. Internal weak pull up.

PC[7:4] Inputs with internal weak pull up*PC[3:0] Inputs with internal weak pull down

byte addressable only

PD[7:0] Bi-directional I/O portbyte addressable only. Power up to input mode.

. Power up to high.

* Pull-up/down resistors are typically 50K ohms.


Wakeup Monitor

Input edge detection of Port C pins

Wakeup = PC0 + PC1 + PC2 + PC3 + /PC4 + /PC5 + /PC6 + /PC7

Unaffected by power down modes.


Register Map Organization

Functional

0x1F

CSR1CSR2

Code Map

0x20

0x2F

PN000[7:0]

PN000[15:8]

I/O Expansion

0x30

0x47

Port A bit_0 output

PN011[31:0]

* SATURN CS# pin must be asserted low during register access.

UST[7:0]UST[15:8]UST[23:16]

UID[7:0]UID[15:8]UID[21:16]

CPU_CLKTransmit FIFOReceive FIFOCRC field I/OReceive SNREncryption RegSticky_bit RegSearch & Lock Reg

0x00

0x10PN001[31:0]

PN000[23:16]

PN000[31:24]

PN010[31:0]

Port A byte outputPort B byte outputPort C byte inputPort D byte I/OPort D I/O dir.Gen Purpose Cnt LGen Purpose Cnt H

0x40

Port A bit_1 output

Port A bit_7 output

Port B bit output0x380x24

0x28

0x2C


I/O Expansion

0x30

0x47

Port A bit_0 output

Port A byte outputPort B byte outputPort C byte inputPort D byte I/OPort D I/O dir.

Gen Purpose Cnt LGen Purpose Cnt H

0x40

Port A bit_1 output

Port A bit_7 output

Port B bit output0x38

Port A, B bit outputs*: Write to target control register with corresponding bit location set to desired output.

Port A, B, C & D byte I/O*: Memory mapped addresses. Port D I/O direction is controlled by the polarity of the second bit of address 0x44. 0 for input, 1 for output.

General Purpose Counter: (See details in register description section.)

* All I/O accesses are unaffected by SATURN Advanced Power Management modes

0x46

0x41..0x44


Pseudo Random Code

0x20

0x2F

PN000[7:0]

PN000[15:8]

PN011[31:0]

PN001[31:0]

PN000[23:16]

PN000[31:24]

PN010[31:0]

0x24

0x28

0x2C

Usage: WriteDefault: none

PNxxx represents bit pattern xxx. Inverted code phase represent inverted bit pattern.


User ID


24-bit field. 22-bit user selectable, begin with “10”.Allowable UID error: 2 out of 8 symbols without declare loss of TDD Lock.

0x0c0x0d0x0e UID[16]UID[21]

UID[15:8]

UID[7:0]

UID[20] UID[19] UID[18] UID[17]01


Input User Status

Usage: ReadDefault: none

24-bit command and status field received from remote partner.

0x080x090x0a UID[23:16]

UST[15:8]

UST[7:0]


Output User Status


24-bit command and status field transmitted to remote partner.

0x040x050x06 UID[23:16]

UST[15:8]

UST[7:0]


CSR1

0 CRC_OVR MCAST DX/VX# ANTSW RESET START STKY0x00


STKY: Set to 1 to turn on Sticky_bit counter audio fidelity control.START: Set to 1 after software reset to start SATURN state machine operation.RESET: Software Reset. (see detail discussion in Power Up Sequence section.)ANTSW Change ANT_SW output pin polarity. Synchronized to TDD machine in hardware.

(See detail synchronization timing in RF Interface section.)DX/VX#: Select between data and voice mode operation in the SATURN.MCAST: Multicast enable bit. Valid only in SATURN data mode (refer to detail explanation

in Multicast Mode section.CRC_OVR: CRC Field Override. Valid only in SATURN data mode (refer to detail explanation

in CRC Field Override section.)


CSR1

LK RLK ADIR SUBF FER CER TND RND0x00

Usage: ReadDefault: none

RND: Received End Interrupt. Set to 1 during any Received Subframes and ReceivedEnd hardware interrupts.

TND: Transmit End Interrupt. Set to 1 during any Transmit Subframes and TransmitEnd hardware interrupts.

CER: Checksum Error. Detected checksum error in the current received subframe.FER: Frame Error. Failed to detect a valid preamble, or detected more than 2 UID

symbol mismatches out of 8, during the allotted receive frame period.SUBF: Subframe Interrupt. Set to 1 during any Subframe hardware interrupts. Set to

zero at either Transmit End or Received End interrupts.ADIR: Readback of the ANT_SW pin during the prior subframe.RLK: Remote Locked. Same meaning as the RLOCK pin signal.LK: LOCKED. Same meaning as the LOCK pin signal.


CSR2

0 0 0 SUBE TE RE M/S T/N0x01

Usage: WriteDefault: 0x00

T/N: Test / Normal bit. Set to 0 during normal operation.M/S: Master / Slave control bit. Set to 1 for Master TDD operation, 0 otherwise.RE: Enable Receive End Interrupt. When set to 1 along with SUBE, enables all subframe

as well as Receive End Interrupts.TE: Enable Transmit End Interrupt. When set to 1 along with SUBE, enables all subframe

as well as Transmit End Interrupts.

CSR2[7:5] These 3 bits must be programmed to zero.


Received SN Register

0x14

Usage: Read OnlyDefault: Clear at start of receive frame


General Purpose Timer

0x46

Usage: Write OnlyDefault: 0xffff

0x47

LH


Encryption Register

0x1e

Usage: Write OnlyDefault: 0x00 for no encryption

Encryption & Authentication method:8-bit encryption key programmed into a 11-bit primitive polynomial generator. Decryption require an identical key entered into both the transmitter and receiver units before coding and decoding starts.

Keys may be changed at any time, subject to software control.


Search & Lock Control Registers

0x12

0x1d

0x150x18..

Control Parameters

Preamble_search_chip_width (PSW)Preamble_search_threshold (PSTH)Preamble_search_symbol_length (PSL)Lock_mode_symbol_length (DLL)Lock_mode_chip_width (DLW)


Sticky_Bit Counter

na na na0x1f na 0 0 1 1

Usage: Write OnlyDefault: 0x03

4-bit field sets maximum allowable received frame error before initiating retraining


Power Up Sequence

Power up

PulseRESET pin

Hardware RESET set to high for at least 380ns with steady CLK_IN signal.

If SATURN OSC circuit is used, set OSCEN# to low. If external clock source is used, wait after clock is stable.

Write to allControl, Code

& I/O Registers(except CSR1)

Initialize control, Code Map and I/O registers.

Write CSR1

Pulse softwareReset_bit CSR1[2]

CLK_IN is stable

Set content of CSR1 with Start_bit to high, Reset_bit to low.

Operational

Set content of CSR1 Reset_bit high, then turn Reset_bit to low.

SATURN_Chip_Enable pin is set to high.


Advanced Power Management

Power up

Operational

Power UpInitializati

onSequence

Idle mode

SATURN_Chip_Enable pin is set to high.

SATURN_Chip_Enable pin is set to low.

Shut Down OSCEN#pin is set to high.

OSCEN#pin is set to low.Software Reset& write CSR1


Advanced Power Management

3.0V static CMOS, 5V tolerant Staged DSP pipeline with multiple

independent clocks Wakeup Monitor General Purpose Timer Tristated & open drain outputs


Audio Hi-Fidelity Control..1

Short TDD frame time (1.5 to 3ms) reduces telco impedance mismatch echo to non-audible levels

Sticky-bit counter eliminates retrain interruptions during bursty frame errors

Search & Lock Control parameters allow fine tuning of RF lock and audio quality under different radio environment


Audio Hi-Fidelity Control..2

When valid data is not received such as during frame error and retraining, a quiescent code pattern of “1000” “0000” is substituted into the ADPCM codec in 48 consecutive nibbles (24 bytes.)

Single bit error as reported by CER will not be blocked.


Anti-jamming Characteristics

Code Division Spread Spectrum allows for a high spreading ratio of alien narrow band noise. (32x)

Frequency diversity Space diversity Packet mode for time diversity


Space Diversity

Provide signal synchronization and SNR measurement facilities

Relinquish control to high level software algorithms

- before hanging up- random periodic- during training

& retraining


Frequency Diversity

32 full duplex, non-overlapping TDD, frequency channels in the 900MHz band

92 channels in 2.4GHz band Large number of PN code sets

available Facilities dedicated to software

control


SATURN Benefits Summary

900/2.4G digital spread spectrum cordless phone solution, partitioned to allow - easy migration from current 46/49MHz designs - gradual upgrading to feature rich phones

Advanced technology at a low cost Design tools, design house assistance Available today


Available Packages

100 pin QFP- 0.65 mm pin pitch- rectangular package

100 pin TQFP - 0.5 mm pin pitch- square package


Design Tools

SATURN Development Board Demo Software Price include license fee Auxiliary components


PN Code Selection

Orthogonality DC Run length Optimizations for SATURN

- Requirements on preamble symbol- VMSK modes

- side lobes, phase margin etc.


Optimizing PN Codes

Chipset Specific: contact Lanwave for details.


UID Selection

22-bit, no restriction on pattern Select group UID with at least more

than 3 symbol difference Implement subgroup ID in UST


Encryption Keys

11-bit primitive polynomial encryptor has 2047 maximum length

Starting point is programmable to any one of 255 locations

Use upper layer software to change keys periodically, if needed

Provide resynchronization mechanism


Search & Lock Strategy

Preprogrammed to 10,000 feet, low alien density environment

Assumed slow mobility - low Doppler, slow fade

Other environment:- high density, high alien noise

- high Doppler.- fast fading.

S-CDMA approach


AC Loop Back

Useful in manufacturing testing CPU performs FIFO access with 12

byte temporary buffer - store 2 subframes

Low latency time – 2.2 to 4.3ms Supported in both master and slave


DC Loop Back

PCM loop back at the ADPCM codec


Clock Tolerance

Designed to allow over 200ppm mismatch between master and slave

Stringent search and lock criteria will require tighter clock discrepancy

Multi handset systems shall target for less than 25ppm offset. (2.4GHz shall target for less than 15ppm offset.)


RF Issues..1

Pick modulation for easy FCC approval

MSK, BPSK, ASK, FSK, PSK compatible

TDD time gap > 400us Hybrid FH with CD/SS in SATURN-II PLL Freq_in selection - 19.2MHz..


RF Issues..2

Gain linearity is not important Phase jitter less than pi/8 is acceptable Use sharp rolloff in IF LPF (>4th order) Signals can be 3.0V compliant Maximize sensitivity & dynamic range


ADPCM Codec Selection

32Kbps at 8KHz sync PHS codecs at 19.2MHz Mclk What is its quiescent code, if any? Other compression schemes in DX2 Extra tone generator in SATURN

GPT STicKY bit


Antenna design

Second antenna in the base will improve quality during roaming

Space at quarter wavelength apart Microstrip is sufficient Fixed or variable SNR thresholds


Partition for migration

CPU4-bit

ReceiverMic

Discrete & linear

User Interface

3

46/49MHz Single chip

CT controller

CPU4-bit

ReceiverMic

User Interface

8 RD, WR, ALE

LCD

32-bit I/O expansion

SATURNL9002VX2

CODECRF

circuit

battery mgmt

•Same CPU (high volume = low cost)

•Similar code (familiar development = fast transition to manufacturing)

46/49MHz 900/2.4GHz CD/SSDigital Phone


and then add new features

CPU4-bit

ReceiverMic

User Interface

LCD

SATURNL9002VX2

CODECRF

circuit

battery mgmt

Basic model

CD/SS Advantages:•Multiple handset•Longer range•Encryption•Clarity•Cost optimized

RF design•100mW to 1000mW•Module vs. On board•Adaptive power control

Codec•ADPCM•CVSD•Vector Coding•Advanced methods

User features•Multiple handsets•Smart phones (CID, paging, email..)•Home monitoring•Wireless modem


DX/DX2 Extensions


Home Networking ApplicationsINTERNET based requirements

Personal - individual: Authentication

- exclusive: Encryption

Communication - interactive: Full Duplex- access: Multilingual (voice & data

capable) - linking: Circuit and/or Packet Oriented

Network - topology: Star (point-to-multipoint)

Bus (multipoint-to-multipoint)- protocol: Layered, Manageable & Secured


Data Mode Features

Programmable frame structure Flexible search & lock algorithm Fully programmable encryption and

error correction fields Star & network topology Optimized for typical CPU / DSP bus No extra SRAM buffering required


DX Performance

DX-20 DX-40 DX-60

Clock frequency:

4 subframes TDD

8 subframes TDD

Asymmetric TDD (2)

19.2MHz

40 Kbps

50.67 Kbps (1)

variable

40.0 MHz

83.3 Kbps

105.5 Kbps

variable

60.0 MHz

125 Kbps

158.3 Kbps

variable

(1) 8 subframes per frame. TDD cycle time 9ms. (1) & (2) Requires external framing coprocessor.


Transmit FIFO

0x16

Usage: Write no more than 2 data subframes before scheduled transmission.

Default: noneRestriction: Data mode only


Receive FIFO

0x17

Usage: Read within 2 subframe time after data have been received.



Checksum Override

0x13

Usage: Write before subframe Transmit FIFO have been filled.Read after subframe Receive FIFO have been emptied.


nana


Coprocessor Interface

I/O Expansion Block multiplexed with Coprocessor Extension Bus

Coprocessor Bus: 29 signals Allow for variations in:

- link layer architecture (#of subframes/frame, asymmetric link..) - protocols (TDD variations, Collision Avoidance) - others (Standard encapsulation, hybrid time & code spreading)

Enable smooth cost feature tradeoff


Frame Architecture Programming

Frame size modification - Preamble length. Preamble structure for target

environment - # of subframes per frame (variable frame size) - asymmetric data rate

- TDD gap time. Arrival time tolerance.

Frame types - abf, ebf, dbf & other variations that requires special

handling

Frame processing - FEC, error handling & encryption methods


Data Framing Structure

Preamble UID & UST Subframe 1 Subframe NSubframe 2

Summary: (54*N + 24) bits per frame. 22 bits User Programmable ID.Programmable TDD gap times.Programmable TDD asymmetry.


Search & Lock Control



Control Register Calculations



Lanwave Technology, Inc.Your Wireless Connection

Contact Lanwave (USA) for detailsTel: (408)-253-3883, Fax: (408)-253-6630

Local (Asia) representatives Japan distribution: Sanshin Electronics

Tel: (81)-3-54847380

Taiwan: Tonsam CorporationTel: (886)-2-2651-0011, Fax: (886)-2-

2651-0033Hong Kong & China:

Dynax Telecom Ltd. Tel: (852)-2481-0223, Fax: (852)-2481-0826

1 Lanwave Technology, Inc. SATURN Silicon Architecture.

Documents

pn code pn000

db processing gain1

possible pn sequencesselect

dsp criteria

data field conjugate3

automatic gain control

error protection

encryption tdd