1 JAZiO JAZiO ™ ™ Incorporated Incorporated www.JAZiO.com www.JAZiO.com Digital Signal Switching Technology
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JAZiOJAZiO™™
IncorporatedIncorporatedwww.JAZiO.comwww.JAZiO.com
Digital Signal Switching Technology
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What Is JAZiO?
• A small company in San Jose, CA specializing in Intellectual Property
• An I/O technology useful for transmitting data between semiconductor chips
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JAZiO Technology
• Innovative I/O switching technology• Can be used to achieve >2 Gigabits/sec/pin with
current semi and packaging technology
• Has built in timing
• Can use slow edges which take the whole bit time
• Detects data value as soon as transition occurs
• Uses differential sensing with low signal levels
• Yet uses only 1 pin per data signal
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Processor vs. Bus Performance
0
200
400
600
800
1000
1200
1400
1600
1988 1990 1992 1994 1996 1998 2000
Meg
aher
tz
Why Is JAZiO Needed?Internal/External Gap
Gap Is Growing!!!
Processor
Bus
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Conventional (Older) Technology
Receiver Has No PrecisionToo Slow for High Performance Products
Receiving ChipDriving Chip
D RTrace
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Differential Technology
Precise ReceiverBut Requires Two Pins Per Data Bit
Receiving ChipDriving Chip
D R
Traces
D
True
Comp
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Pseudo-Differential Technology
Static VREF
A Compromise
Receiving ChipDriving Chip
D R
Trace
VREF
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Full Differential vs Pseudo Differential
Differential develops very quickly and is symmetric around the DC bias of the receiver
RTrueComp
Full Differential
RDataVREF
Pseudo DifferentialDifferential develops slowly and is not symmetric around the DC bias of the receiver
Differential AchievesHigher Data Rates Per Pin
Detecting“0” or “1”
True
Comp
Bit Time
Detecting “1”
Data
VREFDetecting “0”
Bit Time
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Problems with Differential• Requires two, logically redundant, pins per bit
• To achieve a net data rate of, say, 2 Gigabits/sec/pin, each pin must switch at 4 Gigabits/sec
• The driver, the package, the PCB trace, the tester all must deal with the 4 Gigabits/sec
• PCB attenuation of signals increase with frequency (Dielectric absorption) or sqrt(f) (Skin effect)
• Differential will “hit the wall” due to signal attenuation and reach the end of its scalability while JAZiO continues to scale
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JAZiO
• JAZiO was founded in order to allow differential sensing with one pin per bit
1. Therefore data rates comparable to differential technology can be achieved with half the pins
2. Or twice the data rate can be achieved with the same number of pins
• But no pins need to switch faster than the data rate
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JAZiO Technology
Single Data Pin Per BitThree Input Receivers
Receiving ChipDriving Chip
D R
Traces
D
D
D R
Data1
DataN
Voltage/Timing References (VTR)
True
Comp
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Differential Sensing with One Pin Per Bit
• In full differential systems:– Some signals go high and each has a complement going low
– Some signals go low and each has a complement going high
• JAZiO provides: – One VTR signal to stand in for all the complements going
low
– A complement VTR to stand in for all the complements going high
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16 Bits of Full Differential
VTRs are Voltage and Timing References
VT
R
R
D0
VT
R
R
D15
CL
KC
LK
R
D0
D0
R
D15
D15
16 Bits of JAZiO
34 High Speed Pins 18 High Speed Pins
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JAZiO Solution
SteeringLogic
DataOutput
VTR
DataInput
VTRB
A Dual Comparators are used
In cases 1 and 6 Comparator A makes a differential comparisonIn cases 2 and 5 Comparator B makes a differential comparisonIn the other four cases Data Input does not change
Data is driven coincidentally with Voltage/Timing References
DataInput
VTR
VTR
One Bit Time
Provide alternating Voltage/Timing References switching at the data rate
Next Bit Time
8 different combinations of VTR and Data Input
712
3
4 8
56
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Steering Logic
The trick is to know how to select between Comparators A and B and what to do when Data Input does not change
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Steering Logic
• Generate Steering Logic signals (SL and SL)• Use them with Data Output from previous Bit Time to
select between Comparators A and B
• Also use them for data latching
SL
SL
ReceiverOutput
XORin
inout
XORin
in
out
Data Input
VTR
VTR A
B
VTR
VTR
VTRLatchingSystem
LatchedOutput
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DataOutput
SL
Initializationor
Receiver Enable
SL
VTR
VTRDataInput
DataInput
XOR
XOR
55 Small Transistors Per BitNo PLL/DLL Required
No die size penalty!!!
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The receiver cell is: 22um x 55um
(Including routing channels)
The pad cell is: 70um x 80um
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Time Domain
Decision is made in the Time Domain rather voltage domain
VTR
DataInput
First Look forchange
Determine no-change and
switch toComparator B
0.5V
SL
SL
DataOutput
XORin
inout
XORin
in
out
Data Input
VTR
VTR A
B
VTR
VTR
VTR
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JAZiO™ Receiver OperationA
SL
SL
XOR-B
DataOutput
in
in
in
inout
out
Data Input
VTR
VTR
B
VTR
VTR
VTR
XOR-A
TheNo-change
Cases
Initialize 0 1 1 0 0 1DataInput
DataOutput
VTRVTR
SL
SL
CompA
CompB
XOR-B
XOR-A
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vtr
Data Input
xnora Xnorb
Data Output
Time (nS)4 5 6
0
1
1.8
Vol
tage
(V
)
4nH Package
Break-Before-Make Break-And-Remake
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Data Skew at Receiver
Simulations show that width of Skew Band can be up to 40% of bit time
VTR
DataInput
500mV+ 100mV
- 150mV RecommendedSkew band
1.25V/ns
Bit time = 0.5ns
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XORs ProvideReceiver Monitor
SL
Initializationor
Receiver Enable
VTR
VTRDataInput
DataInput
DataOutput
SL
XNORA
XNORB
Rec
eive
rM
onito
r
MON A
MON B
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XORA
XORB=Low
Break &Remake
Break &Remake
VTR & Data Marginally
Aligned
XORB
XORAFalse Select False SelectVTR & Data
Poorly Aligned
XORA=High
XORB=Low
VTR & Data Well Aligned
XOR Waveforms with Alternating Data Pattern
Monitoring Alignment
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Advanced Aligning Techniques
• Monitors provide information on alignment between Data and VTRs
• Simple means for analyzing interface margins at operating frequency
• Monitor information can be fed back to Programmable Delays to improve alignment and can also be used for at speed testing
Driver Programmable
Delay JAZiO
Receiver Latch
One Data Bit
Drivers Programmable
Delay SL
GeneratorVTR, VTR-
MONB
MONA
Driving Chip Receiving Chip
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data_in0
vtr
sl slb
vtrb
data_out 0
SIG
NA
LS
F
RO
M
PA
DS
xora
xora
xorb
xora
xorb
xora xo
rb
xorb
data_in1 data_in2 data_in3
data_out 1 data_out2 data_out 3
4 Bit JAZiO Receiver From Test Chip
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4-bitJAZiO Receiver
4-bitJAZiO Receiver
4-bitJAZiO Receiver
4-bitJAZiO Receiver
4 of 16Serial to Parallel
4 of 16Serial to Parallel
4 of 16Serial to Parallel
4 of 16Serial to Parallel
Latch (latching at ¼ the data rate)
data
_in
0
data
_in
1
data
_in
2
data
_in
3
data
_in
4
data
_in
5
data
_in
6
data
_in
7
data
_in
8
data
_in
9
data
_in
10
data
_in
11
data
_in
12
data
_in
13
data
_in
14
data
_in
15vtr
vtrb
16 JAZiO™ Receivers From Test Chip
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Package & ESD Model
Low Pass Filter
0.6pf
2nH 0.24
Lead frame
0.6pf
2nH 0.2
Bond Wire
1pf
N-Ch Clamp
P-Ch Clamp
0.1pf
Pad0.1pf
200
Cint
ToReceiver
Input Protection Resistor
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Simulation at 2Gb/s
Middle of transmission line Package inductance 2nH
Data Output
VTR
Data Input
Time (nS)5 6 7 8 9
0
1
1.8
Vol
tage
(V
)
Data Output
VTR
Data Input
Time (nS)5 6 7 8 9
0
1
1.8
Vol
tage
(V
)
At Pin
AtReceiver
Input
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Applying JAZiO Technology• JAZiO is the physical I/O layer only
– JAZiO provides no protocol– Works with any protocol– Like good tires make any car better
• Easy to use– No die size penalty– No PLL/DLL or special semiconductor technology– Low Power
• Can be used anywhere that fast switching, low power, and pin efficiency is useful
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How Can JAZiO Be Used?• JAZiO is “essentially” an Open Standard• All technology is publicly visible w/o NDA• Anyone can see it, study it, simulate it, design it in,
build test chips, build prototypes and license before selling products
• Users can develop their own enhancements around JAZiO technology
• Patents have been issued and are ready for licensing
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Summary
• Achieves high performance, low power, high robustness
• JAZiO requires no die size penalty and saves package cost
• JAZiO is available to everyone at low cost and applies to any application
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