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Processor #1
Processor #1
Processor #1
Processor #P
Memory #1
Memory #2
Memory #3
Memory #M
Peripheral #1
Peripheral #2
Peripheral #3
Peripheral #P
IO #1
IO #2
IO #3
IO #N
Interconnection network
•
• accessed
• shared
• power managed
Uneven wire lengths between send and receive nodes
Bound to cause skew between them
Designer need to design protocols addressing worst case skew times
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Data transfermemoryCo-processorData transfermemoryI/O
Graphics operationsCo-processorCPUData transferI/OCPU
Fetching code or datamemoryCPUdescriptionslavemaster
A bus transaction (or bus cycle) includes two parts:Issuing the command and address and transferring the data
The master starts the bus transaction through command & addressThe slave is the one who responds to the address by:
Sending data to the master upon request
Receiving data from the master
Bus
Master
Bus
Slave
Master issues command
Data can go either way
AMBA: Advanced Microprocessor Bus Architecture‐ Family of ARM’s interconnect systems
High PerformanceARM processor
High-bandwidthon-chip RAM
HighBandwidth
ExternalMemoryInterface
DMABus Master
APBBridge
Timer
Keypad
UART
PIO
Adv. High-performance Bus (AHB)
Adv. Peripheral Bus (APB)
High PerformancePipelinedBurst SupportMultiple Bus Masters
Low PowerNon-pipelinedSimple Interface
• 1 unidirectional address bus (HADDR)
• 2 unidirectional data buses (HWDATA,
HRDATA)
• At any time only 1 active
data bus
centralized arbitration / decode
HWDATA
Arbiter
Decoder
Master#1
Master#3
Master#2
Slave#1
Slave#4
Slave#3
Slave#2
Address/Control
Write Data
Read Data
HADDR
HWDATA
HRDATA
HADDR
HRDATA
Multiplexed masters Multi‐layered masters
New AXI4 AMBA standards feature ‐ multi‐layering, simpler handshaking and burst trans.‐ Higher performance
PCI: Peripheral component interconnectionHigh‐speed shared bus
Intel released PCI in public domain in 1990s
Bit/speed width depends on the Peripherals (eg: 32, or 64 bits at 66MHz)
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1
2
3
4
5
6
7
0 1 2 3 4 5 6 7
0
1
2
3
4
5
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NoCconnected cores
Software
Transport
Network
Wiring
Separation of concerns
Queuing / RoutingTheory
Traffic Modeling
Architectures
Networking
Can borrow much from computer network practices
Buffer
Buffer
LOGIC
LOGIC
Routing
Arbitration
Buffer
LOGICNorth
South
East
Buffer
LOGIC
West
Buffer
LOGIC
Core
Buffer
Buffer
LOGIC
LOGIC
Buffer
LOGICNorth
South
East
Buffer
LOGIC
West
Buffer
LOGIC
Core
FIFO controller
Data Packetiser or Data De‐packetiser
FIFO controller
Router in(a packet)
Router out(a packet)
Packet
Data
Core in(a packet)
Core out(a packet)
Question: what motivated the designer to choose AHB crossbar switch?
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