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CoE
115
Lectur
e1
IntroductiontoM
icroController
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Z8
0Microprocessor-based
System
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Microcontroller
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Micro-C
vsMic
ro-P(pinouts)
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Microcontroller
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ProcessorA
rchitecture
TheRISCarc
hitecture
s
imple,hard-
wiredinstruc
tionswhichoftentake
o
nlyoneora
fewclockcy
clestoexecute.
s
mallandfixedcodesize
withcomparativelyfew
instructionsa
ndfewaddressingmode
s.
e
xecutionofinstructionsisveryfast,b
utthe
instructionse
tisrathersimple.
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ProcessorA
rchitecture
TheCISCarc
hitecture
c
haracterized
byitscomp
lexmicrocod
ed
instructionsw
hichtakemanyclockcyclesto
e
xecute.
o
ftenhasala
rgeandvariablecodesizeandoffers
m
anypowerfulinstruction
sandaddressingmodes
.
I
ncomparisontoRISC,C
ISCtakeslongerto
e
xecuteitsin
structions,buttheinstruc
tionsetis
m
orepowerful.
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Microco
ntrollerCompone
nts
Mem
ory
E
achmemory
locationhas
a
specificadd
ress
W
emustsupplyan
a
ddresstoaccessthe
correspondinglocation
R
/Wallowsustoselect
readingorwriting
V
arioustypes
ofmemory
fordifferentfu
nctionsand
speeds
Mem
orylocation0
Mem
orylocation1
Mem
orylocationn-1
Mem
orylocationn-2
address
data
r/w
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Microco
ntrollerCompone
nts
Mem
ory
ReadOnlyMem
ory-Memorythatcanonlyberead
Holdstheprogra
mcodeforamic
roprocessorused
inan
embeddedsyste
mwherethecodeisalwaysthesa
meandis
executedeverytimethesystemisswitchedon
ComputerBIOS,boot-upinformation
O
thertypesofR
eadOnlyMem
ory
ErasableProgra
mmableReadOn
lyMemory(EPROM)Similarto
ROMbutcanbe
erased(exposur
etoultravioletlight)and
reprogrammed
ElectricallyEras
ableProgrammab
leReadOnlyMe
mory
(EEPROM)morecommonthatEPROMbecause
itcanbe
erasedbythem
icroprocessor
FlashMemory,F
erroelectricRAM
(FRAM),MagneticRandom
AccessMemory
(MRAM)
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Microco
ntrollerCompone
nts
Mem
ory
Ra
ndomAccessMe
moryusedtostoredynamicdata
when
processorisrunning
Holdsprogramcodeanddataduringexecution
Canbeaccessesinanyrandomorde
runliketakesord
isks
So
metypesofRAM
StaticRAM(SRAM
)Usestransistorstostorebits,fastSRAMisusedfor
cache
DynamicRAM(DR
AM)Usescapac
itorstostorebits,m
ustberefreshed,
smallerandcheap
erthanSRAM
FastPageMode(FPM),ExtendedDa
taOut(EDO)
SynchrounousD
RAM(SDRAM)intr
oducedin1997andreplacedmost
DRAMincompu
tersby2000
DoubleDataRa
te(DDRSDRAM)u
sesbothclockedges
foundtodayin
mostcomputers
DirectRambusDRAM(RDRAM)so
mewhatofaflop
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M
icrocontrollerComponentsCPU
Smartpart
Processesinstru
ctionsanddata
Allthepartsofa
microprocessor
Registersfast
memoryusedto
st
oreoperandsandother
in
formation
Conditionregister
positive/negativeresult
Exceptionregist
eroverflow
condition
Loopcountregister
Load-storearchitecture
R
egister0
R
egister1
Re
gistern-1
da
ta
address
r/w
CPU
ALU
in
st
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ProcessorCore
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Microcon
trollerCo
mponen
tsI/O
C
onnection
totheouts
ideworld
E
xamples
AnalogtoD
igitalConve
rter
TemperatureSensor
Display
CommunicationsCircuit
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M
icrocontrollerComponentsBUS
G
roupofwiresusedtotra
nsportinform
ation
C
PUtoMemo
ry
Addressbus
Databus
C
PUtoI/O
Portmapped
I/Ousedwh
enaddressspaceislimited,
specialinstru
ctionsareneededforI/O
Memorymap
pedI/OI/Olookslikememorylocations,
easiertouse
andcommoninReducedIns
tructionSet
Computing(R
ISC)
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Mach
ine-leve
lExecu
tion
Mach
ineinstruction
:
Abundleofbin
arybitswithcerta
informats
Onlyasksfors
impleoperations
Assembly:textualnotationsofm
achineprogram
Exam
ple:
c=a+b;
Mach
ineexecution:
r1mem(a
)
r2mem(b
)
r3ADDr
1,r2
mem(c)r
3
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Mach
ine-LevelExecu
tion
Data
In
struction
Stack
I/O
address
mem
ory
CPUF
etchinst Store
Load
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Majo
rInstructionTypes
Arithmetican
dlogic:Add,subtract,multiply,
divide;and,
or,not,xor
Dat
amoveme
nt:transfe
rdatabetw
een
registersand/ormemories
Control:Bran
chesandjumps
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Proc
essorPerformance
CPUTime
=#Cycle
sCycleTime
=#InstructionsC
PICycleTime
CPI:Cyclesperinstructio
n