1 EMT 251/4 INTRODUCTION TO IC DESIGN Mr. Muhammad Imran bin Ahmad 019-4267902 [email protected] Profesor N.S. Murthy
Jan 01, 2016
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EMT 251/4 INTRODUCTION TO
IC DESIGN
Mr. Muhammad Imran bin Ahmad [email protected]
Profesor N.S. Murthy
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Course Outcome
CO1: Students will be able to design and simulate logic circuits at transistor level using schematic entry as well as netlists format.
CO2: Students will be able to produce the layout design of a circuit based on the design rules specified.
CO3: Students will be able to analyze CMOS transistor characteristics.
CO4: Students will be able present their mini project individually in a viva session.
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Laboratory (IC Design Lab, 9th Floor,
KWSP)
Lab 1, Week2 : Netlist Lab 2, Week3 : Schematic designLab 3, Week4 : Layout designLab 4, Week5 : DRC and LVSWeek6 – 13 : Mini ProjectWeek14 : Demo & Viva
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CAD Tools
Mentor Graphics software (Linux OS): Text Editor - Netlist Design Architect - Schematic IC Station - Layout Xelga - Simulation Calibre DRC - DRC Calibre LVS - LVS
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Reading Lists1) Neil H.E. Weste and Daid Harris, CMOS VLSI Design- A
Circuits and Systems Perspective, Prentice Hall, 2005. Text Book
2) Kang, Sung-Mo and Leblebici, Yusuf, CMOS Digital Integrated Circuits- Analysis and Design, McGraw-Hill, 2005.
3) Hodges, David A. et al, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, Mc-Graw-Hill, 2004.
4) Uyemura, J. P., Introduction to VLSI Circuits and Systems, John Wiley, 2002.
5) Rabaey, J. M. et al, Digital Integrated Circuits – A Design Perspective, 2nd Edition, Prentice Hall, 2002.
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Evaluation
Final Exam – 50%Course Work – 50%
Test 1 = 10 % Test 2 = 10 % Lab Test = 15 % Mini project = 15 %
(viva,demo,paper)
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EXPECTATIONS
Attend classes and labs. Find out what you’ve missed if you’re
absent. Come earlier than the
lecturer/engineers. Log on to portal regularly. Ask lecturer/engineers whenever have
any problems related with the subject.
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Moore’s Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
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Moore’s Law
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Scaling….
Technology shrinks by 0.7/generation With every generation can integrate 2x more functions
per chip; chip cost does not increase significantly Cost of a function decreases by 2x But …
How to design chips with more and more functions? Design engineering population does not double every
two years… Hence, a need for more efficient design methods
Exploit different levels of abstraction
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Design Metrics How to evaluate performance of a digital
circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function