1 Electronics for RICH Detectors Veljko Radeka, BNL RICH 2004 Workshop • Developments in electronics: CMOS scaling • The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance • A neglected technology: Interconnections • Matching electronics and detector
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1 Electronics for RICH Detectors Veljko Radeka, BNL RICH 2004 Workshop Developments in electronics: CMOS scaling The quest for single electron sensitivity:
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1
Electronics for RICH DetectorsVeljko Radeka, BNLRICH 2004 Workshop
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
2
Acknowledgements:
• Gianluigi De Geronimo
• Paul O’Connor
• Sergio Rescia
• Pavel Rehak
• Craig Woody
• Bo Yu
… my BNL colleagues.
3
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
4
CMOS Technology Roadmap
Year 1991
1993 1995 1997 1999 2001 2004 2008
Min. feature size [nm]
800 500 350 250 180 130 90 60
Oxide thickness [nm]
16 11 7.7 5.5 4 2.7 2.2 1.8
Power supply [V] 5 5/3.3 3.3 2.5 1.8 1.5 1.2 0.9
Threshold voltage [V]
0.7 0.65 0.6 0.5 0.38 0.28 0.22 0.17
Cutoff frequency [GHz]
12 19 28 40 65 75 100 165
• Driven by digital VLSI circuit needs• Goals: in each generation
– 2X increase in density– 1.5X increase in speed
5
CMOS scaling:
10
100
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
Vo
lts
kT
/q
Supply voltage
Threshold voltage
10
100
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
Vo
lts
kT
/q
Supply voltage
Threshold voltage
0
5
10
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
t ox/d
Si
0
5
10
0.25 0.18 0.15 0.13 0.1 0.07Lmin, m
t ox/d
Si
Oxide Thickness:
6
Threshold mismatch due to discrete dopant distribution
0
500
1000
0.25 0.18 0.15 0.13 0.1 0.07
Lmin, m
Do
pa
nt
ato
ms
pe
r M
OS
FE
T
0
500
1000
0.25 0.18 0.15 0.13 0.1 0.07
Lmin, m
Do
pa
nt
ato
ms
pe
r M
OS
FE
TVT
3D p-MOSFET simulation with stochastically placed dopants
D.J. Frank, IBM J. Res. Dev. 46, 235-244, Mar./May 2002
7
But: Gate tunneling current !!!
• Gate current expected to increase 100
– 200 x per generation below 0.18 mm
• Jox ~ 100 A/cm2 projected for Lmin = 0.1
mm generation with nitrided SiO2
• Considered tolerable for digital circuits
(total gate area per chip ~ 0.1 cm2)
• Typical CSA input FET would have
IG ~ 1 - 10 µA; ENCp ~ 2000 - 7000
rms e- at 1 µsec
• Good for radiation resistance – bad
for ENC.
SiO2 gate leakage current (Lo et al., Electron Dev. Letters 1997)
8 LHC Boston Sept 04 PA
FPGAs - Thirteen Years of ProgressFPGAs - Thirteen Years of Progress
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
14
15
Single Electron Detection and Timing vs Avalanche Gain Gav
Detection (Yes/No): Gav ≥ ~ 10 ENC/qe
“Common” Timing: Gav ≥ (ENC/qe) (tp/σt) ; tp = peaking time after shaping > signal current width
Optimum timing:
----------------------------------------
1. Coarse timing: ~ 1 – 2 ns , for tp = 20ns → Gav ≥ 10 ENC/qe
= 100 ns → ≥ 50 ENC/qe
2. Precision timing: ~ 100 – 200 ps , for tp = 20 ns → Gav ≥ 100 ENC/qe
ENC = ?(Note: Optimum filter for timing is different from opt. filter for charge measurement)
16Power Pd is in input leg only. Add minimum 30µW for signal processingPower Pd is in input leg only. Add minimum 30µW for signal processing
10-14
10-13
10-12
10-11
10
100
1000
Pd=1mW
Pd=100µW
Pd=10µW
TSMC 0.25µmP-MOS, T
p=20ns
EN
Co
pt [
r.m
.s. e
lect
rons
]
Input capacitance Cin [F]
Optimum ENC vs Input CapacitanceOptimum ENC vs Input Capacitance
10 pF10 fF
17Power Pd is in input leg only. Add minimum 30µW for signal processingPower Pd is in input leg only. Add minimum 30µW for signal processing
10-14
10-13
10-12
10-11
1
10
100
1000
Pd=1mW
Pd=100µW
Pd=10µW
TSMC 0.25µmP-MOS, T
p=200ns
E
NC
op
t [r.
m.s
. ele
ctro
ns]
Input capacitance Cin [F]
Optimum ENC vs Input CapacitanceOptimum ENC vs Input Capacitance
10 pF10 fF
18
“Why is the detector capacitance so important in determining the noise performance?”
It is illustrative to express the noise performance in terms of signal and noise “energy” on the detector capacitance. From matched filter theory and the well known relations for ENC:
=transistor carrier transit time ≈ Cgs/gm ; tm= integration time ; Kf is the 1/f noise constant [Joules]; kB= Boltzmann constant.
Numerical (dimensionless) constants aw , a1/f , contain capacitance matching constraints (Cd/Cgs ratio), weighting function shape parameters, but are independent of the transistor width.
Amplifier noise energy referred to the detector capacitance is independent of the detector capacitance. The signal energy is inversely proportional to the detector capacitance. (Cd here includes stray capacitances.)
For a “gut feeling”: Charge at higher potential energy is easier to detect – 1 electron on 1 atofarad (quantum dot) is readily detectable – while not so at higher capacitances.
2 2
2
1
2 1
2 1
w B e m
f f
d
d
d
d
e
S SignalEnergy Q
N NoiseEnergy a k T t
Q
a K
CC
CC
2 2
2
1
2 1
2 1
w B e m
f f
d
d
d
d
e
S SignalEnergy Q
N NoiseEnergy a k T t
Q
a K
CC
CC
for white series noise
for 1/f series noise
VR 06/17/04
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Pixel density – detector trends
STAR TPC
PHX MVD
PHX PAD
M'pix2
EXAFS
PET
XAMPS1
barcode
LHC pixels
MAPS
LSST
DEPFET2DEPFET1
gamma cam
1E-2
1E-1
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E-1
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1998 2000 2002 2004 2006 2008 2010
Doubling every 5 monthsDoubling every 5 months
Year
pix
els
/cm
2
20
Power density
• On-detector power density is limited by cooling capability.
• Electronics for high-density detector must be extremely low power.
G. De Geronimo et al., Proc. PIXEL2002 International Workshop, Carmel, CA, 2002
22
Optimized noise vs. power
ln0.4
ln
d N
d P
(MOSFET optimized at each power level and shaping time)
Note:
4.0dP
dN
Cd = 1pF0.25 µm CMOS
10
100
1000
10 100 1000 10000
Power (W)
No
ise
(rm
s e-
)
10 ns
30
100
300
1000
3000
Shapingtime:
G. DE Geronimo, P. O`Connor
23
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
24
Detector – FE interconnect choices• board-to-backplane
– easy to test, repair– large boards possible– connector pins are failure points– coarse pitch and high capacitance (> 1pF)
• standard SMT package soldered to board (QFP or BGA)– easy to test, difficult to repair– capacitance down to 0.2 pF for small packages– board area limited by reflow oven capacity
• wirebonded chip-on-board– difficult to test, assemble, and repair– board area limited by wirebonder– fragile– low capacitance (0.1 pF)
• bump-bonded flip-chip– can match pixels with pitch from ~30 – 1000
m– difficult to test, assemble, and repair– circuitry has to fit in same area as pixel
• monolithic detector/electronics– interconnect is created as part of the detector