1 Design and Performance of a Web Server Accelerator Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, and Daniel Dias INFOCOM ‘99.

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Design and Performance of a Web

Server Accelerator

Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, and Daniel Dias

INFOCOM ‘99

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Outline Introduction System Architecture Present Performance

Measurements Present an Analysis of the

SPECweb96 Conclusions

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Introduction (1/5) The perform of Web Server is limited by 1. Copy several times across layers of software - the file system and the application - during transmission to O.S. kernel - at the device driver level 2. O.S. scheduler and interrupt processing

Too many overheads and add further inefficiencies

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Introduction (2/5) One technique for Improving the

Performance of Web Site to cache frequently requested

data at the site - Know as [Httpd Accelerators] or

[Web Server Accelerators]

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Introduction (3/5) - Httpd Accelerators differ from proxy caches -> Proxy Cache – speed up access to remote Web site -> Httpd Accelerator – speed up access to local Web site

- It’s Possible both a proxy cache and an httpd accelerator

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Introduction (4/5) Authors’ Accelerator - Run under an [embedded O.S.] -> Serve up to 5000 pages/second from

its cache on a 200 MHz PowerPC 604 -> High-performance

- Highly optimized communications stack

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Introduction (5/5)

- Provides an API -> Allows application programs to

explicitly add, delete, and update cached data. -> Allows dynamic Web pages be

cached.

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System Architecture (1/5)

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System Architecture (2/5) The Cache Operates in One or a

Combination of Two Modes: - Automatic Mode -> Cached automatic after cache misses. -> Webmaster set cache policy

parameters.

- Dynamic Mode -> Explicitly controlled by application programs. [ API functions ]

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System Architecture (3/5)

-> API for explicitly invalidating cached objects often makes it feasible to

cache dynamic Web pages Use the Least Recently Used (LRU)

algorithm for cache replacement

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System Architecture (4/5) Key Software Elements 1. Packet queue on the system card memory 2. Without performing task scheduling, task switching, or interrupts 3. No data copying takes place 4. No buffer linking is necessary. This saves the overhead if buffer linking.

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System Architecture (5/5) TCP Stack was Modified

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Web Server Accelerator Performance (1/7)

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Web Server Accelerator Performance (2/7)

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Web Server Accelerator Performance (3/7)

For a 200 MHz PowerPC 604 Processor, the theoretical capability would be 200,000,000 / 32,823 for an 8 Kbyte page which is 6093 requests per second

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Web Server Accelerator Performance (4/7)

20-40 WebStone clients / node

a. Web Serverb. Client

Ran up to 100 WebStone clients

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Web Server Accelerator Performance (5/7)

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Web Server Accelerator Performance (6/7)

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Web Server Accelerator Performance (7/7)

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Accelerator Performance on SPECweb96 (1/4)

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Accelerator Performance on SPECweb96 (2/4)

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Accelerator Performance on SPECweb96 (3/4)

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Accelerator Performance on SPECweb96 (4/4)

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Conclusions Authors’ presented the design, key

issue in the implementation and the performance of a Web Accelerator.

The Accelerator can provide high hit ratios and excellent performance for workloads similar to SPECweb96 benchmark.