1 Company Confidential Statement of Confidentiality Renesas Confidential Information The following material contains Renesas confidential and proprietary information. No part of this document may be disclosed, printed, copied, or disseminated in any form or by any means, without prior permission from Renesas Electronics America, Inc.
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1 Company Confidential
Statement of Confidentiality
Renesas Confidential Information
The following material contains Renesas confidential and proprietary information. No part of this document may be disclosed, printed, copied, or disseminated in any form or by any means, without prior permission from Renesas Electronics America, Inc.
Renesas Electronics America Inc.
Company Confidential
CSoC Sales TrainingProduct Introduction
Sudhir Mallya / Steven KawamotoCSoC Group / Computing and Communications BU
00000-A
Rev. 1.0June, 2010
Company Confidential3
Focus Segments Storage ASICs (USB3.0/SSD)
4 Company Confidential
Storage ASIC (SSD / USB3.0)
MarketUSB3.0 Device Bridge ChipsEnterprise Class SSD Controller Chips (SATA Gen 3)
Solution(Value)
Optimized chip design with single vendor interface• One stop shop with IDM Value PropositionIP and IP customization: • USB 3.0, SATA Gen 3, PCIe, Flash I/F (ONFI), UHS-2• ARM, DDR 2/3, custom I/O buffer designComplement customer ASIC/COT resources
CompetitionASICs and COTs using Foundry ecosystem • Design House, IP Vendor, Foundry, Package and Test
AdvantagesUnparalleled leadership in USB 3.0Superior Leakage current in CB55-L vs. TSMC 65nmIntegrated and deep service level
Market High end smartphone, smartbook, tablet devices
Solution(Value)
Bridge chip (between host and display module) with eDRAM frame buffer to allow Host to go to sleep when refreshing still images to save system power.MIPI-DSI and MDDI In, RGB Out (DSI and LVDS Out in development).Currently supports up to WSVGA/WXGA resolutions & refreshes display at 60fps (or more).
CompetitionToshiba, Epson. At lower end (~WVGA), also Smart Driver IC’s (driver IC’s with RAM) and Application Processors with stacked DDR.
Advantages
vs Smart driver: Availability/lower cost @ >WVGA, & low powervs App Proc: System power savingsvs Epson: edram for lower powervs Toshiba: Lower power edram and edram experience
relationships with key industry players UNH-IOL MIPI-DSI “plugfest”
participation B/Feb, very successful (next Nov/10)
Tradeshows such as CES and MWC
FPGA board emulates MIPI DSI Host Ambient light
sensor
2Lane MIPI DSI Tremolo-MPWM signal for LED
backlight control
WVGA panel
Company Confidential18
Focus Segments Intel Power Management IC (PMIC)
19 Company Confidential
PMIC Summary
MarketPMIC for Intel Moorestown and Oak Trail platformsHigh-end smartphone, handhelds, tablets, netbooks
Solution(Value)
Rapid, pain-free development PMIC Applications Center of Excellence / Collateral & Support Schematic and Layout reviewsMost robust and widely adopted solution
Competition Freescale and Maxim
AdvantagesBetter solution for large form-factors. Scalable to smartphone.Unique PMIC GUI
Target North American Customers
Major OEMs: Dell, HP, CiscoEmbedded Applications – Battery Mobile Capable• Early Adopters now, working w/ C&I disti for go-to-market plan
Most widely tested, robust PMIC solutionUnique PMIC GUI & technical supportBetter tablet features than competitionOptimized Oak Trail PMIC planned
24 Company Confidential
Overview of WW Design-insHeavily engaged in Asia
Green : Menlow UserBlue : ARM UserBlack : UnknownGrey : MRST Project cancelled
OEM = Original Equipment ManufacturersODM = Original Design ManufacturersIDH = Independent Design House
* Customers with PMIC_NDA signed Customers of Renesas Moorestown PMIC Customers of Freescale PMIC Customers of Maxim PMIC Customers of Renesas Oak Trail PMIC
Aggressively consider all opportunities regardless of LTR.
2. General CBIC business:
CB90 and older technologies: target $5M or greater LTR
CB40/CB55: target $20M or greater LTR
Besides LTR, each opportunity evaluated for– Design complexity– IP requirement/match– Schedule– Risk
28 Company Confidential
Gate Array Sales Guidelines
Product Simple Complex
LTR Guideline*
$1M LTRMinimum $250K / year75% LTR confidence
$2M LTRMinimum $250K /year75% LTR confidence
Channel Guideline
Avnet or Rockwell only Avnet or Rockwell only
CMOS-N5 All masters -
CMOS-9HD All masters -
EA-9HD - All masters
CMOS-12M SOG Type masters(uPD66211-14)
Embedded RAM masters(uPD66201-10)
LTR Guideline is based on Renesas selling price = disti cost One way to meet the LTR guideline is to raise the Renesas selling price
Additional Guidelines to Renesas Sales: Avnet business stays with Avnet Renesas will continue to encourage customers to use the Avnet model. If >$3M LTR opportunity is Renesas-generated and customer prefers, can consider
direct model as a 2nd option
Company Confidential29
Working with CSoCASIC Opportunity Profile
30 Company Confidential
Working with CSOC for CBIC & G/A Opps
Initial Opportunity Discovery by Sales Contact CSoC
Smart Grid – Sudhir Mallya Storage – Steven Kawamoto General CBIC
– East: Mark Fox– West: Sudhir Mallya
General Gate-Array:– Chris Tennant
CSOC ASIC Program Manager (PM) will manage: Technical Profile for ASIC project and opportunity evaluation Quote / Proposal creation ASIC Contracts Project Execution with CSoC Project Manager
31 Company Confidential
Initial Opportunity Discovery by Sales
Complete CBIC Business Profile Form Business Items
Customer contact info Application Schedule Volumes Target price Key issues to win Competition
Technical Major IP cores (in order to prepare for a follow-up meeting) Obtain customer RFQ (if available) Others may be gathered in the follow-up meeting with CSoC and
customer
CBIC Profile Business R32
Please see “Attachments” for CBIC Profile Form
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Technical Profile Details (Example)
= Do Not Write in this space = Required Entry = Optional Entry. This may change to yellow (required) based on other data entered
Mass Prod. DateProduct Life (years)
Creation DateCreated By
First NETLIST DateFinal NETLIST DateES Delivery DateRisk Prod. Date
Modified ByApplicationDesign Start Date
Modification Date
Customer NameASIC Name
Basic Information
Who filled this out and when, initially and most recently
When does customer start needing support
CN
Yr Qty1 Qty2 Qty3Volumes to Quote
Will be filled out by CSoC PM
For Power Estimate. Typical value is 15-30%
Include Everything built out of primitive gates
Used for Clock tree estimates and Power estimates
Effects technology, library, utilization, Power. Must have.
Domain Name Total Gate Count Including FF
Toggle Rate # FF Clock Freq (MHz)
FPGA Based Gate #
Logic DetailsNotes
Handy way to organize Clock Domain info by naming them, but this is optional
If this gate count came from an FPGA tool/library, indicate “yes”
How many of this group of IO?
In, Out, IO?
CMOS, SSTL2, Drive. Schmidt, etc? OK to enter DDR2, QDR, etc. We know what kind of buffers these specs use
IO clocking Freq. If it is DDR, please specify in Description info at left
FPGA Conversion Questions. These only need to be answered in the case of an FPGA conversion project
Netlist Handoff
Async. Description
FPGA Package Type/Pin #FPGA Vendor IP included?
FormatExternal Reset Available?
Company Confidential33
Working with CSoCExample Proposal Example Quotation
Confidential
Internal Use Only
34 Company Confidential
Working with CSoCExample Proposal
Please see “Attachments” for complete example proposalExample Quotation
Confidential
Company Confidential35
Working with CSoCASIC Contracts
36 Company Confidential
ASIC Contract Flow
NDA SLA
Master
DTO Risk-PTO
APT Safety StockAgmnt
Repeat for new ASIC
projects/parts
LOA (w/ Design Owner)
Master Production
Agreement (w/ new party)
APT (w/ new
party)
Once everOnce per every projectOccasionally, as needed
Safety StockAgmnt
Project Kickoff
Form
Approval to Start Final
P&R
DSSS Post Layout Approval
ES Approval
37 Company Confidential
ASIC Contracts Usage (1)Document AKA Purpose When Use What’s Next Comment Related Doc
Non-Disclosure Agreement
NDA Describes the confidential information to be protected, allowed uses and restrictions, and procedures for handling. Protects IP with legal measures against misuse.
When REA will provide any confidential info. Customer may initiate when disclosing confidential info to REA. Typically before RFQ receipt.
Exchange and identification of the confidential information
Initiate with REA’s form, which allows disclosures to our parent company. List expected disclosures for both parties. Include “REA ASIC libraries”.
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Software License Agreement
SLA Allows customers the right to use the OpenCAD software in an REA design kit. It protects REA’s IP.
Typically during RFQ stage, or after quote if customer is interested.
REA provides the design kit, and “FLEXlm” license which allows multiple user access. (FLEXlm alone allows access, not the legal right to use).
NDA is required also to protect our libraries. Ensure that a project NDA includes “REA ASIC libraries”.
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Standard Terms & Conditions
T’s&C’s Prior to execution of a Master, this specifies T’s&C’s.
All quotes or proposals prior to a Master.
Master, depending on the situation.
May help prevent issues later.
-
Document AKA Purpose When Use What’s Next Comment Related Doc Master Development & Production Agreement
Master or Contract or MDAPA
Sets basic business terms for NRE and MP between REA and a customer that will be paying for development (either an OEM or fabless design owner, or a disti when the design owner pays a disti who pays REA) & MP. Covers IP infringement, warranties, etc.
Only one master per customer. Prior to start of, and PO for, the first design project with a customer.
Usually tied to DTO for first design project at a customer.
Master alone is not sufficient, a DTO for design & APT for MP are needed. Master includes all T’s &C’s, so the separate Std T’s&C’s do not apply after execution.
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Development Task Order
DTO Agreement between REA and customer covering initial specs, cost and deliverables for a new design. Think of it as an accepted quote. (Quote is the offer, DTO is the “acceptance”.)
Once per project. If concurrent new designs, multiple projects can be on a single DTO.
Get the NRE PO and bill the first milestone (assuming standard NRE billing milestones).
Necessary for NRE payments.
o Project Start Meeting Summary Form
o Design Specification Summary Sheet
o Approval to Start Final Place&Route
o Post Layout Approval
o ES Approval
Document AKA Purpose When Use What’s Next Comment Related Doc Risk Production Task Order
Risk-PTO
Puts 100% financial liability on customer for an order placed prior to ES approval.
When a customer wishes to place MP order prior to ES approval.
Get the Risk PO.
Without this, a customer receiving non-working ES could cancel the risk order.
o ES Approval
Letter of Authorization
LOA Design Owner authorizes REA to sell their part to another entity. The other entity is typically a CM or a Disti.
o Disti buys for credit reasons.
o Sub buys, to build boards or systems for design owner.
o Occasionally a design owner licenses some other party to buy.
Get the Master Production Agreement signed by the new licensee. CSoC may negotiate terms with the new entity, or may extend prices and other terms in place with the Design Owner.
Newly authorized entity usually does not have the rights to make any changes (including marking) nor to approve PCN’s
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Master Production Agreement
Same Similar to Master except it excludes design.
After an LOA. Get the APT signed.
For a party who buys MP only, not NRE.
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Annual Production Terms
APT Agreement between REA and customer on production pricing, delivery, cancellation, and reschedules
When the customer wants to place an MP order after ES approval.
Get the MP PO.
Typical term is 1 year, but there is a provision to automatically renew
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Document AKA Purpose When Use What’s Next Comment Related Doc Vendor Managed Inventory (Safety Stock) Agreement
VMI or Buffer Agmnt
For REA to build and inventory (rather than ship) a specific amount of product that customer takes liability for.
o Suggest if customer has frequent upsides with little leadtime
o Customer requests it
A blanket PO is needed.
Often we do not charge for this but costs are involved, so don’t assume there is no charge.
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Change Order Same For changes to any term of any of the above, except for a Master
Anytime REA or the customer requests a changed term.
Change PO Master changes require an amendment or new Master
Ideal platform for power conscious products Industry leading low-power CBIC, eDRAM and PMIC technologies
Variety of ASIC/ASCP solutions ARM CPU’s, eDRAM, peripherals and high speed interfaces Gate Arrays for quick time-to-market IBIC / PMIC
IDM Value Proposition: One Stop Shopping Providing Solutions, Design, IP, Fabrication, Packaging, Test, Quality,
Reliability, …
Failure Analysis
Design for TestDesign for Analysis
High ReliabilityQuality Control
Shipment
Failed Chips
Stressed TestHigh Fault Coverage
Feedback for Quality Improvement
Testing
ProductionDesignProcess
ChipPackage
42 Company Confidential
Sales Call to Action
Develop account strategies to build customer relationships and create opportunities based on our values and solutions Smart Grid (ARM SOC & PLM-1) Storage CBIC (USB3.0, SATA Gen3 ) IBIC PMIC
Identify ASIC opportunities in non-target segments that align with our values Low-power Solutions eDRAM ARM-based SOCs Interface IP One-stop shop (IDM Value)
Renesas Electronics America Inc.Company Confidential
Company Confidential44
Addendum
45 Company Confidential
Working with CSoCExample Proposal
Please see “Attachments” for complete example proposalExample Quotation