1 COMP541 Combinational Logic - I Montek Singh Jan 11, 2012.

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COMP541COMP541

Combinational Logic - ICombinational Logic - I

Montek SinghMontek Singh

Jan 11, 2012Jan 11, 2012

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TodayToday Basics of digital logic (review)Basics of digital logic (review)

Basic functionsBasic functions Boolean algebraBoolean algebra Gates to implement Boolean functionsGates to implement Boolean functions

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Binary LogicBinary Logic Binary variablesBinary variables

Can be 0 or 1 (T or F, low or high)Can be 0 or 1 (T or F, low or high) Variables named with single letters in examplesVariables named with single letters in examples Really use words when designing circuitsReally use words when designing circuits

Logic GatesLogic Gates Perform logic functions: Perform logic functions:

inversion (NOT), AND, OR, NAND, NOR, etc.inversion (NOT), AND, OR, NAND, NOR, etc.

Single-input: Single-input: NOT gate, bufferNOT gate, buffer

Two-input: Two-input: AND, OR, XOR, NAND, NOR, XNORAND, OR, XOR, NAND, NOR, XNOR

Multiple-inputMultiple-input

Single-Input Logic GatesSingle-Input Logic Gates

NOT

Y = A

A Y0 11 0

A Y

BUF

Y = A

A Y0 01 1

A Y

Two-Input Logic GatesTwo-Input Logic Gates

AND

Y = AB

A B Y0 0 00 1 01 0 01 1 1

AB

Y

OR

Y = A + B

A B Y0 0 00 1 11 0 11 1 1

AB

Y

More Two-Input Logic GatesMore Two-Input Logic Gates

XNOR

Y = A + B

A B Y0 00 11 01 1

AB

Y

XOR NAND NOR

Y = A + B Y = AB Y = A + B

A B Y0 0 00 1 11 0 11 1 0

A B Y0 0 10 1 11 0 11 1 0

A B Y0 0 10 1 01 0 01 1 0

AB

Y AB

Y AB

Y

1001

Multiple-Input Logic GatesMultiple-Input Logic Gates

AND4

Y = ABCD

AB YCD

B C Y0 00 11 01 1

A0000

0 00 11 01 1

1111

00000001

NOR3

Y = A+B+C

B C Y0 00 11 01 1

AB YC

A0000

0 00 11 01 1

1111

10000000

NAND is UniversalNAND is Universal Can express any Boolean FunctionCan express any Boolean Function Equivalents belowEquivalents below

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Using NAND as Invert-ORUsing NAND as Invert-OR

Also reverse inverter diagram for clarityAlso reverse inverter diagram for clarity

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NOR Also UniversalNOR Also Universal Dual of NANDDual of NAND

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Representation: SchematicRepresentation: Schematic

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Representation: Boolean AlgebraRepresentation: Boolean Algebra More on this next timeMore on this next time

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ZY X F

Representation: Truth TableRepresentation: Truth Table 22nn rows: where n # of variables rows: where n # of variables

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Schematic DiagramsSchematic Diagrams Can you design a Pentium or a graphics chip Can you design a Pentium or a graphics chip

that way?that way? Well, yes, but diagrams are overly complex and hard Well, yes, but diagrams are overly complex and hard

to enterto enter

These days people represent the same thing These days people represent the same thing with text (code)with text (code)

Hardware Description LanguagesHardware Description Languages Main ones are Verilog and VHDLMain ones are Verilog and VHDL

Others: Abel, SystemC, HandelOthers: Abel, SystemC, Handel

Origins as testing languagesOrigins as testing languages To generate sets of input valuesTo generate sets of input values

Levels of use from very detailed to more Levels of use from very detailed to more abstract descriptions of hdwabstract descriptions of hdw Think about C++ from assembly level description to Think about C++ from assembly level description to

very abstract HLLvery abstract HLL

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Design w/ HDLDesign w/ HDL Two leading HDLs:Two leading HDLs:

VerilogVerilogdeveloped in 1984 by Gateway Design Automationdeveloped in 1984 by Gateway Design Automationbecame an IEEE standard (1364) in 1995became an IEEE standard (1364) in 1995

VHDLVHDLDeveloped in 1981 by the Department of DefenseDeveloped in 1981 by the Department of DefenseBecame an IEEE standard (1076) in 1987Became an IEEE standard (1076) in 1987

Most (all?) commercial designs built using Most (all?) commercial designs built using HDLsHDLs

WeWe’’ll use Verilogll use Verilog

Uses of HDLUses of HDL SimulationSimulation

Defines input values are applied to the circuitDefines input values are applied to the circuit Outputs checked for correctnessOutputs checked for correctness Millions of dollars saved by debugging in simulation Millions of dollars saved by debugging in simulation

instead of hardwareinstead of hardware

SynthesisSynthesis Transforms HDL code into a netlist describing the Transforms HDL code into a netlist describing the

hardware (i.e., a list of gates and the wires connecting hardware (i.e., a list of gates and the wires connecting them)them)

IMPORTANT:IMPORTANT: When describing circuits using an HDL, itWhen describing circuits using an HDL, it’’s critical to s critical to

think of the hardware the code should produce.think of the hardware the code should produce.

Verilog ModuleVerilog Module Code always organized in modulesCode always organized in modules Represent a logic Represent a logic ““boxbox””

With inputs and outputsWith inputs and outputs

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ab yc

VerilogModule

ExampleExamplemodule example(input a, b, c,module example(input a, b, c,

output y);output y);

*** HDL CODE HERE ****** HDL CODE HERE ***

endmoduleendmodule

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Levels of VerilogLevels of VerilogSeveral different levels (or Several different levels (or ““viewsviews””))

StructuralStructural DataflowDataflow ConditionalConditional BehavioralBehavioral

Look at first three todayLook at first three today

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Example 1Example 1 Output is 1 when input < 011Output is 1 when input < 011

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Structural VerilogStructural Verilog Explicit description of gates and connectionsExplicit description of gates and connections Textual form of schematicTextual form of schematic Specifying Specifying netlistnetlist

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Example 1 in Structural VerilogExample 1 in Structural Verilogmodule example_1(X,Y,Z,F);module example_1(X,Y,Z,F); input X;input X; input Y;input Y; input Z;input Z; output F;output F;

//wire X_n, Y_n, Z_n, f1, f2;//wire X_n, Y_n, Z_n, f1, f2;notnot

g0(X_n, X),g0(X_n, X),g1(Y_n, Y),g1(Y_n, Y),g2(Z_n, Z);g2(Z_n, Z);

nandnandg3(f1, X_n, Y_n),g3(f1, X_n, Y_n),g4(f2, X_n, Z_n),g4(f2, X_n, Z_n),g5(F, f1, f2);g5(F, f1, f2);

endmoduleendmodule

Can also be input X, Y, Z;

Slight Variation – Gates not namedSlight Variation – Gates not named

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module example_1_c(X,Y,Z,F);module example_1_c(X,Y,Z,F); input X;input X; input Y;input Y; input Z;input Z; output F;output F;

not(X_n, X);not(X_n, X);not(Y_n, Y);not(Y_n, Y);not(Z_n, Z);not(Z_n, Z);

nand(f1, X_n, Y_n);nand(f1, X_n, Y_n);nand(f2, X_n, Z_n);nand(f2, X_n, Z_n);nand(F, f1, f2);nand(F, f1, f2);

endmoduleendmodule

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ExplanationExplanation Each of these gates is an Each of these gates is an instanceinstance

Like object vs classLike object vs class In first example, they had namesIn first example, they had names

not g0(X_n, X),not g0(X_n, X), In second example, no nameIn second example, no name

not(X_n, X);not(X_n, X); Later see why naming can be usefulLater see why naming can be useful

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GatesGates Standard set of gates availableStandard set of gates available

and, or, notand, or, not nand, nornand, nor xor, xnorxor, xnor bufbuf

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Dataflow DescriptionDataflow Description

Basically a Basically a logical logical expressionexpression

No explicit No explicit gatesgates

module example_1_b(X,Y,Z,F);

input X;

input Y;

input Z;

output F;

assign F = (~X & ~Y) | (~X & ~Z);

endmodule

Conditional DescriptionConditional Description

module example_1_c(input [2:0] A,module example_1_c(input [2:0] A,

output F);output F);

assign F = (A > 3assign F = (A > 3’’b011) ? 0 : 1;b011) ? 0 : 1;

endmoduleendmodule

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Noticealternatespecification

AbstractionAbstraction Using the Using the digital abstractiondigital abstraction we we’’ve been ve been

thinking of the inputs and outputs asthinking of the inputs and outputs as True or FalseTrue or False 1 or 01 or 0

What are they really?What are they really?

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Logic LevelsLogic Levels Define discrete voltages to represent 1 and 0Define discrete voltages to represent 1 and 0 For example, we could define: For example, we could define:

0 to be 0 to be groundground or 0 volts or 0 volts 1 to be 1 to be VVDDDD or 5 volts or 5 volts

What about 4.99 volts? Is that a 0 or a 1?What about 4.99 volts? Is that a 0 or a 1? What about 3.2 volts?What about 3.2 volts?

Logic LevelsLogic Levels Define a Define a rangerange of voltages to represent 1 and of voltages to represent 1 and

00 Define different ranges for outputs and inputs Define different ranges for outputs and inputs

to allow for to allow for noisenoise in the system in the system What is noise?What is noise?

What is Noise?What is Noise? Anything that degrades the signalAnything that degrades the signal

E.g., resistance, power supply noise, coupling to E.g., resistance, power supply noise, coupling to neighboring wires, etc.neighboring wires, etc.

Example: a gate (driver) could output a 5 volt Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long signal but, because of resistance in a long wire, the signal could arrive at the receiver wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 voltswith a degraded value, for example, 4.5 volts

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Driver ReceiverNoise

5 V 4.5 V

The Static DisciplineThe Static Discipline Given logically valid inputs, every circuit Given logically valid inputs, every circuit

element must produce logically valid outputselement must produce logically valid outputs

Discipline ourselves to use limited ranges of Discipline ourselves to use limited ranges of voltages to represent discrete valuesvoltages to represent discrete values

Logic LevelsLogic Levels

Driver Receiver

ForbiddenZone

NML

NMH

Input CharacteristicsOutput Characteristics

VO H

VDD

VO L

GND

VIH

VIL

Logic HighInput Range

Logic LowInput Range

Logic HighOutput Range

Logic LowOutput Range

Noise MarginsNoise Margins

Driver Receiver

ForbiddenZone

NML

NMH

Input CharacteristicsOutput Characteristics

VO H

VDD

VO L

GND

VIH

VIL

Logic HighInput Range

Logic LowInput Range

Logic HighOutput Range

Logic LowOutput Range

NMH = VOH – VIH

NML = VIL – VOL

DC Transfer CharacteristicsDC Transfer Characteristics

VDD

V(A)

V(Y)

VOH VDD

VOL

VIL, VIH

0

A Y

VDD

V(A)

V(Y)

VOH

VDD

VOL

VIL VIH

Unity GainPoints

Slope = 1

0VDD / 2

Ideal Buffer: Real Buffer:

NMH = NML = VDD/2 NMH , NML < VDD/2

VVDDDD Scaling Scaling Chips in the 1970Chips in the 1970’’s and 1980s and 1980’’s were designed s were designed

using Vusing VDDDD = 5 V = 5 V As technology improved, VAs technology improved, VDDDD dropped dropped

Avoid frying tiny transistorsAvoid frying tiny transistors Save powerSave power

3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …

Logic Family ExamplesLogic Family Examples

Logic Family VDD VIL VIH VOL VOH

TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4

CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84

LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4

LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7

ReadingReading Textbook Ch. 2.1 – 2.6Textbook Ch. 2.1 – 2.6

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