1 COMP541 Combinational Logic and Design Montek Singh Jan 25, 2007.

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COMP541COMP541

Combinational Logic Combinational Logic and Designand Design

Montek SinghMontek Singh

Jan 25, 2007Jan 25, 2007

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TopicsTopics What we didn’t cover last timeWhat we didn’t cover last time

Other gates, standard formsOther gates, standard forms

Combinational Design (Ch. 3)Combinational Design (Ch. 3) Real DevicesReal Devices

Logic Families, Actual ICs, Gate delaysLogic Families, Actual ICs, Gate delays

Propagation delayPropagation delay

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Combinational Logic DesignCombinational Logic Design Ch. 3 takes us to hierarchical designCh. 3 takes us to hierarchical design Like you’d use for a program of sizeLike you’d use for a program of size

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Design HierarchyDesign Hierarchy Just like with large program, to design a large Just like with large program, to design a large

chip need hierarchychip need hierarchy Divide and ConquerDivide and Conquer

To create, test, and also to understandTo create, test, and also to understand

BlockBlock is equivalent to object is equivalent to object

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ExampleExample 9-input odd func (parity for byte)9-input odd func (parity for byte) Block for schematic is box with labelsBlock for schematic is box with labels

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Design Broken Into ModulesDesign Broken Into Modules

Use 3-input odd functionsUse 3-input odd functions

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Each Module uses XOREach Module uses XOR

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Use NAND to Implement XORUse NAND to Implement XOR In case there’s no XOR, for exampleIn case there’s no XOR, for example

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Design Design HierarchHierarchyy

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Components in DesignComponents in Design RHS shows what must be designedRHS shows what must be designed

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Reuse is CommonReuse is Common Certainly forced because of availability of parts (chips)Certainly forced because of availability of parts (chips) Also the design cycle was very longAlso the design cycle was very long Now more flexibility with programmable logicNow more flexibility with programmable logic

But still reuse from libraries or intellectual property (IP)But still reuse from libraries or intellectual property (IP) Example: buy a PCI designExample: buy a PCI design Open source, see Open source, see www.opencores.orgwww.opencores.org

Note the many logic blocks available in Xilinx libraryNote the many logic blocks available in Xilinx library

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Flow of CAD SystemFlow of CAD System

NetlistNetlist is is description of description of connectionsconnections

Generic Gates

Replaces Generic Gates

with ones available in Technology

Library

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Technology MappingTechnology Mapping Full customFull custom

Pixel-Planes chips (machines in lobby)Pixel-Planes chips (machines in lobby) Memories, CPUs, etcMemories, CPUs, etc

Standard cellStandard cell Library of cellsLibrary of cells Engineer determined interconnectionEngineer determined interconnection

Gate arraysGate arrays Small circuits with interconnectSmall circuits with interconnect

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Hierarchy Example – 4-bit Hierarchy Example – 4-bit EqualityEquality Example 3-4 in bookExample 3-4 in book

Input: 2 vectors A(3:0) and B(3:0)Input: 2 vectors A(3:0) and B(3:0) Output: One bit, E, which is 1 if A and B are Output: One bit, E, which is 1 if A and B are

bitwise equal, 0 otherwisebitwise equal, 0 otherwise

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DesignDesign Hierarchical design seems a good approachHierarchical design seems a good approach One module/bitOne module/bit Final module for EFinal module for E

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Design for MX moduleDesign for MX module Logic function in book isLogic function in book is

I’d call this “not E”, but…I’d call this “not E”, but… Can implement asCan implement as

i i i i iE AB AB

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Design for ME moduleDesign for ME module Final E is 1 only if all intermediate values are 0Final E is 1 only if all intermediate values are 0 SoSo

And a design isAnd a design is

0 1 2 3E E E E E

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Hierarchical VerilogHierarchical Verilog We already saw example of We already saw example of instantiationinstantiation when when

we used AND and OR gateswe used AND and OR gates

Just use module name and an identifier for the Just use module name and an identifier for the particular instanceparticular instance

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Vector of Wires (Bus)Vector of Wires (Bus) Denotes a set of wiresDenotes a set of wiresinput [1:0] S;input [1:0] S;

Syntax is [Syntax is [a: ba: b] where a is high-order] where a is high-order So this could be “[0:1] S”So this could be “[0:1] S” Order will matter when we make assignments with Order will matter when we make assignments with

values bigger than one bitvalues bigger than one bit Or when we connect sets of wiresOr when we connect sets of wires

NOTE: THIS IS NOT AN ARRAY!NOTE: THIS IS NOT AN ARRAY!

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Next slides document designNext slides document design Just for your notesJust for your notes

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MXMX

module mx(A, B, E);module mx(A, B, E);input A, B;input A, B;output E;output E;

assign E = (~A & B) | (A & ~B);assign E = (~A & B) | (A & ~B);

endmoduleendmodule

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MEME

module me(E, Ei);module me(E, Ei);input [3:0] Ei;input [3:0] Ei;output E;output E;

assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]);assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]);

endmoduleendmodule

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Top LevelTop Levelmodule top(A, B, E);module top(A, B, E);

input [3:0] A;input [3:0] A;input [3:0] B;input [3:0] B;output E;output E;

wire [3:0] Ei;wire [3:0] Ei;

mx m0(A[0], B[0], Ei[0]);mx m0(A[0], B[0], Ei[0]);mx m1(A[1], B[1], Ei[1]);mx m1(A[1], B[1], Ei[1]);mx m2(A[2], B[2], Ei[2]);mx m2(A[2], B[2], Ei[2]);mx m3(A[3], B[3], Ei[3]);mx m3(A[3], B[3], Ei[3]);

me me0(E, Ei);me me0(E, Ei);

endmoduleendmodule

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Integrated CircuitIntegrated Circuit Known as IC or chipKnown as IC or chip Silicon containing circuitSilicon containing circuit

Later in semester we’ll examine design and Later in semester we’ll examine design and constructionconstruction

Maybe processesMaybe processes

Packaged in ceramic or plasticPackaged in ceramic or plastic From 4-6 pins to hundredsFrom 4-6 pins to hundreds

Pins wired to pads on chipPins wired to pads on chip

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BondingBonding

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Levels of IntegrationLevels of Integration SSISSI

Individual gatesIndividual gates MSIMSI

Things like counters, single-block adders, etc.Things like counters, single-block adders, etc. Like stuff we’ll be doing nextLike stuff we’ll be doing next

LSILSI VLSIVLSI

Larger circuits, like the FPGA, Pentium, etc.Larger circuits, like the FPGA, Pentium, etc.

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Logic FamiliesLogic Families RTL, DTL earliestRTL, DTL earliest TTL was used 70s, 80sTTL was used 70s, 80s

Still available and used occasionallyStill available and used occasionally 7400 series logic, refined over generations7400 series logic, refined over generations

CMOSCMOS Was low speed, low noiseWas low speed, low noise Now fast and is most commonNow fast and is most common

BiCMOS and GaAsBiCMOS and GaAs SpeedSpeed

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CatalogsCatalogs Catalog pages describe chipsCatalog pages describe chips Look atLook at

http://focus.ti.com/lit/ds/scas014c/scas014c.pdfhttp://focus.ti.com/lit/ds/scas014c/scas014c.pdf

SpecificationsSpecifications PinoutsPinouts Packages/DimensionsPackages/Dimensions Electrical characteristicsElectrical characteristics

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Electrical CharacteristicsElectrical Characteristics Fan in – max number of inputs to a gateFan in – max number of inputs to a gate Fan out – how many standard loads it can drive (load usually 1)Fan out – how many standard loads it can drive (load usually 1) Voltage – often 1.8v, 3.3v or 5v are commonVoltage – often 1.8v, 3.3v or 5v are common Noise margin – how much electrical noise it can tolerateNoise margin – how much electrical noise it can tolerate Power dissipation – how much power chip needsPower dissipation – how much power chip needs

TTL highTTL high Some CMOS low (but look at heat sink on a Pentium)Some CMOS low (but look at heat sink on a Pentium)

Propagation delay – nextPropagation delay – next

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Propagation DelayPropagation Delay Max of high-to-low and low-to-highMax of high-to-low and low-to-high Maximum and typical givenMaximum and typical given

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DelaysDelays Transport delay = “pure” delayTransport delay = “pure” delay

Output after a specified timeOutput after a specified time

Inertial delayInertial delay No effect if input occurs for time that is too short No effect if input occurs for time that is too short

(can’t overcome inertia) – smaller than transport (can’t overcome inertia) – smaller than transport delay timedelay time

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Effect of Transport Delay (blue)Effect of Transport Delay (blue) Delay just shifts signal in timeDelay just shifts signal in time

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Effect of Inertial DelayEffect of Inertial Delay

Blue – Propagation delay time Black – Rejection timeBlue – Propagation delay time Black – Rejection time

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Fan Out and DelayFan Out and Delay Practical fan out of CMOS limited by Practical fan out of CMOS limited by

capacitance of input gatescapacitance of input gates More gates driven, longer time for signal to More gates driven, longer time for signal to

changechange So delay time for CMOS affected by fan outSo delay time for CMOS affected by fan out Wire delay also very importantWire delay also very important

And routing delays in FPGAAnd routing delays in FPGA

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Example using ISEExample using ISE Look at Lab 1 (tomorrow)Look at Lab 1 (tomorrow)

Synthesis report timing predictionSynthesis report timing prediction Text-based Post Place & Route timing reportText-based Post Place & Route timing report View routed designView routed design

To see where components and I/O buffers are locatedTo see where components and I/O buffers are located

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TodayToday Design paradigmDesign paradigm

Hierarchical designHierarchical design

Talked about real devicesTalked about real devices Propagation delaysPropagation delays

First look at how fast your circuits First look at how fast your circuits couldcould work work

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Next TimeNext Time Basic combinational circuitsBasic combinational circuits

MultiplexerMultiplexer EncodersEncoders DecodersDecoders

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ReadRead Chapter 4Chapter 4

Sections 3, 4, 5Sections 3, 4, 5 Section 4-8 covers VerilogSection 4-8 covers Verilog