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1 Chapter 3.2 : Virtual Chapter 3.2 : Virtual Memory Memory What is virtual memory? What is virtual memory? Virtual memory management Virtual memory management schemes schemes Paging Paging Segmentation Segmentation Segmentation with paging Segmentation with paging Page table management Page table management
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1 Chapter 3.2 : Virtual Memory What is virtual memory? What is virtual memory? Virtual memory management schemes Virtual memory management schemes Paging.

Jan 01, 2016

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Page 1: 1 Chapter 3.2 : Virtual Memory What is virtual memory? What is virtual memory? Virtual memory management schemes Virtual memory management schemes Paging.

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Chapter 3.2 : Virtual Chapter 3.2 : Virtual MemoryMemory

What is virtual memory?What is virtual memory? Virtual memory management Virtual memory management

schemesschemes PagingPaging SegmentationSegmentation Segmentation with pagingSegmentation with paging

Page table managementPage table management

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Problems with Memory Problems with Memory Management Techniques Management Techniques

so farso far Unused (wasted) memory due to Unused (wasted) memory due to

fragmentationfragmentation Memory may contain parts of program Memory may contain parts of program

which are not used during a run (ie., which are not used during a run (ie., some routines may not be accessed in some routines may not be accessed in that particular run)that particular run)

Process size is limited with the size of Process size is limited with the size of physical memoryphysical memory

Process needs contiguous space in real Process needs contiguous space in real memory for executionmemory for execution

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Virtual Memory (VM)Virtual Memory (VM)

Virtual memory of process on disk

Real memory of system

Map (translate)

virtual address to real

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Virtual Memory (VM)Virtual Memory (VM)

VM is conceptualVM is conceptual It is constructed on diskIt is constructed on disk Size of VM is not limited (usually Size of VM is not limited (usually

larger than real memory)larger than real memory) All process addresses refer to the VM All process addresses refer to the VM

imageimage When the process executes all VM When the process executes all VM

addresses are mapped on to real addresses are mapped on to real memorymemory

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Did We Solve the Did We Solve the “Problems”?“Problems”?

1.1. Unused (wasted) memory due to Unused (wasted) memory due to fragmentation (We’ll see!)fragmentation (We’ll see!)

2.2. Memory may contain parts of Memory may contain parts of program which are not used during a program which are not used during a run run

YES! Virtual memory contents are YES! Virtual memory contents are loaded into memory on demandloaded into memory on demand

33.. Process size is limited with the size Process size is limited with the size of physical memoryof physical memory

YES! Process size can be larger than YES! Process size can be larger than real memoryreal memory

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(Pure) Paging(Pure) Paging

Virtual and real memory are divided into Virtual and real memory are divided into fixed sized fixed sized pagespages

Programs are divided into pagesPrograms are divided into pages A process address (both in virtual & real A process address (both in virtual & real

memory) has two componentsmemory) has two components

Page # Offset within page

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Interpretation of an Interpretation of an AddressAddress

16 bits for addressing means that the 16 bits for addressing means that the memory addressed is 64K bytes (0000 -memory addressed is 64K bytes (0000 -FFFF)FFFF)

Suppose page size is 4K bytes (12 bits)Suppose page size is 4K bytes (12 bits) The The virtual virtual memory has 16 pages (4 bits)memory has 16 pages (4 bits) Real memory can have at the most 16 Real memory can have at the most 16

pagespages Example : Example :

address : 7 F B C address : 7 F B C 00111 1111 1011 1100111 1111 1011 1100

Page # Offset

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The relation betweenThe relation between virtualvirtual addressesaddresses and physical and physical

memory addressesmemory addresses

64K Virtual 64K Virtual MemoryMemory

32K Real 32K Real MemoryMemory

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Paging (Cont.)Paging (Cont.) When process pages are transferred When process pages are transferred

from VM to real memory, page from VM to real memory, page numbers must be mapped from numbers must be mapped from virtual to real memory addressesvirtual to real memory addresses

This mapping is done by software & This mapping is done by software & hardwarehardware

When the process is started only the When the process is started only the first page (main) is loaded. Other first page (main) is loaded. Other pages are loaded on pages are loaded on demanddemand

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Virtual MemoryVirtual Memory – Memory – Memory Management UnitManagement Unit

The position and function of the MMUThe position and function of the MMU

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Internal operation of MMU with 16 4 KB pagesInternal operation of MMU with 16 4 KB pages

Note that Note that virtual address virtual address

is 16 bits is 16 bits (64K virtual (64K virtual memory) memory)

but the physical but the physical address is 15 address is 15

bits bits (32K real (32K real memory)memory)

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Page TablesPage Tables

Index of page table is the virtual page #Index of page table is the virtual page #

Page Table

0 Page frame #

Page protection

Reference bit

Modification bit

Validity bit

Page Table Entry

1

8

234567

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Page Table Entry FieldsPage Table Entry Fields

Validity bit is set when the page is in Validity bit is set when the page is in memorymemory

Reference bit is set set by the Reference bit is set set by the hardware whenever the page is hardware whenever the page is referredreferred

Modified bit is set whenever the page Modified bit is set whenever the page is modifiedis modified

Page-protection bits set the access Page-protection bits set the access rights (eg., read, write restrictions)rights (eg., read, write restrictions)

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Address Mapping in Address Mapping in PagingPaging

Real memory address

Page tables of processes

PTn

PT 1

PT2. .

Page # Offset within pagePage Table Register

+

Catenate

Virtual memory address

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Address Mapping in Address Mapping in Paging (Cont.)Paging (Cont.)

During the execution every page During the execution every page reference is checked against the page reference is checked against the page map table entrymap table entry

If the validity bit is set (ie., page is in If the validity bit is set (ie., page is in memory) execution continuesmemory) execution continues

If the page is not in memory a If the page is not in memory a page fault page fault (interrupt - trap) (interrupt - trap) occurs and the page is occurs and the page is fetched into memoryfetched into memory

If the memory is full, pages are written If the memory is full, pages are written back using a back using a page replacement page replacement algorithmalgorithm

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Memory Management Memory Management Problems : Re-visit due Problems : Re-visit due

to pagingto paging11. . Unused (wasted) memory due to Unused (wasted) memory due to

fragmentationfragmentation ONLY on the last page (ONLY on the last page (Page BreakPage Break))

22..Memory may contain parts of program which Memory may contain parts of program which are not used during a run are not used during a run Virtual memory contents are loaded into memory on Virtual memory contents are loaded into memory on

demanddemand

33.. Process size is limited with the size of Process size is limited with the size of physical memoryphysical memory Process size can be larger than real memoryProcess size can be larger than real memory

Furthermore, program does not occupy Furthermore, program does not occupy contiguous locations in memory (virtual contiguous locations in memory (virtual pages are scattered in real memory)pages are scattered in real memory)

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SegmentationSegmentation

Pages are fixed in size, segments Pages are fixed in size, segments are are variable sizedvariable sized

A segment can be a logical entity A segment can be a logical entity such assuch as

Main programMain program Some routinesSome routines Data of programData of program FileFile StackStack

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Segmentation (Cont.)Segmentation (Cont.) Process addresses are now in the formProcess addresses are now in the form

Segment # Offset within segment

Segment Map Table has one entry Segment Map Table has one entry for each segment and each entry for each segment and each entry consist of consist of

Segment numberSegment number Physical segment starting Physical segment starting

addressaddress Segment lengthSegment length

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Segmentation (1)Segmentation (1)

One-dimensional address space with growing tablesOne-dimensional address space with growing tables One table may bump into anotherOne table may bump into another

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Segmentation (2)Segmentation (2)

Allows each table to grow or shrink, independentlyAllows each table to grow or shrink, independently

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Segmentation (3)Segmentation (3)

Comparison of paging and Comparison of paging and segmentationsegmentation

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Implementation of Pure Implementation of Pure SegmentationSegmentation

(a)-(d) Development of (a)-(d) Development of fragmentationfragmentation(e) Removal of the (e) Removal of the fragmentationfragmentation by compaction by compaction

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Problems with Problems with SegmentationSegmentation

Similar problems in dynamic partitioningSimilar problems in dynamic partitioning

Fragmentation in real Fragmentation in real memorymemory

Relocation is Relocation is necessary for necessary for compactioncompaction

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Segmentation with Segmentation with PagingPaging

Segmentation in virtual memory, Segmentation in virtual memory, paging in real memorypaging in real memory

A segment is composed of pagesA segment is composed of pages An address has three componentsAn address has three components

Page # Offset within pageSegment #

The real memory contains only the The real memory contains only the demanded pages of a segment, not demanded pages of a segment, not the full segmentthe full segment

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Addressing in Addressing in Segmentation with Segmentation with

PagingPaging

Segment Table Page Tables Pages

Page # Offset within pageSegment #

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How Big is a Page Table?How Big is a Page Table?

Consider a full 2 Consider a full 2 3232 byte (4GB) address byte (4GB) address spacespace Assume 4096 byte (2 Assume 4096 byte (2 1212 byte) pages byte) pages 4 bytes per page table entry4 bytes per page table entry The page table has 2 The page table has 2 3232/2 /2 1212 (= 2 (= 2 2020 ) )

entries (one for each page)entries (one for each page) Page table size would be 2 Page table size would be 2 2222 bytes bytes

(or 4 megabytes)(or 4 megabytes)

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Problems with Direct Problems with Direct Mapping?Mapping?

Although a page table is of variable Although a page table is of variable length depending on the size of length depending on the size of process, we can not keep them in process, we can not keep them in registersregisters

Page table must be in memory for fast Page table must be in memory for fast accessaccess

Since a page table can be very large Since a page table can be very large (4MB), page tables are stored in virtual (4MB), page tables are stored in virtual memory and be subjected to paging memory and be subjected to paging like process pageslike process pages

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How to Solve?How to Solve?

Two-level LookupTwo-level Lookup

Inverted Page TablesInverted Page Tables

Translation Lookaside BuffersTranslation Lookaside Buffers

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Two-Level LookupTwo-Level Lookup

Directory Page Offset

12 bits - 4096 Byte pages

10 bits - 1024 pages

10 bits - 1024 directories

Virtual Address - 32 bits (4 GB)

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Two-Level Lookup Two-Level Lookup (Cont.)(Cont.)

Dir Page Offset

+

+

Physical Address

Page Directory

Page Table

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Two-Level Lookup Two-Level Lookup (Cont.)(Cont.)

A process is represented by one or A process is represented by one or more entries of the page directory (ie., more entries of the page directory (ie., several page tables)several page tables)

Typically a page table size is set as Typically a page table size is set as one page which makes swapping one page which makes swapping easiereasier

This is one of the addressing schemes This is one of the addressing schemes used by Intel family of chips (Intel used by Intel family of chips (Intel chips can use paging, segmentation or chips can use paging, segmentation or a combination of both)a combination of both)

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Inverted Page TablesInverted Page Tables

Page # Offset within page

Virtual Address

hash

Hash TablePage Frame Table

PID

Page # 101

Hash # 23

Process # 17

76

Page #

23

17

32213

21

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Inverted Page Tables Inverted Page Tables (Cont.)(Cont.)

The virtual page number is The virtual page number is hashed to point to a hash tablehashed to point to a hash table

The hash table contains a The hash table contains a pointer to the inverted page pointer to the inverted page table table

Inverted page table contains Inverted page table contains page table entries (one for each page table entries (one for each real memory page)real memory page)

Entries having the same hash Entries having the same hash codes are chainedcodes are chained

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Inverted Page Tables Inverted Page Tables (Cont.)(Cont.)

A fixed portion of memory is A fixed portion of memory is used for mapping regardless of used for mapping regardless of the number of processes or the number of processes or virtual pagesvirtual pages

This approach is used by IBM’s This approach is used by IBM’s AS/400 and RISC System/6000 AS/400 and RISC System/6000 computerscomputers

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Translation Lookaside Translation Lookaside BufferBuffer

Frame # Offset

TLB Hit

TLB Miss

TLB

Page Table

Page # Offset

Virtual Address

Real AddressPage Fault

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Translation Lookaside Translation Lookaside Buffer (Cont.) Buffer (Cont.)

Translation lookaside buffer (TLB) is Translation lookaside buffer (TLB) is a cache for page table entriesa cache for page table entries

TLB contains page table entries that TLB contains page table entries that have been most recently usedhave been most recently used

Whenever the page table is referred Whenever the page table is referred (TLB miss), the page table entry is (TLB miss), the page table entry is also copied to the TLBalso copied to the TLB

TLB is usually an associative TLB is usually an associative memory (content addressable memory (content addressable memory) memory)

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TLBs – Translation TLBs – Translation Lookaside BuffersLookaside Buffers

A TLB to speed up pagingA TLB to speed up paging

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Segmentation with Paging: Segmentation with Paging: MULTICS (1)MULTICS (1)

Descriptor segment points to page tablesDescriptor segment points to page tables Segment descriptor – numbers are field lengthsSegment descriptor – numbers are field lengths

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Segmentation with Paging: Segmentation with Paging: MULTICS (2)MULTICS (2)

A 34-bit MULTICS virtual addressA 34-bit MULTICS virtual address

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Segmentation with Paging: Segmentation with Paging: MULTICS (3)MULTICS (3)

Conversion of a 2-part MULTICS address into a main Conversion of a 2-part MULTICS address into a main memory addressmemory address

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Segmentation with Paging: Segmentation with Paging: MULTICS (4)MULTICS (4)

Simplified version of the Simplified version of the MULTICSMULTICS TLB TLB Existence of 2 page sizes makes actual TLB more complicatedExistence of 2 page sizes makes actual TLB more complicated

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Segmentation with Paging: Segmentation with Paging: Pentium (1)Pentium (1)

A Pentium selectorA Pentium selector

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Segmentation with Paging: Segmentation with Paging: Pentium (2)Pentium (2)

Pentium code segment descriptorPentium code segment descriptor Data segments differ slightlyData segments differ slightly

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Segmentation with Paging: Segmentation with Paging: Pentium (3)Pentium (3)

Conversion of a (selector, offset) pair to a linear addressConversion of a (selector, offset) pair to a linear address

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Segmentation with Paging: Segmentation with Paging: Pentium (4)Pentium (4)

Mapping of a linear address onto a physical addressMapping of a linear address onto a physical address

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Segmentation with Paging: Segmentation with Paging: Pentium (5)Pentium (5)

Protection on the PentiumProtection on the Pentium

Level