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VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques
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Basic StructuresBasic Structures
Basic Building BlocksBasic Building BlocksBasic Building Blocks
�� EntityEntity
�� ArchitectureArchitecture
�� ConfigurationConfiguration
�� PackagePackage
�� LibraryLibrary
VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques
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Entity Declaration (1)Entity Declaration (1)
The External Aspect of a Design UnitThe External Aspect of a Design UnitThe External Aspect of a Design Unit
VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques
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Architectures (1)Architectures (1)
The Internal Aspect of a Design UnitThe Internal Aspect of a Design UnitThe Internal Aspect of a Design Unit
architecturearchitecture architecture_name architecture_name of of entity_name entity_name isis{ architecture_declarative_part}{ architecture_declarative_part}
XX <= <= AA xorxor B;B;SS <= <= XX xorxor CinCin afterafter 1010 nsns;;CoutCout <= <= (A (A andand B) B) oror (X (X andand CinCin) ) afterafter 55 nsns;;
endend DATAFLOWDATAFLOW;;
VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques
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Architectures (3)Architectures (3)
A Structural StyleA Structural StyleA Structural Style
VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques
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Data Objects (1)Data Objects (1)
Three ClassesThree ClassesThree Classes
�� ConstantsConstants
�� Initialized to a specific value and Initialized to a specific value and nevernever modifiedmodifiedconstant MSB : INTEGER := 5;
�� Var iablesVar iables
�� Used to hold temporary dataUsed to hold temporary data
�� OnlyOnly used within processes & subprogramsused within processes & subprograms
variable variable DELAYDELAY : : INTEGER range INTEGER range 0 0 to to 15 := 0;15 := 0;
VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques
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Data Objects (2)Data Objects (2)
Three ClassesThree ClassesThree Classes
�� SignalsSignals
�� Used to communicate between processesUsed to communicate between processes
�� When declared in a package : When declared in a package : Global SignalsGlobal Signals
�� Also declared within entities, blocks, architecturesAlso declared within entities, blocks, architectures
�� Can be used but not defined in processes and Can be used but not defined in processes and subprogramssubprograms
signal CLK : BIT;
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Data Types (0)Data Types (0)
�� Each signal must have a data type associated with it when Each signal must have a data type associated with it when the signal is declaredthe signal is declared
�� A type defines a set of valuesA type defines a set of values
�� An assignment must always be of a value defined by that An assignment must always be of a value defined by that setset
�� Types in either sides of the assignment must matchTypes in either sides of the assignment must match
ConceptConceptConcept
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Data Types (1)Data Types (1)
�� The first identifier is the default valueThe first identifier is the default valuetypetype COLOR COLOR is is (RED, ORANGE, YELLOW);(RED, ORANGE, YELLOW);
type type TERNARY TERNARY isis ( '1', '0', 'X' );( '1', '0', 'X' );
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Data Types (2)Data Types (2)
�� The range must be specifiedThe range must be specified
�� No logical operations on integerNo logical operations on integertypetype MEMORY_SIZE MEMORY_SIZE is range is range 1 1 toto 2048;2048;
Integer TypesInteger TypesInteger Types
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Data Types (3)Data Types (3)
�� BOOLEANBOOLEAN : (false , true): (false , true)�� BIT BIT : ( '0' , '1' ): ( '0' , '1' )�� CHARACTERCHARACTER�� INTEGER INTEGER : range : range --2 147 483 647 to +2 147 483 6472 147 483 647 to +2 147 483 647�� NATURAL NATURAL : Subtype of : Subtype of INTEGERINTEGER (Non Negative)(Non Negative)�� POSITIVE POSITIVE : Subtype of : Subtype of INTEGERINTEGER (positive)(positive)�� BIT_VECTOR BIT_VECTOR : ar ray of BIT values: ar ray of BIT values�� STRING STRING : ar ray of : ar ray of CHARACTERSCHARACTERS
�� REAL REAL : range : range --1.0E+38 to +1.0E+381.0E+38 to +1.0E+38�� TIME TIME : Physical type used for simulation: Physical type used for simulation
Predefined VHDL Data TypesIEEE 1076-1987 Standard Package
Predefined VHDL Data TypesPredefined VHDL Data TypesIEEE 1076IEEE 1076--1987 Standard Package1987 Standard Package
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Data Types (4)Data Types (4)
�� Constrained ArrayConstrained Arraytypetype VEC_64 VEC_64 is ar ray is ar ray (0 (0 toto 63) 63) of INTEGERof INTEGER;;
var iablevar iable S : VEC_64;S : VEC_64;
var iablevar iable S1 : S1 : INTEGERINTEGER;;
S1 := S (1);S1 := S (1);
�� Unconstrained ArrayUnconstrained Arraytypetype BIT_VECTOR BIT_VECTOR is ar ray is ar ray ((POSITIVE range <>POSITIVE range <>) ) of BITof BIT;;
signalsignal S : S : BIT_VECTOR BIT_VECTOR (4(4 downtodownto 0);0);
�� MultipleMultiple DimentionalDimentional ArraysArraystypetype TWO_D TWO_D is ar ray is ar ray (0 (0 toto 7, 0 7, 0 toto 3) 3) of INTEGERof INTEGER;;
Ar ray TypesArray TypesArray Types
VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques