1 ASU MAT 591: Opportunities in Industry! ASU MAT 591: Opportunities In Industry! Subject: On-board Processing By Eric Smith Lockheed Martin- Management.

1

ASU MAT 591: Opportunities in Industry!

ASU MAT 591: Opportunities In ASU MAT 591: Opportunities In Industry!Industry!

Subject: On-board Processing

By

Eric Smith

Lockheed Martin- Management and Data Systems

2


Presentation Overview

Background– Quick overview of SAR

High level technical overview– Architectural Model– Hardware– Software– Issues

Applications Related topics

3


GFLOPS in Space!

OBP Goal:OBP Goal:> 100 GFLOPS> 100 GFLOPS< 1 KW< 1 KW< 100 KG< 100 KG

Space-based Radar Notional SatelliteSpace-based Radar Notional Satellite

4


BACKGROUNDBACKGROUND

5


The need for imaging satellites capable of continuous The need for imaging satellites capable of continuous coverage and real-time output products require high coverage and real-time output products require high

performance on-board processingperformance on-board processing

The need for imaging satellites capable of continuous The need for imaging satellites capable of continuous coverage and real-time output products require high coverage and real-time output products require high

performance on-board processingperformance on-board processing

Why On-Board Processing?

Sensor control– Adaptive controls to improve sensor performance (e.g. ECCM /

beamforming, adaptive optics) Timely delivery of intelligence / dynamic re-tasking

– Direct down link assures low latency and enables direct control by a tactical commander

– Physical antenna size precludes ultra-wide bandwidth communications link

– OBP required to reduce information bandwidth

6


OBP Applications

SAR- Synthetic Aperture Radar– Requires significant computational resources to form SAR images

~3500 operations per pixel

7


Example SAR Imagery

8


Example SAR Imagery

9


OBP ApplicationsOBP Applications

SMTI- Surface moving target indication– Radar application similar to SAR which is used to distinguish moving

targets for from the fixed background scene– Collect times are fractions of a second long– Requires combination of DSP and linear algebra to create adaptive

algorithms needed to separate the movers for scene

Metrology/Controls processing– Determining the motion of a structure so as to correct for the induced

phase errors– Integral part of a control system; very sensitive to latency

Others…

Moving Target Indicator

10


Architecture OverviewArchitecture Overview

11


Factors Driving an OBP Architecture

Algorithm/Application Requirements• Effective Flops – requirement• Memory capacity and

bandwidth

Environment• Radiation• Available Cooling

SV Constraints• Size• Weight• Operating Power

Risk Factors• Schedule• Cost

Mission Life• Design Life• Reliability

Life Cycle Cost• NRE and Recurring• O&M and upgrades

OBP Architecture

12


OBP Architecture

MUX Mod MUX Mod

Processing

Element #1

Processing

Element #1

Processing

Element #n

Processing

Element #nMUX

Fabric

MUX

Fabric

NVMSNVMS

Control ProcControl Proc

NVMSNVMS


cPCI

Bus ComputerBus Computer UARTUART

LLPLLP LLP

LLP

Output

Formatter

Output

Formatter

LLP

MEM Slice #1MEM Slice #1

MEM Slice #nMEM Slice #n LLPLLP

LLP

Link Level Protocol (LLP) 800 MBps

FromSensor

To Comm(s)

MassData Storage

Network Fabric

PE’s and Control Proc’s

13


OBP Architectural Concepts

Modular architecture with separate module types– Network infrastructure– Mass data storage– Processing elements

Sensor data processing elementsControl/general purpose processing elements

– IO Subsystem Processor configured as needed for the application

– Mix of module types is determined by requirementsPerformanceFunctionalityAvailability- N+1 versus 2N redundancy

14


Representative Performance Requirements

Performance Specifications– Processing Elements

24 Gflops per Processing Module (PM ) 56 watts 1 Gbyte/PE

– MDS 64 Gbits/slice 30 watts/slice

– Network 8x800MBps simultaneous input channels 16 PE maximum

SBR Configuration Requirements– 240 Gflops scalable to 384 Gflops for Back End Processor (BEP)– ½ Tbit– 1400watts (w/ margin)– Post-mitigation Single Event Upset (SEU) Rate

0.06 bit errors / hour

– Total Ionization Dosage (TID) Tolerance greater than 75 Mev*cm2/mg

15


H/W ArchitecturesH/W Architectures

16


Approach

Continuum of Computational Alternatives

PerformancePerformanceFlexibilityFlexibility

ASPsGPMicroprocessors

PowerPC, x86 LSP, LSP-II

FPGACommercialDSP

TI, Analog Device, TriMedia Xilinx, Atmel

•Benefit from high volume /commodity production

•Well understood HOL programming model, robust set of commercially supported tools

•Relative poor domain specific performance

•Large recurring technology investment

•Low level or HDL based programming homegrown/custom tools required

•Excellent domain specific performance

Full Custom

LL beamformer

17


FLOP/Watt Performance Comparison

Peak MFlops (MOp) /Watt for large FFT in 2002

GP + FPGA390 GP + LSPII

425Comm PPC G4

118

Rad PPC 750

7

Near Future1430

1 10 100 1000

SBR LEO Threshold

GP + FPGA/RCC120

Wideband Processing

Maxwell SCS750

23

Narrowband/General Purpose Processing

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ASU MAT 591: Opportunities in Industry! Processing Element Trade Data

Clock Power PowerCPU MHz Watts MF/W

UltraSPARC-II 248 26 3Pentium 4 2400 65 17PowerPC 750FX 1000 6 33LM-LSP+ 300 5 600LM-LSP2 300 8.3 725

Commercial Processors

Clock Power Power SEU TID LET

CPU MHz Watts MF/W Bit/Hr Krad MEV*cm2/mg

1750A 16 0.4 <1 10-13 1000 60Mongoose V 25 5 <1 << 1000 83

THOR 50 4 4 10-12 1000 284

Rad6000 33 3.7 3 10-16 1000 >120RTDSP 25 1.36 21 >> >>

RHDSP24 75 4 375 10-4 300 45RHP(Pentium) 166 10 7.5 1000 40

TSC695E 25 1 5 <10-12 300 >>

RAD750 166 5 7 10-11 200 45

LM LSP2 300 8.3 725 10-3 30 75

Virtex-II FPGA 150 8 650 10-7 100 >120

Processors Flown in Space

Rad-Tolerant Processors Being Developed

Fixed point

MF/W at thechip level based on a256K FFT

Power at thechip level

Estimate

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Background: FPGA

FPGA: Field Programmable Gate Array– Logic device whose configuration can be set to meet the specific

application requirement Two types

RAM based can be reprogrammed in the field after deployment Anti-fuse based devices can only be programmed once

– Used for prototyping, low volume applications– Features

Embedded RAM, Multiplier Arrays, and Hard IP such as RISC cores Current generation have the equivalent of a couple million logic gates

Next generation will have 10s of million logic gates

Basis for Reconfigurable Computing Paradigm

20


Example FPGA: Xilinx Vertex-II

Conf

Logic

Block

Frames

(CLB)

Conf

Logic

Block

Frames

(CLB)

BR

AM

0

BR

AM

1

21


Features of processing

DSP for image formation– Complex arithmetic

Single precision floating-point or fixed point math

– Linear shift-invariant operators FFT FIR filtering

– Extremely high data/processing rates 100’s of GFLOPS

Linear algebra for motion compensation and SMTI– Double precision– Exception handling

Heuristic & non-linear processing for backend processing– Includes “pixel polishing” and SMTI

22


Approach based on heritage systems

Enhanced Parallel Vector Supercomputer

Enhanced MPP Supercomputer

23


Reconfigurable Computing Paradigm

Utilizes FPGAs or FPGA-like devices that can be configured in such a way that is “optimal” for a specific processing task– The meaning of “optimal” depends on the criteria

Fastest time-to-market Highest throughput for the least amount of energy

Goal is to program these devices using standard S/W processes while achieving “optimal” performance– E.G. ‘C’ to circuits using a GNU compiler– Lots of on-going research with promising results

JHDL at BYU, Stream-C at LANL FORGE tool by Xilinx

– LM uses a combined Top Down/ Bottoms-up Methodology to achieve “optimal” performance based on highest FLOP/Watt criteria

24


Processing Element

FPGA Based– Gate density/performance now permits system-on-chip complexity

Available with embedded RISC processors and other IP I/O and chip package pin count limitations overcome by moving functions onto

a single chip

– Commercially supported tools and development environments– Avoids high NRE costs for advanced semiconductor processes

$1M+ mask charge in 90nm process Higher risk Requires Large on-going investment in a non-core competency Availability of vendors for low volumes uncertain (ROA thing)

Overall programming model comparable with heritage systems– Differs at the low level programming step

25


Processing Element Module (PEM)

User enabled TMR based SEU mitigation using RHBD FPGA

Maintains primitive /algorithm compatibility

GP control from external RHDB computer

• 3 sections per module

• 22.5 Gflop/s peak throughput (sustained for large FFTs)

• 1 GByte shared memory

• 8 MByte local memory per section

AcronymsRHBD Rad-hard by designTMR Triple modular redundancy

PE 3Xilinx

XC2V6000150MHz

QDR SRAM256Kx72.9 watts: 1 chip

7.5 Gflops11.6 watts650 Mflop/w

PortAConfig/SEU

110

BufD

PortBPortC

110110




110

BufC

110

BufA

110

BufB

PE 2Xilinx

XC2V6000150MHz



PortAConfig/SEU

110

BufD

PortBPortC

110110




110

BufC

110

BufA

110

BufB

PE 1Xilinx

XC2V6000150MHz



PortAConfig/SEU

110

BufD

PortBPortC 110

110




110

BufC

110

BufA

110

BufB

Interface / TMR Supervisor(Actel RTAX2000S)

40RapidIO(8-bit)

DATA STORAGEDDR SDRAM1 GBYTE12 Watts : 16 chip

115

22.5 Gigaflops51.8 watts (peak)367 Mflops/watt

40

10

40

10

40

10

POWER CONVERTER70% efficient

(22.2 Watts dissipated @ 51.8 Watt load)

I/O= 345Power= 5 watts

40RapidIO(8-bit)

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RCC Implementation Styles

Two styles used by Lockheed Martin– Optimized “Primitives”

Circuits are developed and specifically optimized for each operation type E.G Fast Fourier Transform Circuits developed using a h/w description language such as Verilog or VHDL

Collections of such circuits are implemented on a physical FPGA device Routing between these circuits implement an algorithm The FPGA is reconfigured as needed with different primitives to implement the overall algorithm

Issues Can be used where reconfiguration time is not an issue May require a large number of primitive types

– Micro-coded Function Module Group A few programmable state-machine based circuits are developed that can perform the

processing required for a class of operation types Multiple copies of such circuits are implemented and programmed separately for each

task Issues

Useful when configuration time is at issue Typically less optimal

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Example RCC Styles

PC IFPC IF DFCDFC FFTFFT RFG

QDR_Ram

A

QDR_Ram

A

QDR_Ram

B

QDR_Ram

B

QDR_Ram

C

QDR_Ram

C

PORT APORT A PORT BPORT B PORT CPORT C

Micro-coded FMG Optimized PrimitivesF

un

cti

on

Mo

du

le G

rou

p

Algorithm Partition Area

Interconnect

Fu

nc

tio

n M

od

ule

Gro

up

Fu

nc

tio

n M

od

ule

Gro

up

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H/W Abstraction Layer

Exposes germane implementation details to application developers

Standard API simplifies application development– Fosters re-use– Simplifies maintenance and spiral development

Provides a standard set of resources to the application partition– Infrastructure treated as fixed IP

Memory interface including address controller External interface Embedded controller

29


H/W Abstraction Layer

AC

FA

CF

AC

FA

CF

Algorithm Partition Area(algorithm partitions go here)

External I/F

QDRMemory

QDRMemory

QDRMemory

QDRMemory

To/From Control FPGA

Fixed IP

GP Controller

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GP Controller

AC

FA

CF

AC

FA

CF

Algorithm Partition Area(algorithm partitions go here)

External I/F

QDRMemory

QDRMemory

QDRMemory

QDRMemory

Fixed IP

GP Controller

MicroBlaze 32-bit RISC Core•Performs initialization, algorithm level sequencing and control, exception handling•Vendor supported tool suite and development H/W

•GNU, VXWorks•82 D-MIPS @ 125 MHz on Virtex-II (-5)•Instantiated Size (min): 900 cells (plus memory, peripherals)

31


FMG Approach

Consists of the resources needed to implement required arithmetic operations– Arithmetic units, local memory, and local control

Used in conjunction with the H/W abstraction layer to implement primitives– Overall primitive control encapsulated in the API

Primitive operation uses global resources that are part of the HAL

– Viewed by the application programmer as a library High level control provided by on-board RISC controller

32


Generic FM Architecture Description

Implements data path part of primitive functions– Used in conjunction with HAL/GP

Calls initiated by GP in ‘C’

Lo

cal

Mem

ory

Dat

a P

ath

Configuration Registers

Initialization & Control

Static & Dynamiccontrol

Status

Initialization

Data In

Data Out

ConditionCodes

FMG

Microcode SM

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Optimized Primitive: Radix-2 FFT

Add

Add

Add

Add

Add

Add

Mpy

Mpy

Mpy

Mpy

Dly

Out

In

Dly

Fold

Part:XC2V6000-5FF1152Part Utilization: 10% (overall)Circumscribed Area Utilization: 20%Flip flops = 11%LUTs = 7%Slices = 15%BRAMs = 6%18x18 Mpy = 11%

Power = 2.4 wattsSpeed (-5) = 5.824 ns = 171 MHz

QDR_BankA

QDR_BankB

Read Address Generator

Timing & Control

Write Address Generator

Half Butterfly

Output Multiplexer

Half Butterfly

Twiddle Generator

34


FFT Logic Placement Comparison

QDR_BankA

QDR_BankB

Read Address Generator

Timing & Control

Write Address Generator

Add

Add

Add

Add

Add

Add

Mpy

Mpy

Mpy

Mpy

Dly

Out

In

DlyTwiddleGenerator

Output Multiplexer

HalfButterfly

Fold

HalfButterfly

Manual placement Automatic placement

Manual placement results in better overall device utilization, increased performance, and is more conducive to re-use

35


Algorithm Implementation Algorithm Implementation ProcessProcess

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Example Processing Dataflow

ESA

Multi-Channel Receiver Offset A-to-D

ConvertersFilter RF

SubbandsDelay and Equalize

ESA Ch.sForm 4

GMTI Beams

FEP: “Front End” Processing

MDSConvert Fast

Time to Frequency

Correct Subbands

Resample Polar VPH

Compress Subbands to Range

Turn Range to Slow Time

Compress to Azimuth

Background Sampling Multi_Algo

Weights Calculations

Suppress Clutter / Filter Velocities

Turn Azimuth to Range

Combine Subbands

Compress Full - BW Pulses

Multi_Algo Detectors &

CFARs Multi-Algo NCI /CPI Combiners

Target Reports

OBP: “Back End” Processing

37


Decomposition to primitives

Convert Fast Time to

Frequency

Correct Subbands

Compress to Azimuth

Background Sampling

Multi_Algo Weights

CalculationsSuppress Clutter / Filter Velocities

Turn Azimuth to

Range

Combine Subbands

Compress Full - BW Pulses

Multi_Algo Detectors & CFARs

Multi-Algo NCI /CPI Combiners

Target Reports

Resample Polar VPH

Compress Subbands to

Range

Turn Range to

Slow Time

• Phase Training / Culling

• Power Selected Training

• Compute covariances

• Perform 2_D smoothing

• Eigen decomposition• Sample Matrix

Inversion• Adaptive channel

balance

• Data Format Convert (DFC)

• Mo-comp phase stabilization

• Fast time to RF xform

• Fast time sample adjust

• Fresnel quadratic removal

• Fresnel De-ripple

• (bypassed in WAS mode)

• (Staggers formation)

• Azimuth weighting• Doppler vs. Rg

sample shift in AZ

• Apply weights• (Combine staggers)• Combine 4-to-3

beams

• Incl “Burn Through Clutter Discrimination

38


Algorithm Components

Chain: Sequence of Primitives- Programmed in HOL (‘C’)

Primitive: A signal processing function (kernel) on the scale of a complete FFT or vector filtering function

Examples:

c c

RFG

Reference Function

Generator

Complex Multiply

FFT

FastFourier

Transform

Perform FFT on Signal Vector

IPF

In-PlaneFilter

Filter the Complex Signal

SQRT

Square Root

Take the Square Root of Real-

valued samples

39


Components of a Primitive

RISC Controller

HAL

API

FMG

FMG


Microcode SM

Data Path


Device Device Device

e.g. Vsma(v1, d1, x, v2, d2, d3, cnt)

void Vsma(V *v1, int d1, double x, V *v2, int d2, V *v3, int d3, int cnt){

// Init Address Generators *adr_src1_strt= v1; *adr_src1_inc= d1; *adr_src2_strt= v2; *adr_src2_inc= d2;

// Init FMG *fmg_c1= x; *mc_adr= Vsma; *mc_start= go;}

40


Primitive Development Process

Specify– Derive requirements– Develop test plan

Design– Create API

Create a high level model of the primitive in “C”

– Perform functional decomposition – Create data flow

Implement– Write HOL interface– Write microcode– Simulate– Verify

Acceptance Test Document

– Update programmer’s guide Signoff and Promote

– Update primitive library

41


Implementation Flow

Primitive Development– Bottom-up Microcoded data path Low-level initialization

Algorithm Prototyping & Implementation• Matlab©• Mathcad©• HOL

2

22exp azBfkjA

Faster, Harder,

more results….

Primitive Library Development(Off-Line)

Algorithm Development–Top-down

–Canonical S/W development environment

–Supports mixed environment•Workstation/PE•Allows rapid prototyping

SpecificationFunctional Prototype

APIPrimitive

42


Chain Development

Environment supports mixed implementation of FPGA and workstation based functional prototype primitives– During development, chains implemented as individual calls to the

PEM, possibly with FPGA reconfiguration between calls Functional prototypes used as the specification for the

FPGA implementation

c

r

DFC

Deskew Phase

ChangeFFT1

RFG2A RFG2B

FFT2 Range Ripple

Correction

c

c

Data Format

-1 +1

Synthetic Target

Phase History Generator

Emulation executed on the workstationEmulation executed on the workstation

43


Development Testbench

PEM

Testbench

Stimulus Data /OperatingStimulus Data /OperatingParametersParameters

Configuration BitConfiguration BitStreamsStreams

ResultsResults

44


Issues related to OBPIssues related to OBP

45


Issues: RadiationIssues: Radiation Two Basic Effects

– TID- Total Ionizing Dose The amount of ionizing radiation that a device can tolerate before it fails Cumulative effect that is highly dependent on the orbit and mission duration Devices that are able to withstand > 200KRads are considered radiation

tolerant Can be mitigated by shielding Causes increased current flow possibly leading catastrophic device failure

– Single event effects (SEE) Effects typically caused by high energy particles which temporarily interrupt

device operation SEU-single event upsets

» Cause registers/memory to change state resulting in incorrect results being generated SEFI- single event functional interrupts

» Causes the device to stop functioning until reset or power-cycled

SEEs rates are a function of the orbit, solar flare activity, and the device characteristics

Unaffected by shielding; requires active mitigation techniques to overcome

46


Radiation Environment

LEO– TID post-shield 2.83E+03 (no margin)

– SEU Effects Heavy Ions Flux: at 30MeV-cm2/mg =

500E-06 at 80MeV-cm2/mg = 150E-06

Galactic at 30MeV-cm2/mg = 500E-09Cosmic Rays: at 80MeV-cm2/mg = 150E-09

– Orbit: 600 Km circular, 94° inclination, 5 year MEO

– TID post-shield 67.0E+03 (no margin)

– SEU Effects Heavy Ions Flux: at 30MeV-cm2/mg =

500E-06at 80MeV-cm2/mg =

150E-06Galactic at 30MeV-cm2/mg =

500E-09Cosmic Rays: at 80MeV-cm2/mg = 150E-09

– Orbit: 10,000 Km circular, 94° inclination, 5 year

Example Equatorial Orbit,5 Years, No SAA

Orbital Altitude (1000 kilometers)

1

10

100

1000

10,000krads

1 2 3 4 5 6 7 8 9 10

Commercial ComponentCommercial ComponentRadiation RangeRadiation Range

XQVR300 SEU Rates

0.0001

0.0010

0.0100

0.1000

1.0000

10.0000

100 1,000 10,000

Orbital Altitude (km) (at 60 deg)SE

U's

per

day

Dynamic Function Upset Rate

No Upset Mitigation

Benefit of TMR and Scrub

(CREME96 & AP8max) r evised 9/ 7/ 2000

47


Latch-up

Potentially catastrophic device failure mechanism that can be brought on by prolonged exposure to a radiation environment

Parasitic BJTs within MOS transistors and the existence of path for current flow can result in the creation of an “induced” Darlington-pair transistor (2 gain).

*Digital Integrated Circuits, by Jan M. Rabaey, Prentice Hall ‘95

48


Raw Unmitigated 2V6000 Upset Rates

1000km, 90 degree inclination orbit, CREME96 GCR max – The solar-quiet ("no flare") model in CREME96 represents the ambient

environment, which prevails in the absence of solar energetic particle ("flare") events. This environment, which varies slowly in intensity over the 22-year solar cycle, is the basic environment in which all space systems must operate.

Worst Week Day (WWD) – This model is based on SEP fluxes averaged over the 180 hours (=7.5 days) beginning at 1300 UT on 19 October 1989. This week was the most severe SEP environment observed in the last two solar maxima (roughly 1980.5-83.5 and 1989.0-92.0). It can therefore be used as a "99% worst case" environment for systems designed to operate through solar maximum.

Worst Day (WD) – This model is based on SEP fluxes averaged over 18 hours beginning at 1300 UT on 20 October 1989. This period was the single largest flux enhancement in October 1989. It was caused by the arrival at Earth of a powerful interplanetary shock, which also produced a large geomagnetic storm.

Functional Block

Slices% CLB Logic

Block Ram bits CLB-FF GCR Max Worst Day

Worst Week Day

100% Device Element Utilization33792 100.0% 2,654,208 67,584 1.96E+01 8.90E+02 234.370POR SEFI 1.39E-05 1.46E-03 3.17E-04JCFG SEFI 7.19E-06 2.81E-04 7.61E-05SelectMap SEFI 1.87E-05 1.79E-03 4.31E-04

Totals: 33792 100% 100% 100% 19.568 890.125 234.370

2V6000 Raw Device Unmitigated SEU RatesFunctional Element Breakdown Upsets/device-day

49


Raw 2V6000 Upset Rates

Upsets in the CLBs dominate device upset rate

GCR Max Upsets/Dev-day vs Utilization

0.0000

2.0000

4.0000

6.0000

8.0000

10.0000

12.0000

14.0000

16.0000

18.0000

1 8 15 22 29 36 43 50 57 64 71 78 85 92 99

% Utilization

CLB Upsets

BRAM Upsets

Registers

50


Mitigated Upset Rate

Also considering the 1 in 10 functional error rate factor.– About 1 in 10 configuration errors results in a real functional error.

The mitigated upset rate .041 non-flare, 2.03 flare, per device/day

Slices% CLB Logic Block Ram bits CLB-FF GCR Max Worst Day

Worst Week Day

DDR SDRAM Controller 9018 26.69% 9228

Rapid I/O Logic 8706 25.76% 9009

R-S EDAC 2316 6.85% 192 0

DMA controller 1737 5.14% 1,336,704 2685

PCI I/F 945 2.80% 0 669

Sensor I/F 864 2.56% 13,392 2142

Software 7695 22.77% 19,872 5226

Test 1422 4.21% 1209 3.16E-01 1.43E+01 3.71E+00

Misc Logic 0 0.00% 0 0 0.00E+00 0.00E+00 0.00E+00

Voter Logic 100 0.30% 0 0 4.9E-02 2.2E+00 5.8E-01

POR SEFI 1.4E-05 1.5E-03 3.2E-04

JCFG SEFI 1.9E-05 1.8E-03 4.3E-04

SelectMap SEFI 7.2E-06 2.8E-04 7.6E-05

Totals: 32803 97.07% 58.22% 44.64% 0.365 16.456 4.292

Functional Error Reduction Factor 10 10 10

Totals 0.041 2.034 0.458

Mitigated Upset Rate/Device-day

51


Approaches to SEU Mitigation

Hard By Design– Use semiconductor technology and libraries that are inherently radiation

hard Few manufacturers Older technologies that don’t meet SWaP (and performance) requirements

TMR- Triple Mode Redundancy– The “Gold” Standard– Uses majority voting to determine the correct output from a logic block– Expensive- Requires essentially 3x the amount of H/W to implement

each function Signature Analysis

– Logic block stimulated with a known input; output checked to verify that the correct response is generated

– Can be implemented with little overhead using CRC– May be difficult to generate stimuli that provides good circuit coverage

52


Other Approaches to SEU Mitigation

Exploits characteristics of the algorithms to detect efforts– Consider the discrete Fourier transform and efficient implementations

called fast Fourier transform

– What do you know about the energy content of a signal on either side of the transform?

FFT

F()f(t)

Parseval’s Theorem:

dFFdttftf

)(*)()(*)(

53


Issues: Mission Success Fault-tolerance / graceful degradation

– The ability to continue to operate in the presence of faults perhaps at diminished capacity

– Achieved thru robust design and verified thru extensive analysis and testing Elimination of failure modes in which a single failed component could render

the entire system non-operational

Approaches– Redundancy

N+m- Incremental redundant functional A/B Side- duplicated subsystems that are cross-strapped

– Error Detection and Correction (EDAC) Used extensively in memory and network subsystems

– Reprogramming / Reconfiguration

54


Fault-tolerance

Cross-strapping N+m

MUX Mod MUX Mod

Processing

Element #1

Processing

Element #1

Processing

Element #n

Processing

Element #nMUX

Fabric

MUX

Fabric

NVMSNVMS


NVMSNVMS


NVMSNVMS


NVMSNVMS


cPCI

Bus ComputerBus Computer UARTUART

LLPLLP LLP

Output

Formatter

Output

Formatter

MEM Slice #1MEM Slice #1

MEM Slice #nMEM Slice #n LLPLLP

LLP

Link Level Protocol (LLP)

800 MBps

MassData Storage

Network Fabric

PE’s and Control Proc’s

•Employs redundancy throughout•Memory and PE modules•Data paths

•EDAC in memories and network•Reprogramability / Reconfigurability

55


In-flight changes

IncorporateModification

Data orCode +

Config FileUplink

Test andIntegration

ChangeAnalysis and

Correction

ChangeDetection

OK

OK

Failure

OBP

OBPSelf Test

ConfigFile

Uplink

TestCollection and

Processing

TES

Support Facility

EDU

Support Facility

The process being used on an operational ground based system is directly applicable to the SBR program

56


Future Generation OBPFuture Generation OBP

57


MEO Notional Design

Nominal 100m x 9m AESA feed 50 nominal phase center spacing 400 channels (1.5m x 1.5m panels) 5,000km (2,700 NM) - 15,000km (8,100

NM)

MEO SBR concept requires designers to re-think their approach: distributed processor architecture

58


Architectural Concept

Enhanced fault-tolerance

SM PP

Versatile Processing Element (VPE)

DSPEngine

f1

DSPEngine

f2

DSPEngine

f3LM

LM

Sensor Input

100m

PVPE

N/W I/F

PPC405

SM Ctl

Combination of DSP engine hard macrocell and FPGA enable overall algorithm optimization

Network of distributed processing elements reduces cost and improves fault-tolerance

NIC

OCC

1 ASU MAT 591: Opportunities in Industry! ASU MAT 591: Opportunities In Industry! Subject: On-board Processing By Eric Smith Lockheed Martin- Management.

Documents

asu mat

background slide

architecture overview

pixel slide

example sar imagery

n processing element

information bandwidth

metrologycontrols processing