0pic2_10_29_1335492453

STM32F0x System and Memories Technical Training

MCD Application TeamMCD Application TeamNovember -2011V0.2

STM32F0x Series 64KB STM32F051

RTCXTAL32KHz

M0 CORTEXTM-M0 CPU

48MHz

up to 8kB SRAM

Flash I/F

64kB/32kB FLASHMemory

DMA5 Channels

Nested vect IT Ctrl

ARMLiteHi-Speed Bus

Matrix / Arbiter (max 48MHz)

SW debugw/ ROP level2

protection

5 backup regs

20 bytes

Power SupplyPOR/PDR/PVD

HSI8MHz 1%

PLL

1 x Systick Timer

XTAL4~32MHz

STBY/VBAT

� ARM 32-bit Cortex-M0 CPU� Operating Voltage:

� VDD = 2.0 V to 3.6 V � VBAT = 1.6 V to 3.6 V

� Safe Reset System (Integrated Power On Reset (POR)/Power Down Reset (PDR) + Programmable voltage detector (PVD))

� Embedded Memories:� FLASH: up 64 Kbytes� SRAM: up 8 Kbytes

� CRC calculation unit� 5 Channels DMA� Power Supply with software configurable

internal regulator and low power modes.� Low Power Modes with Auto Wake-up� Low power calendar RTC with 20 bytes of

backup registers

Reset Clock Ctrl

CRC

Touch Sensing CtrlFast I/O interface26/39/55 w/ TS MUX

Up to 16 Ext. ITs

Matrix / Arbiter

ARM® Peripheral Bus

(max 48MHz)

1 x 12-bit ADC16ch / 1µs

T°°°°C sensor

1x 12-bit DAC

2x GP comparators

2x SPI, 1 w/ I2S

2x I²C1 w/ FM+ 20mA

2x USART

1x CEC

Win-WDG

1 x 32-bit TIMER4ch

I-WDGw/ AWU

LSI 32KHz

1 x 16-bit TIMER2ch (1ch w/ cpl/dt)

3 x 16-bit TIMER1ch (2 with cpl/dt)

STBY/VBAT

Advanced TIMER3x2ch + 1ch

1 x 16-bit TIMER4ch

1 x Basic TIMER

1

backup registers� Up to 48 MHz frequency managed &

monitored by the Clock Control w/ Clock Security System

� Rich set of peripherals & IOs� 1 × 12-bit DAC with output buffer

� 2 low power comparators (Window mode and wakeup)

� Dual Watchdog Architecture� 11 Timers w/ advanced control features

(including Cortex SysTick and WDGs)� 7 communications Interfaces� Up to 55 fast I/Os all mappable on

external interrupts/event� 1x12-bits 1Msps ADC w/ up to 16

external channels + Temperature sensor/ voltage reference/VBAT measurement

Touch Sensing Ctrl

System Architecture� Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA

� BusMatrix added to allow parallel access

� Efficient DMA and Rapid data flow

� Direct path to SRAM through arbiter, guarantees alternating access

� Von Neumann + BusMatrix allows Flash execution in parallel with DMA transfer

� Increase Peripherals Speed for better performance

� Advanced Peripheral bus (APB) architecture up to 48MHz

� Allows to optimize use of peripherals (18MBits/s SPI, 6Mbps USART, 48MHz GP-Timer, 12MHz toggling I/Os)

2

Bu

sMatrix

System

CORTEX-M3Master 1

GP-DMAMaster 2

SRAMSlave 1SRAMSlave 1

FLASHFLASHF

lash

I/F

Sla

ve 3

Fla

sh I/

FS

lave

3

AHB2APB

AHB

Slave 2 Bridges

APB

ArbiterSYSCFG, TIMs, WWD, IWWD, RTC, I2Cs, USARTs, SPI/I2Ss, HDMI-CEC,DBGMCU

RCC, CRC, Touch Sensing controller (TSC)

Buses are not overloaded

with data movement tasks

DMA AHB2GPIO GPIO A, B ,C, D, F

AHB

AHB

AHB

Slave 4 Bridge

Memory Mapping and Boot Modes

BOOT Mode

Selection Boot Mode Aliasing

BOOT1 BOOT0

x 0User Flash User Flash is selected as

boot space

0xE010 0000

0xFFFF FFFF

� Boot modesDepending on the Boot configuration, Embedded Flashmemory, System memory or Embedded SRAM memoryis aliased at @0x00. Even when aliased, these memories are still accessible from their original memory space.

� The boot configuration is defined with BOOT0 pin and BOOT1 bit from USER option byte.

� Addressable memory space of 4 Gbytes

� FLASH : up to 64 Kbytes

� RAM : up to 8 Kbytes with parity check

� 4 bits per word for parity check

� Automatic check when reading

� NMI/BRK_IN of TIM1 w/ SRAM_PARITY_LOCK bit

+ SRAM_PEF Error Flag both in SYSCFG register 2

Cortex-M0 internal peripherals0xE000 0000

Reserved

x 0boot space

1 1System memory

SystemMemory is selected as boot space

0 1Embedded SRAM

Embedded SRAM is selected as boot space

CODE

SRAM

Peripherals

0x0000 0000

0x2000 0000

0x4000 0000

Reserved

Reserved

Reserved

0x0800 0000

0x0800 FFFF

0x1FFF EC00

Flash

System Memory

Reserved

Option Bytes0x1FFF F800

0x1FFF F80C

3

Reserved � System memory : contains the Bootloader used to re-

program the FLASH through USART1 or USART2 (same pins configuration as for STM32 products).

� Boot from SRAM : In the application initialization code

you have to Relocate the Vector Table in SRAM using the

NVIC Exception Table and Offset register.

0x4800 1800

FLASH MEMORYFLASH MEMORY

Flash Features Overview� Flash general features:

� Up to 64KBytes � 64 pages of 1KBytes size and 16 Sectors of 4KBytes size (4 pages)� Endurance: 10k cycles� Access time: 35ns� Half word (16-bit) program time: 52.5µs (Typ)� Page erase time and Mass erase time: 20ms (Min), 40ms (Max)

� Flash interface features:� Read Interface with pre-fetch buffer� Read Interface with pre-fetch buffer� Option Bytes loader� Flash program/erase operations� Types of Protection:

� Readout Protection: Level 0, Level 1 and Level 2 (No debug, cut swd,no bootloader)� Write Protection

� Memory organization:� Main Program memory block (or Main Flash memory)� Information block : 3KBytes of System memory + 6 Option Bytes (12 with complements)

� 2 option bytes for write protection and 1 for Readout protection� 1 option byte for device configuration : VDDA supervisor, BOOT1, Reset w/ STDBY/STOP, IWWG HW� 2 option bytes reserved for user data

5

Flash read operations

� The embedded Flash module can be addressed directly, as a common memory space. Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data.

� The instruction fetch and the data access are both done through the same AHB bus. Read accesses can be performed with the following options managed through the Flash access control register (FLASH_ACR) :� Instruction fetch : Prefetch buffer enabled for faster CPU execution� Instruction fetch : Prefetch buffer enabled for faster CPU execution

[The prefetch buffer is ON after reset]� Latency : number of wait states for a correct read operation (0 or 1)

[48MHz is reached with only 1 wait state]

� The prefetch buffer is 3 blocks wide where each block consists of 8 bytes. It is managed by the prefetch controller which initiates a read request when there is at least one block free.

Flash memory prefetch controller�� Mission:Mission: Support 48 48 MHzMHz operation directly from Flash memory

� Flash with Prefetch based on 3× 64bits buffers

Instructions /// Data-DMA-Debug BUS

Flash memory

Prefetch controller

ARBITER ARBITER **

64 b

its

64 b

its

FLASH MEMORY

64 b

its

* The read requests are managed with following priority order :

1=Option byte loader, 2=Prog and erase operation, 3=Instr/Data fetch, 4=prefetch access

Instructions /// Data-DMA-Debug BUS ARBITER ARBITER **

32 bitsData

16-bitData

8 bitData

32 bitsThumb-2

16 bitsThumb-2

16 bitsThumb

CORTEX-M0

CPU

7

ARRAY

64 b

its

64 b

its

64 b

its

Flash program and erase operations (1/2)

� The embedded Flash memory can be programmed using � in-circuit programming (ICP) or in-application programming (IAP).

� The program and erase operations can be performed over the whole product voltage range. They are managed through the usual Flash registers.

� After reset, the Flash memory is protected against unwanted write � After reset, the Flash memory is protected against unwanted write or erase operations. The FLASH_CR register is not accessible in write mode. An unlocking sequence of KEYs should be written to the FLASH_KEYR register to open the access to the FLASH_CR register.

� The main Flash memory can be programmed 16 bits at a time. Any attempt to write data that are not half-word long will result in a bus error generating a Hard Fault interrupt.

8

Flash program and erase operations (2/2)� The embedded Flash memory can be erased page per page or

completely with Mass erase.� The information block is unaffected by Mass erase operation.

� The 6 option bytes are programmed differently from main Flash:� After unlocking the Flash access, authorize the programming of option bytes by

writing same set of KEYS to FLASH_OPTKEYR register to set the OPTWRE bit in the FLASH_CR register.

� Then set the OPTPG bit in the FLASH_CR register.� Then set the OPTPG bit in the FLASH_CR register.

� When the Flash memory read protection option is changed from protected to unprotected, a Mass Erase of the main Flash memory is performed.

� On POR reset, the option bytes loader performs a read of option bytes and stores the data into the FLASH registers (when programmed the option bytes are taken into account only after POR reset). User can also use the FORCE_OPTLOAD bit from FLASH_CR register to initiate the option bytes loader (generating SYSTEM reset).

9

Flash error/status flags and interrupts

� The Flash program and erase controller provides error and status flags with possible interrupts:� WRPERR (write protection error flag): Set by hardware when an address to be

erased/programmed belongs to a write-protected part of the Flash memory.� PGERR (programming error flag): Set by hardware when the data to program is different from

0xFFFF before programming.� EOP (End of operation): This bit is set by hardware when a Flash or Option byte operation

(program/erase) is completed.� BSY (Write/erase operations in progress)

10

Interrupt event Event flag Enable control bit

End of programming EOP EOPIE

Error

WRPERRPGAERROPTVERRSIZERR

ERRIE

Flash protections (1/6)� Two kind of protections are available:

� Write protection to avoid unwanted writings � Readout protection to avoid piracy: Level 0, Level 1 and Level 2 (No debug)� Both activated by setting option bytes

� Write protection� The write protection is implemented with a choice of protecting 4 pages (4K) at a

time it means with sector granularity.� 2 options bytes are used to protect all the 64KBytes main Flash program memory

11

� 2 options bytes are used to protect all the 64KBytes main Flash program memory� Any programming or erase of a protected page is discarded and the Flash will return

protection error flag in the FLASH_SR status register

� Un-protection� Erase the corresponding bit on WRP0 or WRP1 option bytes� Reset the device (POR Reset) or set the FORCE_OPTLOAD bit to re-load the options bytes

for disabling any write protection.

� The write protection bit values are visible also through FLASH_WRPR write protection register.

� Read protection

� The read protection is activated by setting the RDP option byte and then, by applying POR reset or using FORCE_OPTLOAD bit from FLASH_CR register to reload the new RDP option byte.

� Three levels of protection from no protection (Level 0) to maximum protection (Level 2 or No debug)

Flash Protections (2/6)

RDP byte value RDP complement value Read protection level

0xAA 0x55 Level 0

� Readout protection Level 0

� No read protection

� All operations (if no write protection is set) from/to the Flash, option byte or the RTC Backup registers are possible in all boot configurations (Flash user boot, boot RAM, boot loader or debug).

12

0xAA 0x55 Level 0

Any value but 0xAA or 0xCC

Any value (not necessarily complement) but 0x55 and 0x33

Level 1 (default)

0xCC 0x33 Level 2 (No debug)

� Readout protection Level 1

� When this protection is enabled :

� User mode: Code executing in user mode can access main Flash memory and option bytes with all operations.

� Debug, boot RAM and boot loader modes: The main Flash memory and backup registers (RTC_BKPxR in RTC) are totally inaccessible in these modes, a simple read access generates a bus error and a Hard Fault interrupt. Any attempted program/erase operations sets the PGERR flag.

Flash Protections (3/6)

� Un-protection:

� When the RPD is reprogrammed to the value 0xAA to move back to Level 0, a Mass erase of the main Flash memory is performed and the backup registers (RTC_BKPxR in RTC) are reset.

13

� Readout protection Level 2 (No debug)

� When This protection is enabled :

� All protections provided by Level 1 are active.

• Boot from RAM, boot from system memory and all debug features (serial-wire) are disabled.

Flash Protections (4/6)

• Option bytes can no longer be changed except in user mode but not totally ; RDP option byte cannot be programmed/erased and other option bytes can only be programmed (not erased).

� Un-protection:

� Not possible :level 2 cannot be removed at all: it is an irreversible operation.

14

Flash Protections (5/6)

Level 1 RDP ≠ 0xCCRDP ≠ 0xAA

Write options including RDP = 0xCC Write options including

RDP ≠ 0xAA and RDP ≠

Write options including RDP = 0xAA

RDP ≠ 0xAA and RDP ≠ 0xCCOther option(s) modified

15

Level 2 RDP=0xCC

Level 0 RDP=0xAA

Write options including RDP = 0xCC

RDP ≠ 0xAA and RDP ≠ 0xCC

RDP = 0xAAOther option(s) modified

Option byte write (RDP level increase) includes: Option byte erase and New option byte programmingOption byte write (RDP level decrease) includes: Option byte erase, New option byte programming and Mass EraseOption byte write (RDP level identical) includes : Option byte erase and New option byte programming

Flash Protections (6/6)

Area Protection level

User execution Debug, boot from RAM or boot from system memory

(loader)

Read Write Erase Read Write Erase

Main memory

1 Yes Yes Yes No No No

� Access status versus protection level and execution modes :

16

memory 2 Yes Yes Yes N/A N/A N/A

Systemmemory

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

Option bytes

1 Yes Yes Yes Yes Yes Yes

2 Yes Yes No N/A N/A N/A

Backup registers

1 Yes Yes N/A No No N/A

2 Yes Yes N/A N/A N/A N/A

Quiz

� How many (Erase/Write) cycles are available in the STM32F0x Flash ?____________

� List the all supported protections and How Enable/Disable them ?____________

� What is the Maximum Flash Read Frequency?____________

17

Same as STM32F1xx

just less channels

DIRECT MEMORY ACCESS (DMA)System Peripherals

DMA requests mapping

19

Quiz� How many DMA channels are embedded in STM32F05x?

____________

� Where are the DMA remapping bits ?____________

20

Same as STM32F1xx

but with new features

CRC CALCULATION UNIT

(CRC)

System Peripherals

CRC Features (1/3)� CRC-based techniques are used to verify storage integrity or data transmission� In functional safety standards (such as EN/IEC 60335-1), CRC peripheral offers a

means of verifying the embedded Flash memory integrity

� Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 : X32+ X26+ X23 + X22 + X16+ X12 + X11+ X10 + X8 + X7 + X5 + X4 + X2 + X + 1

AHB Bus� Single input/output 32-bit data register, but

handles 8,16 and 32-bits data size

CRC computation (polynomial:0x4C11DB7)

Data register (Input)

Data register (Output)

AHB Bus

32-bit (read access)

handles 8,16 and 32-bits data size

� CRC Peripheral is mapped to AHB bus for fast operation, CRC computation done in 4 AHB clock cycles (HCLK) maximum

� Computation duration depends on data size� 4 HCLK cycles for 32-bit � 2 HCLK cycles for 16-bit� 1 HCLK cycle for 8-bit

22

32-bit (write access)

CRC Features (2/3)

� The Input register can be accessed for write operations either :� by Cortex-M0 CPU or� In back-to-back with DMA in Memory to Memory transfer mode, keeping

CPU free for other tasks or even in sleep mode ( for power optimization)� A new Input buffer is available to avoid AHB bus stall during computation

time, thus freeing AHB1 bus for others concurrent operations

� It has also a general-purpose 8-bit register (can be used for temporary storage)� It has also a general-purpose 8-bit register (can be used for temporary storage)

� New Modes� Programmable CRC initial value, very useful when the CRC computation

is stopped then continued without re-start again in the application ( Interrupts with higher priorities, several CRC computations etc.)

� Initial value is re-loaded from CRC_INIT (32-bits register) each time a CRC reset is applied, the default value is 0xFFFF_FFFF to keep compatibility with STM32F1xx series

23

CRC Features (3/3)

� New Modes (Continued)� Reversibility on Input and Output data without extra cycles

� Output: the reversing is done at bit level only

� This replaces the same operation as “RBIT” instruction not available in

001011001100 10001000 10 00100 00010

031

000100100010 01110100 01 10000 00001

031

0x11223344

0x22CC4488

� This replaces the same operation as “RBIT” instruction not available in Cortex-M0 instruction set but is in Cortex-M3/M4 and will save many CPU cycles if done by software…

� Input : The bits reversing can be performed on 8 bits, 16 bits and 32 bits to support various endianness schemes� example if input data 0x1A2B3C4D is used for CRC calculation as:

� 0x58D43CB2 with bit-reversal done by byte� 0xD458B23C with bit-reversal done by half-word� 0xB23CD458 with bit-reversal done on the full word

24

Quiz

� Which CRC Algorithm does the STM32F0xx CRC use?____________

� How many cycles are required to compute a CRC of XX bytes from RAM ?____________

� What is the value taken in CRC computation if input is : 0x11223344 and � What is the value taken in CRC computation if input is : 0x11223344 and reversal mode is set to half word ?____________

25

POWER CONTROL (PWR)

System Peripherals

Power Supply

V

VDDA

VSSA

A/D converterD/A converterCOMPTemp. sensorReset blockPLL

VDDA domain

CoreMemories

V18 domainVDD domain

STANDBY circuitry(Wake-up logic,IWWDG, RTC, LSE crystal 32K osc,

I/O Rings

� Power Supply Schemes

� VDD = 2.0 to 3.6 V: External Power Supply for I/Os and the internal regulator.

� VDDA = 2.0 to 3.6 V: External Analog Power supplies for ADC,DAC, Reset blocks, RCs and PLL.

� ���� ADC or DAC working only if VDDA >=2.4 V

VSS

VDD

VBAT

LSE crystal 32K oscBKP registersRCC BDCR registerRTC

Backup domain

MemoriesDigitalperipherals

crystal 32K osc,RCC CSR )

Voltage Regulator

Low Voltage Detector

� VBAT = 1.8V to 3.6 V: For Backup domain when VDD is not present.

� Power pins connection:

� VDD and VDDA can be provided by a separated power supply source.

� VSS and VSSA must be tight to ground

Power Sequence

� When VDD power supply source is different from VDDA power supply source (VDD < VDDA)

� The VDDA voltage level must be always greater or equal to the VDD voltage

� During power-on, the VDDA must be provided first (before VDD)

� During power-off, it is allowed to have temporarily VDD > VDDA, but the voltage difference must be <0.4V� could be maintained by an external Schottky diode

28

Supply monitoring and Reset circuitry

� The STM32F05x POR / PDR circuitries are always active and monitor two supply voltage: VDD and VDDA.

� The POR supervisor circuit monitors only VDD

� The PDR supervisor circuit monitors VDD and VDDA� The PDR supervisor on VDDA can be disabled by programming

Option byte.

29

Option byte.

� Programmable Voltage Detection (PVD) - Can be ON/OFF.

� The PVD enable/disable is controlled by software via a dedicated bit (PVDE).

Power On Reset / Power Down Reset

� Two Integrated POR / PDR circuitries guarantees proper product reset when voltage is not in the product guaranteed voltage range (2V to 3.6V)

� No need for external reset circuit

VDD and VDDA

POR

PDR40mv hysteresis

Vtrh

Vtrl

Tempo 2.5ms� No need for external reset circuit

� POR and PDR have a typical hysteresis of 40mV

Reset

Vtrl min 1.8V / Vtrh max 2V

� The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector monitors only VDD.

Programmable Voltage Detector (PVD)

� Programmable Voltage Detector

� Enabled by software

� Monitor the VDD power supply by comparing it to a threshold

� Threshold configurable from 2.1V to

VDD

100mv hysteresis

PVD Threshold

� Threshold configurable from 2.1V to 2.9V by step of 90mV

� Generate interrupt through EXTI Line16 (if enabled) when VDD < Threshold and/or VDD > Threshold

� � Can be used to generate a

warning message and/or put the MCU into a safe state

PVD

Output

Backup Domain� Backup Domain contains

� Low power calendar RTC (Alarm, periodic wakeup from Stop/Standby)

� 20 Bytes Data RTC registers

� Separate 32kHz Osc (LSE) for RTC

� RCC BCSR register: RTC clock source selection and enable + LSE config

� Reset only by RTC domain RESET

Backup Domain

32KHz OSC(LSE)

RCC BDSRreg

Wakeup IWWDG

VBATpower switch

� VBAT independent voltage supply

� Automatic switch-over to VBAT when VDD goes lower than PDR level

� No current sunk on VBAT when VDD present

� Tamper event detection: resets all user backup registers

� TimeStamp event detection.

32

RTC + 20 Bytes Data

WakeupLogic

IWWDGVDD

RTC_TAMPx

Low Power Modes (1/4)

� SLEEP Mode: Core stopped, peripherals kept running

� Entered by executing special instructions

� WFI (Wait For Interrupt)� Exit: any peripheral interrupt acknowledged by the Nested Vectored Interrupt Controller (NVIC)

� WFE (Wait For Event)� An event can be an interrupt enabled in the peripheral control register but NOT in the NVIC or an EXTI

line configured in event mode

� Exit: as soon as the event occurs � No time wasted in interrupt entry/exit

� Two mechanisms to enter this mode

� Sleep Now: MCU enters SLEEP mode as soon as WFI/WFE instruction are executed

� Sleep on Exit: MCU enters SLEEP mode as soon as it exits the lowest priority ISR

� To further reduce power consumption you can save power of unused peripherals by gating their clock

Low Power Modes (2/4)

� STOP Mode: all periph clocks, PLL, HSI and HSE are disabled, SRAM and registers contents are preserved.

� If the RTC and IWWDG are running they are not stopped in STOP (either as their clock sources)

� To further reduce power consumption the Voltage Regulator can be put in Low Power mode

� Wake-up sources:

� WFI was used for entry: any EXTI Line configured in Interrupt mode (the corresponding EXTI

34

� WFI was used for entry: any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC)

� WFE was used for entry: any EXTI Line configured in event mode

� EXTI line source can be: one of the 16 external lines, PVD output, RTC alarm, COMPx, I2C1, USART1 or the CEC.

� The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for processing incoming data. If this is used, the voltage regulator should not be put in the low-power mode but kept in normal mode.

� After resuming from STOP the clock configuration returns to its reset state (HSI used as system clock).

Low Power Modes (3/4)

� STANDBY Mode: Voltage Regulator off, the entire V18 domain is powered off. � SRAM and register contents are lost except registers in the Backup domain and

STANDBY circuitry

� PLL, the HSI RC and the HSE crystal oscillators are also switched off.

� RTC and IWWDG are kept running in STANDBY (if enabled)

� In STANDBY mode all IO pins are high impedance and non-active except:� Reset pad (still available)

� RTC pins (if configured)� RTC pins (if configured)

� PC14 & PC15 could be forced to output high/low in RTC registers

� WKUPx pins (if enabled)

� Wake-up sources:� WKUPx pins rising edge

� RTC alarm

� External reset in NRST pin

� IWWDG reset

� � After wake-up from STANDBY mode, program execution will restart in the same way as after a RESET.

Low Power Modes (4/4)� STM32F05x Low Power modes: uses CortexM0 Sleep modes

� SLEEP, STOP and STANDBY

Feature STM32F05x typ IDD/IDDA (*)

RUN mode w/ execute from Flash on 48MHz

(HSE bypass 8MHz x 6 PLL = 48MHz) All peripherals clock ON22.9 / 0.166 (mA)22.9 / 0.166 (mA)22.9 / 0.166 (mA)22.9 / 0.166 (mA)

RUN mode w/ execute from Flash on 24MHz

(HSE bypass 8MHz x 3 PLL = 24MHz) All peripherals clock ON11.7 / 0.088 (mA)11.7 / 0.088 (mA)11.7 / 0.088 (mA)11.7 / 0.088 (mA)

RUN mode w/ execute from Flash on 8MHz

(HSI) All peripherals clock ON4.15 / 0.079 (mA)4.15 / 0.079 (mA)4.15 / 0.079 (mA)4.15 / 0.079 (mA)

Sleep mode w/ execute from Flash at 48MHz

(HSI 8MHz / 2 x 12 PLL = 48MHz) All peripherals clock ON12.9 / 0.243 (mA)12.9 / 0.243 (mA)12.9 / 0.243 (mA)12.9 / 0.243 (mA)

STOP w/ Voltage Regulator in low power

All oscillators OFF, PDR on VDDA is OFF3.6 / 1.34 (µA)3.6 / 1.34 (µA)3.6 / 1.34 (µA)3.6 / 1.34 (µA)

STANDBY w/ LSI and IWWDG OFF

PDR on VDDA is OFF1.1 / 1.21 (µA)1.1 / 1.21 (µA)1.1 / 1.21 (µA)1.1 / 1.21 (µA)

Typical values are measured at TA = 25 °C, VDD =3.3V VDDA= 3.3 V.

STM32F05x Low Power modes

Mode name Entry Wakeup

Effect on 1.8V

domain clocks

Effect onVDD

domainclocks

Voltage regulator

IO state Wakeup latency

SLEEP,SLEEP now

orSLEEP on-

exit

WFI Any interrupt CPU CLK OFF

no effect on other

clocks or analogclock

sources

None ON

All I/O pins keep the

same state as in the

Run mode

NoneWFE Wake-up event

PDDS, LPSDSR

Any EXTI line ON, in low

powerHSI RC wakeup time

Run mode

STOP

LPSDSRbits +

SLEEPDEEP bit +

WFI or WFE

Any EXTI line (configured

in the EXTI registers,internal and external

lines) All 1.8Vdomain clocksOFF

HSI andHSE andoscillator

sOFF

powermode

(dependingon

PWR_CR)

HSI RC wakeup time + regulator wakeup

time from Low-power mode

STANDBY

PDDS bit +SLEEPDEEP

bit +WFI or WFE

WKUP pin rising edge,RTC alarm, RTC tamper event, external reset in NRST pin, IWDG reset

OFF

all I/O pins are high

impedance(1)

Reset phase

37

Note (1): Standby mode: all I/O pins are high impedance except:- Reset pad (still available)- RTC pins, PC14 and PC15 if configured in the RTC registers.- WKUP pin 1 (PA0) and WKUP pin 2(PC13), if enabled.

Quiz� How many power supply domains are available?

____________

� What is the power sequence recommendation?____________

� What are the wake-up sources from STOP mode?� What are the wake-up sources from STOP mode?____________

38

RESET AND CLOCK CONTROL

(RCC)

System Peripherals

RESET Sources

� System RESET � Resets all registers except some RCC

registers and Backup domain� Sources

� Low level on the NRST pin (External Reset)

� WWDG end of count condition� IWWDG end of count condition� A software reset (through NVIC)� Low power management reset

Filter

VDD

RPU

PULSEGENERATOR

(min 20µs)

SYSTEM RESET

NRST WWDG RESETIWWDG RESET

Software RESET

Power RESET

Low power management RESET

External RESET

Standby exit

POR/PDR

Option byte loader RESET

� Low power management reset� Option byte loader reset

(FORCE_OBL bit)

� Power RESET

� Resets all registers except the Backup domain

� Sources

� Power On/Power down Reset (POR/PDR)

� Exit from STANDBY

� Backup domain RESET

� Resets in the Backup domain: RTC registers + Backup Registers + RCC_BDCR register

� Sources

� BDRST bit in RCC_BDCR register

� POWER Reset

40

Clock Features� System Clock (SYSCLK) sources:

� HSE (High Speed External osc) 4MHz to 32MHz, can be bypassed by user clock� HSI (High Speed Internal RC): factory trimmed internal RC oscillator 8MHz +/- 1%� PLL x2, x3, .. x16 (16MHz min. output freq.)

� Additional clock sources:� LSI (Low Speed Internal RC): ~40kHz internal RC� LSE (Low Speed External oscillator): 32.768kHz, can be bypassed by user clock

� configurable driving strength (power/robustness compromise) � HSI14 (High Speed Internal RC 14MHz): dedicated oscillator for ADC

� Clock-out capability on the MCO (HSI14, LSI, LSE, SYSCLK, HSI, HSE, PLL/2)� Clock-out capability on the MCO (HSI14, LSI, LSE, SYSCLK, HSI, HSE, PLL/2)

� Clock Security System (CSS) to switch to backup clock in case of HSE clock failure� Enabled by SW w/ interrupt capability linked to Cortex NMI

� RTC Clock sources: LSE, LSI and HSE clock divided by 32

� USART, I2C & CEC have multiple possible clock sources

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Clock Scheme

LSI RC

32.768KHz /32

LSE OscOSC32_IN

OSC32_OUT

~40kHz IWWDGCLK

RTCCLK

HSE

PCLK

TIMxCLKAPB

Prescaler/1,2,4,8,16

HCLK

AHB Prescaler/1, 2, ..512

/8 SysTick

CSS

HSE OscOSC_OUT

OSC_IN

4 -32 MHz

PLLCLK

8MHz

/ 2

HSE

HSI

SYSCLK

48 MHz max

PLLx2, x3, .. x16/2, 3, ..16

If (APB pres=1) x1Else x2

HSI14 RC

/2, 4

ADC

HSI RC

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HSI14

LSI

LSE

MCO SYSCLK

HSI

HSE

PLLCLK/2

SYSCLK

HSI

LSE

PCLK

LSE

HSI

SYSCLK

USART1

I2C1

CEC/244

Internal/External clock measurement using TIM14

� TIM14 input capture can be triggered by an I/O or by RTCCLK, HSE/32 or MCO signal � Purpose:� Use the precise LSE clock to measure HSI frequency; HSI used as system clock,

knowing the LSE frequency we can determine the HSI frequency (w/ the precision of the LSE)

� Measure the LSI frequency (w/ the precision of the HSE or HSI) to fine tune IWWDG and/or RTC timing

� Have rough indication of the external crystal frequency by comparing HSI (used as a system clock) and HSE/32

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MCO

HSE/32

GPIO

TIM14

TI1RTCCLK

TI1_RMP bits in TIM14_OR

HSI14

LSI

LSE

SYSCLK

HSI

HSE

PLLCLK/2

Quiz� What is new in the reset system?

____________

� What is the maximum AHB and APB clock frequencies ?____________

� What is the purpose of connecting LSE clock to TIM14 CH1 input capture and how it could be done?____________

� What is the purpose of the CSS?____________

44

Same as STM32F1xx

Window Watchdog (WWDG)System Peripherals

CMP

W0W1W2W3W4W5W6-

T0T1T2T3T4T5T6WDGA

WWDG_CR

WWDG_CFR

6-Bit Down Counter

Write WWDG_CR

comparator= 1 when

T6:0 > W6:0

WWDG Reset

WWDG features

� Configurable time-window, can be programmed to detect abnormally late or early application behavior

� Conditional reset

� Reset (if watchdog activated) when the down counter value becomes less than 40h (T6=0)

� Reset (if watchdog activated) if the down counter is reloaded outside the time-window

� To prevent WWDG reset: write T[6:0] bits (with T6 equal to 1) at regular intervals while the counter

PRESCALER (WDGTB)

PCLK

(up to 48MHz)

equal to 1) at regular intervals while the counter value is lower than the time-window value (W[6:0])

� Early Wakeup Interrupt (EWI): occurs whenever the counter reaches 40h � can be used to reload the down counter

� WWDG reset flag (in RCC_CSR) to inform when a WWDG reset occurs

� Min-max timeout value @48MHz (PCLK): 85.33µs / 43.69ms

Best suited to applications which require the watchdog to react within an accurate timing window

Refreshnot allowed

RefreshWindow

T[6:0] CNT down counter

time

W[6:0]

3Fh

T6 bit

Reset

Quiz

� When can be generated the WWDG reset?____________

� What is the maximum WWDG timeout?____________

Like STM32F1xx with added window

Independent Window Watchdog (IWWDG)

System Peripherals

IWWDG features� Selectable HW/SW start through option byte

� Advanced security features:

� IWWDG clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails

� Once enabled the IWWDG can’t be disabled (LSI can’t be disabled too)

� Safe Reload Sequence (key) + window

� IWWDG function implemented in the VDD

8-bitPRESCALER

LSI

(40KHz)

12-bit reload value

PrescalerRegister

Status Register

ReloadRegister

Key Register

IWWDG Reset

1.8V voltage domain

Window Register

12-bit down counter

� IWWDG function implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWWDG reset can wake-up from STANDBY)

� To prevent IWWDG reset: write IWWDG_KR with AAAAh key value at regular intervals before the counter reaches 0, while respecting the defined refresh window

� IWWDG reset flag (in RCC_CSR) to inform when a IWWDG reset occurs

� Min-max timeout value @40KHz (LSI): 100µs / 26.2s

Best suited to applications which require the watchdog to run as a totally independent process outside the main application

VDD voltage domain

12-bit window comp

Quiz

� Which clock feeds the IWWDG down counter?____________

� When can be generated the WWDG reset?____________

� Can the IWWDG be started by HW? How?� Can the IWWDG be started by HW? How?____________

� What is the maximum IWWDG timeout?____________

Same as STM32F-2Same as STM32F1xx

but with New features and

new Name

EXTENDED INTERRUPT/EVENT

CONTROLLER (EXTI)

System Peripherals

EXTI Features

� Manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Manager

� Some communication peripherals (UART, I2C, CEC, comparators) are able to generate events when the system is in run/sleep mode and also when the

EXTI[15:0]

Interrupt Mask Register

Pending Request Register

Software InterruptEvent Register

Rising TriggerSelection Register

To NVIC

Edge Detect Circuit

Pulse Generator

Falling TriggerSelection Register

Event Mask Register

run/sleep mode and also when the system is in stop mode allowing to wake up the system from stop mode.

� These peripherals are able to generate both a synchronized (to the system APB clock) and an asynchronous version of the event.

� All others features are same as STM32F1x series

Up to 28 Interrupt/Events requests :

Up to 55 GPIOs can be used as EXTI line(0..15)EXTI line 16 is connected to the PVD outputEXTI line 17 is connected to the RTC Alarm eventEXTI line 18 is reserved (internally held low)EXTI line 19 is connected to RTC tamper and TimestampsEXTI line 20 is reserved (internally held low)EXTI line 21 is connected to Comparator 1 outputEXTI line 22 is connected to Comparator 2 outputEXTI line 23 is connected to I2C1 wakeupEXTI line 24 is reserved (internally held low)EXTI line 25 is connected to USART1 wakeupEXTI line 26 is reserved (internally held low)EXTI line 27 is connected to CEC wakeup.

52

Quiz

� How many lines does have the Extended interrupt controller support?____________

� Which lines are mapped to a special asynchronous events ?________________________

� Which lines can be used as system wake-up ?____________

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