08.508 DSP Lab Manual Part-A

08.508 Digital Signal Processing Lab

Department of ECE, VKCET Page 1

Department of Electronics & Communication, VKCET

08.508 Digital Signal Processing Lab ManualPART-A


“Some people make things happen, some watch things happen, while others wonder what happened”


08.508 Digital Signal Processing LabSyllabus

Credits: 4

PART A: Experiments on Digital Signal Processors. 1. Sine wave generation. 2. Real Time FIR Filter implementation (Low-pass, High-pass and Band-pass) 3. Real Time IIR Filter Implementation (Low-pass, High-pass and Band-pass) 4. Pseudo Random Sequence Generator. 5. Real time DFT of sine wave. 6. Sampling a given Analog signal and study of aliasing.


08.508 Digital Signal Processing LabPrerequisite knowledge and/or skills:

• Write computer programs in an object-oriented language such as C or C++.• Understand basic linear-system concepts: linear time-shift invariance, system

functions, Laplace transforms, z-transforms.• Represent digital filters as difference equations, signal flow graphs, z-transform

system function, poles and zeroes.• Understand Fourier transform properties in continuous and discrete domains. • Understand digital filter (IIR and FIR) designing concepts.

Objectives:

• To define and use Discrete Fourier Transforms (DFTs)• To design and understand simple finite impulse response (FIR) filters• To design and understand simple infinite impulse response (IIR) filters• To train the students to design and implement practical DSP systems • To program a DSP chip TMS320C6713 to filter signals using Code Composer

Studio compiler for the chip. The student should understand how to design algorithms for implementation

Outcomes:

Students will:

a) Have the ability to conduct experiments, as well as to analyze and interpret data in various problems using MATLAB, and DSP starter kit using TMS320C6713

b) Be able to design discrete-time filters and/or implement and verify a filtering system

c) Gain knowledge of DSP and be able to design filtering methods in discrete-time domains, as well as to analyze the method in the frequency domain


08.508 Digital Signal Processing LabIndex

INTRODUCTION TO DSP STARTER KIT (DSK) USNIG TMS320C6713..........................6

SINE WAVE GENERATION AND REAL-TIME DFT USING DSK...................................24

PSEUDO RANDOM SEQUENCE GENERATOR USING DSK...........................................31

REAL TIME IIR FILTER DESIGN USING DSK...................................................................34

REAL TIME FIR FILTER DESIGN USING DSK..................................................................51

BIBLIOGRAPHY .......................................................................................................................64


08.508 Digital Signal Processing LabExpt. No. 1 INTRODUCTION TO DSP STARTER KIT (DSK) USNIG TMS320C6713

Objectives: a) To study the architecture of TMS320C6713 DSP processorb) To familiarize DSP Starter Kit (DSK) for TMS320C6713c) To familiarize Code Composer Studio (CCS) software for DSK

Equipments required:1. DSK for TMS320C67132. PC installed Software- CCS3. USB cable4. Audio stereo cable (3.5mm banana connector at one end and crocodile pin at other end)5. DSO and connecting probe

Theory:

1.1 Introduction to DSP processors:

Digital Signal Processing is the mathematics, the algorithms, and the techniques used to manipulate the signals in digital form. Signals originate as sensory data from the real world: seismic vibrations, visual images, sound waves, etc. This technology includes a wide variety of goals, such as: enhancement of visual images, recognition and generation of speech, compression of data for storage and transmission, etc.

Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. These devices can be used for variety of applications like cellular telephones to advanced scientific instruments. Hardware engineers use "DSP" to mean Digital Signal Processor, just as algorithm developers use "DSP" to mean Digital Signal Processing.

Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx family contains only CPU. There is no RAM, ROM, I/O ports and Timer

Microcontroller such as 8051 family contains CPU, RAM, ROM, I/O ports, Timer and Interrupt circuitry. Some Microcontrollers also contain ADC, DAC and Flash Memory

DSP Processors such as Texas Instruments and Analog Devices contains CPU, RAM, ROM, I/O ports and Timer. DSP processors are optimized for fast arithmetic, extended precision, dual operand fetch, zero overhead loop and circular buffering.


08.508 Digital Signal Processing LabThe basic features of a DSP Processor are:

Features Use

Fast-Multiply accumulate Most DSP algorithms, including filtering, transforms, etc. are multiplication- intensive

Multiple – Access memory architecture Many data-intensive DSP operations require reading a program instruction and multiple data items during each instruction cycle for best performance

Specialized addressing modes Efficient handling of data arrays and first-in, first-out buffers in memory

Specialized program control Efficient control of loops for many iterative DSP algorithms. Fast interrupt handling for frequent I/O operations.

On-chip peripherals and I/O interfaces On-chip peripherals like A/D converters allow for small low cost system designs. Similarly I/O interfaces tailored for common peripherals allow clean interfaces to off-chip I/O devices.

DSP Chip Manufacturers:There are various manufacturers for DSP chips. Some of the well known companies are Analog Devices, Motorola, Lucent Technologies, NEC, SGS-Thompson, Conexant, and Texas Instruments. In the lab Texas Instruments (TI) DSP chip TMS320C6713 is used. 1.2 TMS320C6713 DSP Processor

In 1983, Texas Instruments released their first generation of DSP chips, the TMS320 single-chip DSP series. The first generation chips (C1x family) could execute an instruction in a single 200-nanosecond (ns) instruction cycle. The current generation of TI DSPs includes the C2000, C5000, and C6000 series, which can run up to eight 32-bit parallel instructions in one 4.44ns instruction cycle, for an instruction rate of 1.8 x 109 instructions per second. The C2000 and C5000 series are fixed-point processors. The C6000 series contains both fixed point and floating-point processors. In the lab, we will be using the C6713 processor, a member of C67x family of floating-point processors. Features of TMS320C6713 are:

• Highest-Performance Floating-Point Digital Signal Processor (DSP): • Eight 32-Bit Instructions/Cycle • 32/64-Bit Data Word • 300, 225, 200MHz (GDP* and ZDP*), and 225, 200, 167MHz (PYP*) Clock Rates • 3.3, 4.4, 5, 6 Instruction Cycle Times • 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS #

_______________________________________________________________________________________________________________

* GDP, ZDP and PYP are the three types of Plastic Ball Grid Array IC package

# MIPS stand for 'Million Instructions Per Second' and MFLOPS stands for "Million Floating-Point Operations Per Second"


08.508 Digital Signal Processing Lab• Rich Peripheral Set, Optimized for Audio • Highly Optimized C/C++ Compiler • Extended Temperature Devices Available

Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core • Eight Independent Functional Units:

Two ALUs (Fixed-Point) Four ALUs (Floating- and Fixed-Point) Two Multipliers (Floating- and Fixed-Point)

• Load-Store Architecture With 32 32-Bit General-Purpose Registers • Instruction Packing Reduces Code Size • All Instructions Conditional• Instruction Set Features • Native Instructions for IEEE 754 • Single- and Double-Precision• Byte-Addressable (8-, 16-, 32-Bit Data) • 8-Bit Overflow Protection • Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization

L1/L2 Memory Architecture • 4K-Byte L1P Program Cache (Direct-Mapped) • 4K-Byte L1D Data Cache (2-Way) • 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and

192K-Byte Additional L2 Mapped RAM• Device Configuration • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot • Endianness*: Little Endian, Big Endian• 32-Bit External Memory Interface (EMIF) • Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM • 512M-Byte Total Addressable External Memory Space

Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) 16-Bit Host-Port Interface (HPI) Two Multichannel Audio Serial Ports (McASPs)

1. Two Independent Clock Zones Each (1 TX and 1 RX) 2. Eight Serial Data Pins Per Port:

Individually assignable to any of the Clock Zones

________________________________________________________________________________________________________Endianness is the attribute of a system that indicates whether integers are represented from left to right or right to left. Big endian is the most significant byte of any multi-byte data field is stored at the lowest memory address, which is also the address of the larger field. Little endian means that the least significant byte of any multi-byte data field is stored at the lowest memory address, which is also the address of the larger field.


08.508 Digital Signal Processing LabEach Clock Zone Includes:

1. Programmable Clock Generator 2. Programmable Frame Sync Generator 3. TDM Streams From 2-32 Time Slots 4. Support for Slot Size:

8, 12, 16, 20, 24, 28, 32 Bits 5. Data Formatter for Bit Manipulation

3. Wide Variety of I2S and Similar Bit Stream Formats 4. Integrated Digital Audio Interface Transmitter (DIT) Supports:

1. S/PDIF*, IEC60958-1, AES-3, CP-430 Formats 2. Up to 16 transmit pins 3. Enhanced Channel Status/User Data

5. Extensive Error Checking and RecoveryTwo Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces Two Multi-channel Buffered Serial Ports: 6. Serial-Peripheral-Interface (SPI) 7. High-Speed TDM Interface 8. AC97 InterfaceTwo 32-Bit General-Purpose Timers Dedicated GPIO Module with 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG#) Boundary-Scan-Compatible Package Options:

• 208-Pin PowerPAD™ Plastic (Low-Profile) Quad Flat pack (PYP) • 272-BGA Packages (GDP and ZDP)

0.13-µm/6-Level Copper Metal Process • CMOS Technology

3.3-V I/Os, 1.2-V Internal (GDP & PYP) 3.3-V I/Os, 1.4-V Internal (GDP)(300 MHz only)

_________________________________________________________________________* S/PDIF is a digital audio interconnect used in consumer audio equipment over relatively short distances. The name stands for Sony/Philips Digital Interconnect Format. S/PDIF is standardized in IEC 60958-1. IEC stands for International Electro technical Commission and is non-governmental international standards organization that prepares and publishes International Standards for all electrical, electronic and related technologies – collectively known as "electro technology". *AES3 is the digital audio standard and frequently called AES/EBU and also published as part of IEC 60958, is used for carrying digital audio signals between devices. It was developed by the Audio Engineering Society (AES) and the European Broadcasting Union (EBU)

#JTAG stands for Joint Test Action Group. It was initially devised for testing printed circuit boards using boundary scan and also widely used for IC debug ports


08.508 Digital Signal Processing Lab1.3 Architecture of TMS320C6713Functional block of TMS320C6713 processor is shown below:

Internal memory includes a two-level cache architecture with 4kB of level 1 program cache (L1P), 4kB of level 1 data cache (L1D), and 256kB of level 2 memory shared between program and data space. It has a glueless (direct) interface to both synchronous memories (SDRAM and SBSRAM) and asynchronous memories (SRAM and EPROM).

On-chip peripherals include two McBSPs (Multi-channel Buffered Serial Port), two McASPs (Multi-channel Audio Serial Port), two general purpose timers, a HPI (Host Port Interface) and a 32-bit EMIF (External Memory Interface), one dedicated GPIO (General-Purpose Input/output) module and two I2C (Inter Integrated Circuit) ports. It requires 3.3V for I/O and 1.26V for the core (internal). Internal buses include a 32-bit program address bus, a 256-bit program data bus to accommodate eight 32-bit instructions, two 32-bit data address buses, two 64-bit data buses and two 64-bit store data buses. With a 32-bit address bus, the total memory space is, including external memory spaces.

CPU Features:The CPU consists of eight independent functional units divided into two data paths, A and B, as shown in functional block. Each path has a unit for multiply operations (.M), for logical and arithmetic operations (.L), for branch, bit manipulation, and arithmetic operations (.S), and for loading/storing and arithmetic operations (.D). The eight functional units consist of four floating/ fixed-point ALUs (two .L and two .S), two fixed-point ALUs (.D units), and two floating / fixed-point multipliers (.M units). Each functional unit can read directly from or write directly to the Department of ECE, VKCET Page 10

08.508 Digital Signal Processing Labregister file within its own path. Each path includes a set of sixteen 32-bit registers, A0 through A15 and B0 through B15.Units ending in 1 write to register file A, and units ending in 2 write to register file B. Two cross-paths (1x and 2x) allow functional units from one data path to access a 32-bit operand from the register file on the opposite side. There can be a maximum of two cross-path source reads per cycle. Each functional unit side can access data from the registers on the opposite side using a cross-path (i.e., the functional units on one side can access the register set from the other side). There are 32 general-purpose registers, but some of them are reserved for specific addressing or are used for conditional instructions.

Memory Features:

Memory configuration is:


08.508 Digital Signal Processing LabMemory map range address is:


08.508 Digital Signal Processing Lab1.4 DSP Starter Kit

The TMS320C6713 DSP chip is very powerful by itself, but for development of programs, a supporting architecture is required to store programs and data, and bring signals on and off the board. In order to use this DSP chip in a lab or development environment, a circuit board containing appropriate components, designed and manufactured by TI, is provided. Together, Code Composer Studio, the DSP chip, and supporting hardware make up the DSP Starter Kit, or DSK.

Package Contents:

TMS320C6713 DSK Overview Block Diagram

The C6713 DSK has a TMS320C6713 DSP on-board that allows full-speed verification of code with Code Composer Studio. The C76713 DSK provides:Department of ECE, VKCET Page 13

08.508 Digital Signal Processing Lab1. A USB Interface2. SDRAM and ROM3. An analog interface circuit for Data conversion (AIC)4. An I/O port5. Embedded JTAG emulation support

Connectors on the C6713 DSK provide DSP external memory interface (EMIF) and peripheral signals that enable its functionality to be expanded with custom or third party daughter boards. The DSK provides a C6713 hardware reference design that can assist you in the development of your own C6713-based products. In addition to providing a reference for interfacing the DSP to various types of memories and peripherals, the design also addresses power, clock, JTAG, and parallel peripheral interfaces.

The C6711 DSK includes a stereo codec. This analog interface circuit (AIC) has the following characteristics:High-Performance Stereo Codec

• 90-dB SNR Multi-bit Sigma-Delta ADC (A-weighted at 48 kHz)• 100-dB SNR Multi-bit Sigma-Delta DAC (A-weighted at 48 kHz)• 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages• 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer

Voltages• 8 kHz, 16 kHz, 24 kHz, 32 kHz, 44 kHz, 48 kHz and 96-kHz Sampling-Frequency

SupportSoftware Control via TI McBSP-Compatible Multiprotocol Serial Port

• I2C-Compatible and SPI-Compatible Serial-Port Protocols• Glue less Interface to TI McBSPs

Audio-Data Input/output Via TI McBSP-Compatible Programmable Audio Interface• I2S-Compatible Interface Requiring Only One McBSP for both ADC and DAC• Standard I2S, MSB, or LSB Justified-Data Transfers • 16/20/24/32-Bit Word Lengths

AIC32 stereo codec line with Line In, Line Out, MIC and headphone jacks to interface with analog audio signals that are sampled and digitized so it can be processed by DSP

The C6713DSK has the following features:


08.508 Digital Signal Processing LabThe 6713 DSK is a low-cost standalone development platform that enables

customers to evaluate and develop applications for the TI C67XX DSP family. The DSK also serves as a hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.

The DSK uses the 32-bit EMIF for the SDRAM (CE0) and daughter card expansion interface (CE2 and CE3). The Flash is attached to CE1 of the EMIF in 8-bit mode.

An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP0 is used for the codec control interface and McBSP1 is used for data. Analog audio I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP1 can be re-routed to the expansion connectors in software.

A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The registers reside at the midpoint of CE1.

The DSK includes 4 LEDs and 4 DIP switches as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers.

An included 5V external power supply is used to power the board. On-board voltage regulators provide the 1.26V DSP core voltage, 3.3V digital and 3.3V analog voltages. A voltage supervisor monitors the internally generated voltage, and will hold the board in reset until the supplies is within operating specifications and the reset button is released. If desired, JP1 and JP2 can be used as power test points for the core and I/O power supplies.

Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector.

Code Composer Studio (CCS):CCS is a powerful integrated development environment that provides a useful transition

between a high-level (C or assembly) DSP program and an on-board machine Digital Signal Processing language program. CCS consists of a set of software tools and libraries for developing DSP programs, compiling and linking them into machine code, and writing them into memory on the DSP chip and on-board external memory. It also contains diagnostic tools for analyzing and tracing algorithms as they are being implemented on-board. In the lab, we will always use CCS to develop, compile, and link programs that will be downloaded from a PC to DSP hardware.


08.508 Digital Signal Processing Lab1.5 INSTALLATIONSystem Requirements:

Minimum Recommended

• 233MHz or Higher Pentium-Compatible CPU

• 600MB of free hard disk space• 128MB of RAM• SVGA (800 x 600 ) display• Local CD-ROM drive

• 500MHz or Higher Pentium – Compatible CPU

• 128MB RAM• 16bit Color

Supported Operating Systems

• Windows® 98• Windows NT® 4.0 Service Pack 4 or higher• Windows® 2000 Service Pack 1• Windows® XP

Troubleshooting DSK Connectivity:If Code Composer Studio IDE fails to configure your port correctly, perform the following steps:

1. Test the USB port by running DSK Port test from the start menuUse Start → Programs → Texas Instruments → Code Composer Studio → Code Composer Studio C6713 DSK Tools → C6713 DSK Diagnostic Utilities

ORClick on “6713 DSK Diagnostics Utilities” icon in the desktopThe below Screen will appear


08.508 Digital Signal Processing Lab2. Select → Start → Select 6713 DSK Diagnostic Utility Icon from Desktop3. The Screen Look like as above4. Select Start Option 5. Utility Program will test the board6. After testing Diagnostic Status you will get PASS

If the board still fails to detectGo to CMOS setup → Enable the USB Port Option(The required Device drivers will load along with CCS Installation)

ORReconnect USB cable, refresh the PC and do the first step

1.6 Introduction to Code Composer Studio Code Composer is the DSP industry's first fully integrated development environment

(IDE) with DSP-specific functionality. With a familiar environment liked MS-based VC++, Code Composer lets you edit, build, debug, profile and manage projects from a single unified environment. Other unique features include graphical signal analysis, injection/extraction of data signals via file I/O, multi-processor debugging, automated testing and customization via a C-interpretive scripting language and much more.CODE COMPOSER FEATURES INCLUDE:

1. IDE (Integrated Development Environment)2. Debug IDE3. Advanced watch windows4. Integrated editor5. File I/O, Probe Points, and graphical algorithm scope probes6. Advanced graphical signal analysis7. Automated testing and customization via scripting8. Visual project management system9. Compile in the background while editing and debugging10. Multi-processor debugging11. Help on the target DSP

Procedure to work on Code Composer Studio:

To create the New Project In CCS, select ‘Project’ and then ‘New’. A window named ‘Project Creation’ will appear.

In the field labeled ‘Project Name’, enter ‘Lab01’ (or your own project name). In the field ‘Location’, click on the ‘. . .’ on the right side of the field and navigate to the folder to store the file. In the field ‘Project Type’, verify that ‘Executable (.out)’ is selected, and in the field ‘Target’, verify that ‘TMS32067XX’ is selected. Finally, click on ‘Finish’. CCS has now created a project file Lab01.pjt, which will be used to build an executable program. This file is stored on specified path.



To add supporting files to project:The next step in creating a project is to add the appropriate support files to the file Lab01.

In the CCS window, go to ‘Project’ and then ‘Add Files to Project . . .’. In the window that appears, click on the folder next to where it says ‘Look In:’ Make sure that you are in the path where support files are saved. The C source code file contains functions for initializing the DSP and peripherals. The Vectors file contains information about what interrupts (if any) will be used and gives the linker information about resetting the CPU. This file needs to appear in the first block of program memory. The linker command file tells the linker how the vectors file and the internal, external, and flash memory are to be organized in memory. In addition, it specifies what parts of the program are to be stored in internal memory and what parts are to be stored in the external memory. In general, the program instructions and local/global variables will be stored in internal random access memory or IRAM. To Add Appropriate Libraries to a Project:

In addition to the support files that you have been given, there are pre-compiled files from TI that need to be included with your project. For this project, we need run-time support libraries. For the C6713 DSK, there are three support libraries needed: csl6713.lib, dsk6713bsl.lib, and rts6700.lib. The first is a chip support library, the second a board support library, and the third is a real-time support library. Besides the above support libraries, there is a GEL (general extension language) file (dsk6211 6713.gel) used to initialize the DSK. The GEL file was automatically added when the project file Lab01.pjt was created, but the other libraries must be explicitly included in the same manner as the previous files. Go to ‘Project’ and then ‘Add Files to Project’. For ‘Files of type’, select ‘Object and Library Files (*.o*,*.l*)’. Navigate to the path for support and select the files rts6700.lib . . . In the left sub-window of the CCS main window, double-click on the folder ’Libraries’ to make sure the file was added correctly.

These files, along with our other support files, form the black box that will be required for every project created in this lab. The only files that change are the source code files that code a DSP algorithm and possibly a vectors file.


08.508 Digital Signal Processing LabTo Create a Source fileFile → New → Type the code (Save & give file name, E.g.: sum.c).

To Add Source Code Files to a Project:The last file that you need to add is your C source code file. This file will contain the

code needed to perform the required task. Go back to ‘Project’ and then ‘Add Files to Project. For ‘Files of type’, select ’C/C++ source files (*.c)’, click on the file and add it to your project by clicking on ‘Open’.

Files for Non-real time programs:1. Library file- rts6700.lib

Path: C:\CCStudio_v3.1\c6000\cgtools\lib\rts6700.lib2. Command and linking file- hello.cmd

Path: C:\CCStudio_v3.1\tutorial\dsk6713\hello1\hello.cmd

Files for real time programs:1. Configuration file:

To create configuration file-File → New → DSP/BIOS Configuration

Use dsk6713.cdb Save as filename.cdb (keep same name as project, so it is easy to identify) in the project

folder and add this file to the project as similar way to other files (But file type is *.cdb). Then three files are added in generated file folder automatically. Within that open filenamecfg_c.c file and copy the line “#include”filenamecfg.h”, paste it to the source file

2. Library file: dsk6713bsl.libPath: C:\CCStudio_v3.1\c6000\\dsk6713\lib\dsk6713bsl.lib

3. Add header file generated within filenamecfg.h to source file

To Compile:Project → Compile

To Build: Project → build, which will create the final .out executable file.(Eg. sum.out).

Procedure to Load and Run program:Load the program to DSK: File → Load program → sum.out (Which is in the folder “Debug” in the project folder.)To execute project: Debug → Run.To watch variables: View → Memory

Enter the variable in the field of address and select format


08.508 Digital Signal Processing LabTo plot variables: View → Graph → Time/frequency

The following display will appear

Give the variable name in the field “Start Address” and suitable parameters for others

Procedure to run real time program:a) To connect DSK to PC

1. Connect DSO probe to the audio cord’s crocodile end and connect audio cord to Line-out pin of DSK2. Connect power supply to DSK3. Wait for POST to complete, during POST observe 1 kHz sinusoidal wave in DSO4. Connect USB cable from PC to DSK5. Launch Code Composer Studio C6713 DSK6. CCS will load and wait for your input7. Connect to C6713 DSK by Debug>Connect (or Alt+C) and verify “The target now connected” message on left corner of CCS

b) To develop and run the program for sine wave generation1. Create new project named “sine.pjt”.2. Add library file “dsk6713bsl.lib” to the project3. Create DSP/BIOS configuration file and save configuration file as

“sinewave.cdb”4. Add “sinewave.cdb” to the project5. Type the source code and save as “sinewave.c”Department of ECE, VKCET Page 20

08.508 Digital Signal Processing Lab6. Add the source code to the project7. Open “sinewavecfg_c.c” and copy - #include "sinewavecfg.h" save it to the

source code “sinewave.c”8. Compile project9. Build the project10. Load the executable file and run the program and observe sine wave and plot it

with frequency and volt

Sample programs and outputs :1.Linear convolution#include<stdio.h>#include<math.h>int y[20];int x[10]={1,2,3,2,1,0,0,0,0};int h[10]={2,1,0,1,2,0,0,0,0};main(){int l=5; int m=5; int n,k;for(n=0;n<l+m-1;n++)

{y[n]=0;for(k=0;k<=n;k++)

y[n]+= x[k]*h[n-k];}for(n=0;n<l+m-1;n++)printf("y(n)= {%d, ",y[n]);

printf(“}”);}

Result:y(n)={ 2 5 8 8 8 8 8 5 2 }Graphical display

2. Sine wave generation by look up table#include” “ //Add configuration header file here#include <math.h>#include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713.h"Department of ECE, VKCET Page 21

08.508 Digital Signal Processing Lab#include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713_aic23.h"#define SINE_TABLE_SIZE 96#define PI ( ( double )3.1415927 )#define SINE_MAX 0x7FFE //Peak value of sine waveint sinetable[SINE_TABLE_SIZE];

DSK6713_AIC23_Config config = { \ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\ 0x00ff, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \ 0x00ff, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \};void InitSineTable( void ){ int i; double increment= 0; double radian = 0;

increment = ( PI * 2 ) / SINE_TABLE_SIZE; for ( i = 0 ; i < SINE_TABLE_SIZE ; i++ ) { sinetable[i] = ( int )( sin( radian ) * SINE_MAX ); radian += increment; }}void main(){ int i;

DSK6713_AIC23_CodecHandle hCodec; DSK6713_init(); InitSineTable();

hCodec = DSK6713_AIC23_openCodec(0, &config);

DSK6713_AIC23_setFreq(hCodec, 7); //Sampling rate 96 kHz while(1)

{ for ( i = 0 ; i < SINE_TABLE_SIZE ; i++ )Department of ECE, VKCET Page 22

08.508 Digital Signal Processing Lab { while (!DSK6713_AIC23_write(hCodec, sinetable[i])); while (!DSK6713_AIC23_write(hCodec, sinetable[i])); } }}

Result:Observed the sine wave on DSO have the following specifications:Peak voltage : 1.3VFrequency : 1kHz

The look-up table contents are plotted by graph:


08.508 Digital Signal Processing LabExpt. No. 2 SINE WAVE GENERATION AND REAL-TIME DFT USING DSK

Objectives: a) To generate sine wave using TMS320C6713 DSK b) To obtain DFT of the real-time sine wave using TMS320C6713 DSK

Equipments required:

1. DSK for TMS320C67132. PC installed Software- CCS3. USB cable4. Audio stereo cable (3.5mm banana connector at one end and crocodile pin at other

end)5. DSO and connecting probe6. Function generator with connecting probe

Theory:Generating a Sinusoid in Real-Time:

In general form, sinusoidal function can be represented as

Where f0 is frequencyIn real-time digital systems, this requires samples of the above signal to be sent to

the CODEC at a fixed rate. If the sampling rate Fs = 1/ts, in C code the above equation can be written as

which is only defined for integer values of n. Here, the argument of the sine function,

is a linear function that can be easily updated at each sample point. At the next time instance, time n + 1, the argument becomes

which is the previous argument, namely θ0n, plus the phase offset

This means that the sinusoidal frequency is determined by the distance (in radians) between sample points within one 2π period of a sine wave. As long as fo < Fs/2 (θo < π), the output will have frequency fo. Using fo > Fs/2 (θo > π) will result in aliasing, which will be explored in the first assignment. This way of generating a sine wave may seem counterintuitive, since we generally fix fo and vary the sampling rate. Here, the sampling rate is fixed, so we control the frequency of the reconstructed signal by specifying the amount of radians to increment (within a Department of ECE, VKCET Page 24

08.508 Digital Signal Processing Lab2π period) at each sample point. The key idea here is that the sample rate F s is fixed and that fo is generated by carefully choosing the sample spacing (θ0 radians). Using the on-board CODEC running at Fs, it is theoretically possible to generate any sinusoid whose frequency is fo < Fs, although limitations in the smoothing filter on the analog output reduce the maximum frequency to less than Fs/2.

Real time DFT:The N-point DFT of sequence x(n) is

Where twiddle factor is

This can be decomposed into a sum of real components and a sum of imaginary components, or

Procedure:1. Sine wave generation

a) To develop and run the program for sine wave generation1. Create new project named “sine.pjt”.2. Type the source code and save as “sinewave.c”3. Add the source code to the project4. Add library file “dsk6713bsl.lib” to the project5. Create DSP/BIOS configuration file and save configuration file as

“sinewave.cdb”6. Add “sinewave.cdb” to the project7. Compile project8. Build the project9. Load the executable file and run the program and observe sine wave and plot

it with frequency and volt

b) To connect DSK to PC1. Connect DSO probe to the audio cord’s crocodile end and connect audio cord

to Line-out pin of DSK2. Connect power supply to DSK3. Wait for POST to complete, during POST observe 1 kHz sinusoidal wave in

DSO4. Connect USB cable from PC to DSK5. Launch Code Composer Studio C6713 DSKDepartment of ECE, VKCET Page 25

08.508 Digital Signal Processing Lab6. CCS will load and wait for your input7. Connect to C6713 DSK by Debug>Connect (or Alt+C) and verify “The target

now connected” message on left corner of CCS

2. DFT of Real-time sine wavea) To connect DSK to PC

1. Connect Signal generator (set as 1Vpp, 2 kHz sine wave) probe to the audio cord’s crocodile end and connect audio cord to Line-in pin of DSK

2. Connect power supply to DSK3. Wait for POST to complete4. Connect USB cable from PC to DSK5. Launch Code Composer Studio C6713 DSK6. CCS will load and wait for your input7. Connect to C6713 DSK by Debug>Connect (or Alt+C) and verify “The target

now connected” message on left corner of CCS

b) To develop and run the program for DFT of real time sinewave1. Create new project named “dftsinewave.pjt”.2. Type the source code and save as “dftsinewave.c”3. Add the source code to the project4. Add library file “dsk6713bsl.lib” to the project5. Create DSP/BIOS configuration file and save configuration file as

“dftsinewave.cdb”6. Add “dftsinewave.cdb” to the project7. Compile project8. Build the project9. Load the executable file and run the program10. Observe the input buffer and DFT sequence using View > Memory tool

Programs:1. Sine wave generation

#include "sinewavecfg.h"#include<math.h>#include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713.h"#include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713_aic23.h"

#define Fs 32000 // Sampling frequency in Hz#define f 5000 // Frequency in Hz#define pi ( ( double )3.1415927 )#define Vm 12659//Peak value of sine wave with 79uV resolution, 12659 for 1Vpp

float x[Fs/1000]; // Fs/1000 is length of sequence

DSK6713_AIC23_Config config = { \ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \Department of ECE, VKCET Page 26

08.508 Digital Signal Processing Lab 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\ 0x00ff, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \

0x00ff, /* 3 DSK6713_AIC23_LEFTHPVOL right channel headphone volume */ \ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \};

void main(){int n;float b;int N=Fs/f;double theta =2*pi*f/Fs;

DSK6713_AIC23_CodecHandle hCodec;DSK6713_init(); //Initialize board support library

hCodec = DSK6713_AIC23_openCodec(0, &config); //Open the codecDSK6713_AIC23_setFreq(hCodec, 4); //Set the sampling rate at 32 kHz

for(n=0;n<N;n++)x[n]=sin(theta * n);

while(1){

for ( n = 0 ; n < N ; n++ ){b=Vm*x[n];

while (!DSK6713_AIC23_write(hCodec, b));while (!DSK6713_AIC23_write(hCodec, b));}

}}


08.508 Digital Signal Processing Lab2. DFT of real time sine wave

#include "dftsinewavecfg.h"#include <math.h>#include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713.h"#include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713_aic23.h"

#define Fs 24000 //Sampling frequency in Hz#define f 3000 //Frequency in Hz#define pi ( ( double )3.1415927 )

Uint32 l_input; //Input buffer to store sampled data from codec. Unsigned 32 bit typeUint32 x[Fs/f]; // Intermediate buffer as input sequence. Unsigned 32 bit typefloat sumre=0, sumim=0, X_real[Fs/f]={0.0}, X_imag[Fs/f]={0.0}; //variables for DFT

DSK6713_AIC23_Config config = { \ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\ 0x00ff, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \ 0x00ff, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \};

void main(){int n,k;int N=Fs/f;

DSK6713_AIC23_CodecHandle hCodec;DSK6713_init(); //Initialize board support library

hCodec = DSK6713_AIC23_openCodec(0, &config); //Open the codecDSK6713_AIC23_setFreq(hCodec, 3); //Set the sampling rate at 24 kHz

while(1) { for ( n = 0 ; n < N ; n++ ) { while (!DSK6713_AIC23_read(hCodec, &l_input)); // Read codec

x[n]=l_input;}

for(k=0;k<N;k++){sumre=0; Department of ECE, VKCET Page 28

08.508 Digital Signal Processing Labsumim=0;for(n=0;n<N;n++)

{sumre=sumre+x[n]* cos(2*pi*k*n/N);sumim=sumim-x[n]* sin(2*pi*k*n/N);}

X_real[k]=sumre;X_imag[k]=sumim;}

}}

Results:1. Sine wave generation

a) f = 5000Hz, Fs = 32kHz and Vm =1 VppObserved the sine wave on DSO have the following specifications:Peak to peak voltage : 1VFrequency : 5 kHz

The look-up table contents are plotted by graph:

b) f = 5 kHz, Fs = 44 kHz and Vm =2 VpObserved the sine wave on DSO have the following specifications:Peak to peak voltage : 2.2VFrequency : 5.02 kHz


08.508 Digital Signal Processing LabThe look-up table contents are plotted by graph:

2. Real time DFT of sine wave a) Frequency of sine wave input 3 kHz, Peak to peak voltage 700mV and

Sampling rate of CODEC 24 kHz Observed memory variables:

x 2741 65530 65526 7 2730 6 3871 65535X_real207080.0 93811.3 -62796.99 -91531.28 -55086.0 -91531.32

-62797.03 93811.28 X_imag0.0 -61655.71 1.003906 61654.3 0.01666744 -61654.27

-0.9921875 61655.68

b) Frequency of sine wave input 10 kHz, Peak to peak voltage 1V and Sampling rate of CODEC 24 kHz

Observed memory variables:x502 24 497 30 5490 65534 65036 65504 60044 65533 493 27 5494 2 65045 65511 X_real464766.0 -145125.6 142178.2 -24076.79 -59540.98 -95025.54 -43054.16 26060.0 -59564.0 26060.03 -43054.11 -95025.62 4977.998 -30487.57 -216666.8 90570.29 X_imag0.0 -35467.02 221677.4 85607.59 -20.98047 85608.55 -36504.53 -35482.1 0.02246658 35482.09 36504.61 -85608.45 -22.98828 -85641.8 -201727.6 35438.47


08.508 Digital Signal Processing LabExpt. No. 3 PSEUDO RANDOM SEQUENCE GENERATOR USING DSK

Objective: To generate a pseudo random sequence using TMS320C6713 DSK

Equipments required:1. DSK for TMS320C67132. PC installed Software- CCS3. USB cable

Theory:Pseudorandom noise sequence generation can be implemented using maximal length

sequence (MLS) technique. MLS are also called m-sequence. MLS generator can be made from shift registers with proper feedback. If the shift generator has m bits the length of generated sequence is N=2m-1. MLS has several properties that make them good approximation to ideal binary random sequences when N is large.Frequency of Occurrence of 1’s and 0’s

The number of 1’s in one period of MLS is 2m-1 and the number of 0’s is 2m-1-1. Thus period contains one more 1 than 0. For large N, 1’s and 0’s appear with equal likelihood.Frequency of Runs of 1’s and 0’s

A run of k 1’s is defined to be a string staring with zero, followed by k 1’s and ending with a zero. In one period of MLS, there is one run of m 1’s. There is no run of m-1 1’s.Correlation property

For MLS, N=2m-1 the periodic autocorrelation function is

For ideal binary random sequence the autocorrelation function is 1 for n = 0 and 0 otherwiseRandom sequence generation

Any 16 bit sequence other than all zero sequence can be used as a seed. XOR operation of some bits in the shift register say bit b0, b2, b10and b14 is taken and then outcome is placed in a feedback variable i.e. fb as shown in figure shown below.

The register with initial seed is then shifted to the left by 1 bit. The value in the feedback variable fb is then assigned to b0 of the register.


08.508 Digital Signal Processing LabPseudo random sequence: 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1

Algorithm:1. Start2. Assign value for seed in a 16 bit register3. Set feedback bit variable as 14. If bit0 is high set pseudo random sequence, else clear5. XOR bit0, bit2, bit10 and bit14, place the result to feedback variable6. Load feedback variable to bit07. Repeat the step 4 to 6 for m times8. Stop

Program:

#include <math.h>#include <stdio.h>

typedef struct BITVAL //register bits to be packed as integer{ unsigned int b0:1, b1:1, b2:1, b3:1, b4:1, b5:1, b6:1; unsigned int b7:1, b8:1, b9:1, b10:1, b11:1, b12:1,b13:1; unsigned int b14:1, b15:1; } bitval;

typedef union SHIFT_REG{ unsigned int regval; bitval bt;} shift_reg;

short fb;shift_reg sreg; //shift reg structure

void main(){int m=16,i;short prnseq; //for pseudo-random sequencesreg.regval = 0xFFFF; //set shift registerfb = 1; //initial feedback valueprintf("Pseudo random sequence: ");for (i=0; i<m; i++)

{if(sreg.bt.b0) //sequence{0,1}based on bit b0prnseq = 1; Department of ECE, VKCET Page 32

08.508 Digital Signal Processing Labelseprnseq = 0; fb =(sreg.bt.b0)^(sreg.bt.b2); //XOR bits 0,2fb ^=(sreg.bt.b10)^(sreg.bt.b14); //with bits 10,14 ->fbsreg.regval<<=1; //shift register 1 bit to leftsreg.bt.b0 = fb; //close feedback pathprintf("%d ",prnseq);}

}

Results:Pseudo random sequence: 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0


08.508 Digital Signal Processing LabExpt. No. 4 REAL TIME IIR FILTER DESIGN USING DSK

Objective: To realize IIR low pass, high pass and band pass filters using DSK Equipments required:

1. DSK for TMS320C67132. PC installed Software- CCS3. USB cable4. Audio stereo cable (3.5mm banana connector at one end and crocodile pin at

other end)5. DSO and connecting probe6. Function generator with connecting probe

Theory:The input-output relationship of recursive system is

The transfer function is

Where N(z) and D(z) represent the numerator and denominator polynomial respectively and N is the order of the filterAlso

There are several structures to implement IIR filters; one of the most common types is direct form-II. It requires half as many delay elements as the direct form-I. For example, a second-order filter requires two delay elements z-1, as opposed to four with the direct form I. Let a delay variable U(z) be defined as

And

Taking the inverse z-transformDepartment of ECE, VKCET Page 34

08.508 Digital Signal Processing LabSolving for u(n)

Taking the inverse z-transform of Y(z)

Direct form-II IIR filter structure is shown below:

Flow chart for Real time IIR filters:


08.508 Digital Signal Processing LabFlow chart for IIR filters:

MATLAB® CODE FOR FILTER COEFFICIENTS:

1. Butterworth LP and HP filters: Specifications: Cut-off frequency: 3 KHz Sampling rate: 96000 samples/sec Filter order: 2

% LPF N=2;fc=3000;Fs=96000;wc=2*fc/Fs;[num,den]=butter(N,wc);b=ceil([num(1) num(2)/2 num(3)].*2^15-1)a=ceil([den(1) den(2)/2 den(3)].*2^15-1)freqz(num,den);title(‘IIR Butterworth LPF’);(Note: b(2) and a(2) should be divided by 2 to avoid overflow)

% HPF Department of ECE, VKCET Page 36

08.508 Digital Signal Processing LabN=2;fc=4000;Fs=44000;wc=2*fc/Fs;[num,den]=butter(N,wc,’high’);b=ceil([num(1) num(2)/2 num(3)].*2^15-1)a=ceil([den(1) den(2)/2 den(3)].*2^15-1)freqz(num,den);title(‘IIR Butterworth HPF’);

2. Butterworth BP filters: Specifications: Cut-off frequencies: 4000Hz and 8000HzSampling rate: 32000 samples/sec Filter order: 2

%BPFN=2;fc1=4000;fc2=8000;Fs=32000;wc=[2*fc1/Fs 2*fc2/Fs];[num,den]=butter(N/2,wc);b=ceil([num(1) num(2)/2 num(3)].*2^15-1)a=ceil([den(1) den(2)/2 den(3)].*2^15-1)freqz(num,den);title(‘IIR Butterworth BPF’);

3. Chebyshev type 1 LP and type 2 HP filters: Specifications: Cut-off frequency: 1.5 kHz Sampling rate: 8000 samples/sec Ripple: 10dBFilter order: 2

% LPF N=2;fc=1500;Fs=8000;R=0.5;wc=2*fc/Fs;[num,den]=cheby1(N,R,wc);b=ceil([num(1) num(2)/2 num(3)].*2^15-1)a=ceil([den(1) den(2)/2 den(3)].*2^15-1)freqz(num,den);title(‘IIR Chebyshev type 1 LPF’);


08.508 Digital Signal Processing Lab% HPF

N=2;fc=11000;Fs=96000;R=10;wc=2*fc/Fs;[num,den]=cheby2(N,R,wc,’high’);b=ceil([num(1) num(2)/2 num(3)].*2^15-1)a=ceil([den(1) den(2)/2 den(3)].*2^15-1)freqz(num,den);title(‘IIR Chebyshev type 1 HPF’);

4. Chebyshev type 2 BP filters: Specifications: Cut-off frequencies: 2000Hz and 16000HzSampling rate: 48000 samples/sec Filter order: 2 Ripple =15dB

%BPFN=2;fc1=2000;fc2=16000;Fs=48000;R=15;wc=[2*fc1/Fs 2*fc2/Fs];[num,den]=cheby1(N/2,R,wc);b=ceil([num(1) num(2)/2 num(3)].*2^15-1)a=ceil([den(1) den(2)/2 den(3)].*2^15-1)freqz(num,den);title(‘IIR Chebyshev type 2 BPF’);

The filter coefficients a and b were then saved into an ASCII text file compatible with standard C-header files or copy it and use it as constant in CCS source code

(Note: We can also use ‘fdatool’ in Matlab to generate filter coefficients) FDATOOL Filter Design & Analysis Tool. FDATOOL launches the Filter Design & Analysis Tool (FDATool). FDATool is a Graphical User Interface (GUI) that allows you to design or import, and analyze digital FIR and IIR filters.

Program:#include "iircfg.h"

#include "c:\ccstudio_v3.1\c6000\dsk6713\include\dsk6713.h"Department of ECE, VKCET Page 38

08.508 Digital Signal Processing Lab#include "c:\ccstudio_v3.1\c6000\dsk6713\include\dsk6713_aic23.h"

extern signed int IIR_FILTER(signed int ); // Sub program for IIR filter

/*filter coefficients: In Matlab b0, bi...are numerator and a0,a1,... are denominator coefficients respectively. Here b0, b1,.... are denominator and a0,a1,.... are numerator*/

/*uncomment the required filter coefficients*/const signed int b[] = { //276, 276, 276 //LPF fc=3 kHz Fs=96 kHz

// 1621, 1621, 1621 //LPF fc=8 kHz Fs= 96 kHz//20540, -20540, 20540 //HPF fc=5kHz Fs=48kHz

5436, 0, -5436 //BPF fc1=5kHz fc2=8kHz Fs=48khz};const signed int a[] = {

// 32767, -28242, 24823 //LPF fc=3 kHz Fs=96 kHz// 32767, -20965 , 15650 //LPF fc=8kHz Fs=96kHz//32767, -18174, 13047 //HPF fc=5kHz Fs=48kHz32767, -18374, 21895 //BPF fc1=5kHz fc2=8kHz Fs=48khz

};

DSK6713_AIC23_Config config = { \0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \};void main(){ DSK6713_AIC23_CodecHandle hCodec; Uint32 l_input, r_input,l_output, r_output; //IO buffer variables /* Initialize the board support library */ DSK6713_init(); /* Start the codec */Department of ECE, VKCET Page 39

08.508 Digital Signal Processing Lab hCodec = DSK6713_AIC23_openCodec(0, &config); /* Set sampling rate*/ DSK6713_AIC23_setFreq(hCodec, 6); while(1) { /* Read a sample to the left channel */

while (!DSK6713_AIC23_read(hCodec, &l_input));/* Read a sample to the right channel */

while (!DSK6713_AIC23_read(hCodec, &r_input)); l_output=IIR_FILTER(l_input);

r_output=l_output;/* Send a sample to the left channel */

while (!DSK6713_AIC23_write(hCodec, l_output));/* Send a sample to the right channel */

while (!DSK6713_AIC23_write(hCodec, r_output)); }}signed int IIR_FILTER(signed int x1){

static signed int x[6] = { 0, 0, 0, 0, 0, 0 }; /* x(n), x(n-1), x(n-2). Must be static */ static signed int y[6] = { 0, 0, 0, 0, 0, 0 }; /* y(n), y(n-1), y(n-2). Must be static */ int temp=0;

temp = (short int)x1; /* Copy input to temp */

x[0] = (signed int) temp; /* Copy input to x[stages][0] */ temp = ( (int)a[0] * x[0]) ; /* a0 * x(n) */temp += ( (int)a[1] * x[1]); /* a1/2 * x(n-1) */temp += ( (int)a[1] * x[1]); /* a1/2 * x(n-1) */temp += ( (int)a[2] * x[2]); /* a2 * x(n-2) */ temp -= ( (int)b[1] * y[1]); /* b1/2 * y(n-1) */temp -= ( (int)b[1] * y[1]); /* b1/2 * y(n-1) */temp -= ( (int)b[2] * y[2]); /* b2 * y(n-2) */ /* Divide temp by coefficients[b0] */ temp >>= 15;if ( temp > 32767 )

{ temp = 32767;

}else if ( temp < -32767) { temp = -32767; } y[0] = temp ;Department of ECE, VKCET Page 40

08.508 Digital Signal Processing Lab/* Shuffle values along one place for next time */

y[2] = y[1]; /* y(n-2) = y(n-1) */ y[1] = y[0]; /* y(n-1) = y(n) */ x[2] = x[1]; /* x(n-2) = x(n-1) */ x[1] = x[0]; /* x(n-1) = x(n) */

/* temp is used as input next time through */ return (temp<<2); }

Results:1. IIR Butterworth LPF

Specifications:Cut-off frequency: 3 kHz Sampling rate: 96000 samples/sec Filter order: 2

Desired Response:


08.508 Digital Signal Processing LabObservations:Vin = 500mVpp

f (in Hz)

Vo (in V)

Normalized f (in pi

rad/sample)

Gain in dB

100 0.9 0.0021 5.10552000 0.9 0.0417 5.10553000 0.7 0.0625 2.92264000 0.5 0.0833 0.00005000 0.4 0.1042 -1.93826000 0.3 0.1250 -4.43707000 0.2 0.1458 -7.95889000 0.1 0.1875 -13.979415000 0.04 0.3125 -21.938220000 0.03 0.4167 -24.437025000 0.02 0.5208 -27.958830000 0.01 0.6250 -33.9794

Observed response

2. IIR Butterworth HPFSpecifications:

Cut-off frequency: 4 kHz Sampling rate: 44000 samples/sec Filter order: 2


08.508 Digital Signal Processing LabDesired Response:

Observations:Vin = 500mVpp

f (in Hz)

Vo (in V)

Normalized f (in pi

rad/sample)

Gain in dB

600 0.03 0.0125 -24.4370700 0.03 0.0146 -24.4370800 0.04 0.0167 -21.9382900 0.05 0.0188 -20.00001000 0.06 0.0208 -18.41642000 0.3 0.0417 -4.43703000 0.5 0.0625 0.00004000 0.7 0.0833 2.92265000 0.8 0.1042 4.08246000 0.9 0.1250 5.10557000 1 0.1458 6.02068000 1 0.1667 6.020620000 1 0.4167 6.0206

Observed response

3. IIR Butterworth BPFSpecifications:Department of ECE, VKCET Page 43

08.508 Digital Signal Processing LabCut-off frequencies: 4 kHz and 8 khzSampling rate: 32000 samples/sec Filter order: 2

Desired Response:


f (in Hz)

Vo (in V)

Normalized f (in pi rad/sample) Gain in dB

100 0.02 0.0063 -27.9588200 0.03 0.0125 -24.4370300 0.04 0.0188 -21.9382400 0.06 0.0250 -18.4164500 0.07 0.0313 -17.0774600 0.08 0.0375 -15.9176700 0.1 0.0438 -13.97941000 0.2 0.0625 -7.95882000 0.3 0.1250 -4.43703000 0.5 0.1875 0.00004000 0.7 0.2500 2.92265000 0.9 0.3125 5.10556000 1 0.3750 6.02067000 0.9 0.4375 5.10558000 0.7 0.5000 2.92269000 0.5 0.5625 0.000010000 0.4 0.6250 -1.938212000 0.3 0.7500 -4.437014000 0.2 0.8750 -7.9588


08.508 Digital Signal Processing LabObserved response

4. IIR Chebyshev type-1 LPFSpecifications:

Cut-off frequency: 1.5kHz Sampling rate: 96000 samples/sec Filter order: 2 Ripple: 0.25

Desired Response:



f (in Hz)

Vo (in V)

Normalized f (in pi rad/sample)

Gain in dB

100 0.9 0.0021 5.1055500 0.9 0.0104 5.1055600 0.9 0.0125 5.10551000 0.9 0.0208 5.10552000 0.7 0.0417 2.92263000 0.4 0.0625 -1.93824000 0.3 0.0833 -4.43705000 0.2 0.1042 -7.95886000 0.1 0.1250 -13.97947000 0.07 0.1458 -17.07748000 0.05 0.1667 -20.00009000 0.04 0.1875 -21.938210000 0.04 0.2083 -21.938212000 0.03 0.2500 -24.437014000 0.02 0.2917 -27.958816000 0.01 0.3333 -33.979418000 0.01 0.3750 -33.979420000 0.01 0.4167 -33.9794

Observed response


08.508 Digital Signal Processing Lab5. IIR Chebyshev type-2 HPF

Specifications:Cut-off frequency: 11kHz Sampling rate: 96000 samples/sec Filter order: 2 Ripple: 10dB

Desired Response:


f (in Hz)

Vo (in V)


100 0.3 0.0021 -4.43703000 0.3 0.0625 -4.43704000 0.3 0.0833 -4.43705000 0.2 0.1042 -7.95887000 0.1 0.1458 -13.97948000 0.01 0.1667 -33.97949000 0.1 0.1875 -13.979410000 0.2 0.2083 -7.958811000 0.3 0.2292 -4.437012000 0.4 0.2500 -1.938214000 0.6 0.2917 1.583616000 0.7 0.3333 2.922618000 0.8 0.3750 4.082420000 0.9 0.4167 5.105524000 0.9 0.5000 5.105528000 0.9 0.5833 5.1055



6. IIR Chebyshev type-2 BPFSpecifications:

Cut-off frequencies: fc1= 2kHz fc2=16kHzSampling rate: 48000 samples/sec Filter order: 2 Ripple: 15dB

Desired Response



f (in Hz)

Vo (in V)


100 0.01 0.0042 -33.9794200 0.02 0.0083 -27.9588300 0.03 0.0125 -24.4370400 0.04 0.0167 -21.9382500 0.05 0.0208 -20.0000600 0.05 0.0250 -20.0000700 0.06 0.0292 -18.4164800 0.07 0.0333 -17.0774900 0.08 0.0375 -15.91761000 0.08 0.0417 -15.91762000 0.2 0.0833 -7.95883000 0.3 0.1250 -4.43704000 0.4 0.1667 -1.93825000 0.6 0.2083 1.58366000 0.9 0.2500 5.10557000 0.9 0.2917 5.10558000 0.8 0.3333 4.08249000 0.6 0.3750 1.583610000 0.5 0.4167 0.000012000 0.3 0.5000 -4.437014000 0.3 0.5833 -4.437016000 0.2 0.6667 -7.958818000 0.1 0.7500 -13.979420000 0.08 0.8333 -15.917622000 0.04 0.9167 -21.9382




08.508 Digital Signal Processing LabExpt. No. 5 REAL TIME FIR FILTER DESIGN USING DSK

Objective: To realize FIR low pass, high pass and band pass filters using DSK Equipments required:

1. DSK for TMS320C67132. PC installed Software- CCS3. USB cable4. Audio stereo cable (3.5mm banana connector at one end and crocodile pin at

other end)5. DSO and connecting probe6. Function generator with connecting probe

Theory:The non-recursive equation for Nth order FIR filter is

The transfer function is

There is different form for realizing FIR filter. A simple structure is direct form and is show below:


08.508 Digital Signal Processing LabFlow chart for real time FIR filters

Flow chart for FIR filter


08.508 Digital Signal Processing LabMATLAB® CODE FOR FILTER COEFFICIENTS:

1. LP and HP filters using rectangular window: Specifications: Cut-off frequency: 3 KHz Sampling rate: 8000 samples/sec Filter order: 20

% LPF N=20;M=N+1;fc=1000;Fs=8000;wc=2*fc/Fs;

win=rectwin(M);b=fir1(N,wc,win)a=1;freqz(b,a);title(‘FIR LPF using rectangular window’);grid on;

% HPF N=20;M=N+1;fc=1000;Fs=8000;wc=2*fc/Fs;

win=rectwin(M);b=fir1(N,wc,’high’,win)a=1;freqz(b,a);title(‘FIR HPF using rectangular window’);grid on;

2. BP filters using Kaiser window: Specifications: Cut-off frequencies: 3 KHz and 18kHzSampling rate: 96000 samples/sec Filter order: 10Beta: 4

N=20;M=N+1;fc=[5000 10000];Fs=32000; beta=4;wc=2*fc/Fs;Department of ECE, VKCET Page 53

08.508 Digital Signal Processing Lab win=kaiser(M,beta);

b=fir1(N,wc,win)a=1;freqz(b,a);title(‘FIR BPF using Kaiser window’);grid on;

Program:#include "fircfg.h"

#include "c:\ccstudio_v3.1\c6000\dsk6713\include\dsk6713.h"#include "c:\ccstudio_v3.1\c6000\dsk6713\include\dsk6713_aic23.h"

#define N 20 //Order of the filter

extern signed long FIR_FILTER(signed int ); //Subprogram for FIR filter

//Filter coefficients// Uncomment the required coefficientsconst float h[] = {//LPF, fc=1kHz, Fs=8kHz, N=20, Rectangular window/*0.0312,0.0245,-0.0000,-0.0315,-0.0519,-0.0441,0.0000,0.0734,0.1558,0.2203,0.2447,0.2203,0.1558,0.0734,0.0000,-0.0441,-0.0519,-0.0315,-0.0000,0.0245,0.0312*///HPF, fc=1kHz, Fs=8kHz, N=20, Rectangular window/*-0.0328,-0.0258,-0.0000,0.0331,0.0547,0.0464,-0.0000,-0.0773,-0.1641,-0.2320,0.7732,-0.2320,-0.1641,-0.0773,-0.0000,0.0464,0.0547,0.0331,-0.0000,-0.0258,-0.0328*///BPF, fc1=5kHz, fc2=10kHz, Fs=32kHz, N=20, Kaiser window, Beta =4/*0.0353,-0.0533,-0.0405,0.0171,-0.0175,0.0388,0.1384,-0.0625,-0.2644,0.0300,0.3184,0.0300,-0.2644,-0.0625,0.1384,0.0388,-0.0175,0.0171,-0.0405,-0.0533,0.0353*/};static short in_buffer[N]; //Buffer variable

DSK6713_AIC23_Config config = { \ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\ 0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \Department of ECE, VKCET Page 54

08.508 Digital Signal Processing Lab 0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \};

//Main programvoid main(){ DSK6713_AIC23_CodecHandle hCodec; Uint32 l_input, r_input,l_output, r_output; /* Initialize the board support library, must be called first */ DSK6713_init(); /* Start the codec */ hCodec = DSK6713_AIC23_openCodec(0, &config); /* Set sampling rate*/ DSK6713_AIC23_setFreq(hCodec, 4); while(1) {

/* Read a sample to the left channel */while (!DSK6713_AIC23_read(hCodec, &l_input));/* Read a sample to the right channel */while (!DSK6713_AIC23_read(hCodec, &r_input)); l_output=(Int16)FIR_FILTER(l_input);

r_output=l_output;/* Send a sample to the left channel */

while (!DSK6713_AIC23_write(hCodec, l_output));/* Send a sample to the right channel */

while (!DSK6713_AIC23_write(hCodec, r_output)); } }//Subprogram bodysigned long FIR_FILTER(signed int x){

int i,M;signed long y=0; //output variableM=N+1;Department of ECE, VKCET Page 55

08.508 Digital Signal Processing Labin_buffer[0] = x; // new input at buffer[0] for(i=M;i>0;i--)

in_buffer[i] = in_buffer[i-1]; // shuffle the buffer for(i=0;i<M;i++)

y += h[i] * in_buffer[i]; //filter return(y);

}Results:1. FIR LPF using rectangular window

Specifications:Cut-off frequency: 1 kHz Sampling rate: 8000 samples/sec Filter order: 20

Desired Response:



f (in Hz) Vo (in Vpp) Normalized f (in pi rad/sample) Gain in dB

100 1 0.0250 6.0206700 1 0.1750 6.0206800 0.9 0.2000 5.1055900 0.7 0.2250 2.92261000 0.5 0.2500 0.00001100 0.3 0.2750 -4.43701200 0.06 0.3000 -18.41641300 0.1 0.3250 -13.97941400 0.12 0.3500 -12.39581500 0.08 0.3750 -15.91761600 0.04 0.4000 -21.93821700 0.08 0.4250 -15.91761800 0.09 0.4500 -14.89451900 0.06 0.4750 -18.41642000 0.04 0.5000 -21.93822100 0.07 0.5250 -17.07742200 0.08 0.5500 -15.91762300 0.06 0.5750 -18.41642400 0.04 0.6000 -21.93822500 0.06 0.6250 -18.41642600 0.08 0.6500 -15.91762700 0.06 0.6750 -18.41642800 0.04 0.7000 -21.93822900 0.06 0.7250 -18.41643000 0.08 0.7500 -15.91763100 0.06 0.7750 -18.41643200 0.04 0.8000 -21.93823300 0.06 0.8250 -18.41643400 0.06 0.8500 -18.41643500 0.06 0.8750 -18.41643600 0.04 0.9000 -21.93823700 0.05 0.9250 -20.00003800 0.05 0.9500 -20.0000

Observed response:



2. FIR HPF using rectangular windowSpecifications:

Cut-off frequency: 1 kHz Sampling rate: 8000 samples/sec Filter order: 20

Desired Response:


08.508 Digital Signal Processing LabObservations:

f (in Hz) Vo (in V) Normalized f (in

pi rad/sample) Gain in dB

100 0.02 0.0250 -27.9588200 0.02 0.0500 -27.9588250 0.03 0.0625 -24.4370300 0.03 0.0750 -24.4370350 0.03 0.0875 -24.4370400 0.02 0.1000 -27.9588450 0.02 0.1125 -27.9588500 0.03 0.1250 -24.4370550 0.04 0.1375 -21.9382600 0.06 0.1500 -18.4164650 0.06 0.1625 -18.4164700 0.06 0.1750 -18.4164750 0.04 0.1875 -21.9382800 0.06 0.2000 -18.4164850 0.12 0.2125 -12.3958900 0.22 0.2250 -7.1309950 0.34 0.2375 -3.34981000 0.6 0.2500 1.58361100 0.7 0.2750 2.92261200 0.9 0.3000 5.10551300 1 0.3250 6.02063300 1 0.8250 6.0206

Observed response:


08.508 Digital Signal Processing Lab2. FIR BPF using Kaiser window

Specifications:Cut-off frequencies: 5 kHz and 10 kHzSampling rate: 32000 samples/sec Filter order: 20 Beta: 2

Desired Response:


08.508 Digital Signal Processing LabObservations:

f (in Hz) Vo (in V) Normalized f (in pi

rad/sample) Gain in dB

500 0.02 0.0313 -27.9588600 0.02 0.0375 -27.9588700 0.01 0.0438 -33.9794800 0.01 0.0500 -33.9794900 0.02 0.0563 -27.95881000 0.02 0.0625 -27.95881400 0.02 0.0875 -27.95881500 0.02 0.0938 -27.95881600 0.03 0.1000 -24.43701700 0.03 0.1063 -24.43701800 0.03 0.1125 -24.43701900 0.02 0.1188 -27.95882000 0.02 0.1250 -27.95882100 0.01 0.1313 -33.97942400 0.02 0.1500 -27.95882500 0.02 0.1563 -27.95882600 0.03 0.1625 -24.43702700 0.03 0.1688 -24.43702800 0.04 0.1750 -21.93822900 0.05 0.1813 -20.00003200 0.05 0.2000 -20.00003300 0.04 0.2063 -21.93823400 0.03 0.2125 -24.43703500 0.02 0.2188 -27.95883600 0.01 0.2250 -33.97943700 0.03 0.2313 -24.43703800 0.04 0.2375 -21.93823900 0.07 0.2438 -17.07744000 0.09 0.2500 -14.89454100 0.12 0.2563 -12.39584200 0.16 0.2625 -9.89705000 0.5 0.3125 0.00006000 0.9 0.3750 5.11


08.508 Digital Signal Processing Labf (in Hz) Vo (in V) Normalized f (in pi

rad/sample) Gain in dB

7000 1 0.4375 6.02068000 1 0.5000 6.02069000 0.9 0.5625 5.105510000 0.5 0.6250 0.000010500 0.26 0.6563 -5.679911000 0.08 0.6875 -15.917611200 0.04 0.7000 -21.938211300 0.04 0.7063 -21.938211400 0.03 0.7125 -24.437011500 0.04 0.7188 -21.938211600 0.04 0.7250 -21.938211700 0.05 0.7313 -20.000012200 0.05 0.7625 -20.000012300 0.04 0.7688 -21.938212400 0.03 0.7750 -24.437012600 0.02 0.7875 -27.958812700 0.01 0.7938 -33.979412800 0.02 0.8000 -27.958812900 0.03 0.8063 -24.437013000 0.03 0.8125 -24.437013100 0.04 0.8188 -21.938213800 0.04 0.8625 -21.938213900 0.03 0.8688 -24.437014000 0.03 0.8750 -24.437014100 0.02 0.8813 -27.958814200 0.01 0.8875 -33.979414500 0.01 0.9063 -33.979414600 0.02 0.9125 -27.958814900 0.02 0.9313 -27.9588


08.508 Digital Signal Processing LabObserved response:


08.508 Digital Signal Processing LabBIBLIOGRAPHY

Text Books:

1. Rulph Chassaing - DSP Applications Using C and the TMS320C6x DSK

2. Paul M Embree – C Algorithms for Real-time DSP

3. TMS320C6713 Data sheet

4. User Manual of DSK for TMS320C6713

References:

1. John G. Proakis & Dimitris K Manolakis - Digital Signal Processing

2. Alan V. Oppenheim Ronald W. Schafer - Discrete-Time Signal Processing

3. Steven W. Smith - The Scientist & Engineer's Guide to Digital Signal Processing

4. Sanjit K. Mitra - Digital Signal Processing – Computer Based Approach

5. Nasser K - Real Time Digital Signal Processing Based on the TMS320C6000

6. Edmund Lai – Practical Digital Signal Processing


08.508 DSP Lab Manual Part-A

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