Term Project: Single Bus Processor Design and simulate the LC -3 processor Design and simulate the LC -3 processor using VHDL Register Files Register File consists of 8 registers: n Two 16-bit output busses: SR1 and SR2 n One 16-bit input bus: DR SelSR1 SelSR2 SR1 SR1 SelSR1 SelSR2 16 3 3 3 Register is selected by: n SelSR1 selects the register to put on SR1 n SelSR2 selects the register to SelDR DR SR2 DRin SR2 DR SelDR CLK 16 16 3 put on SR2 n SelDR selects the register to be written via DR when DRin is 1 Behaves as a combinational logic block: w SelSR1 or SelSR2 valid = > SR1 LC- 3 Architecture 2 w SelSR1 or SelSR2 valid = > SR1 or SR2 valid after “ access time. ” Register Files 3 SelSR1 16 DR R0 R1 R2 R3 mux ... 16 16 SR1 Decoder R4 R5 R6 R7 mux ... 16 SR2 ... Decoder LC-3 Architecture 3 3 SelSR2 3 SelDR DRin Clock Single Bus Architecture Accumulator based architecture 16 SelDR R0 R1 R2 R3 R4 R5 R6 R7 SelDR DRin MDR MAR Memory Unit R7 16 16 16 SelSR1 SelSR2 Src1 Src2 ALUop PC IR Control Unit LC- 3 Architecture 4 Internal System Bus Unit
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Term Project:Single Bus Processor
Design and simulate the LC-3 processor Design and simulate the LC-3 processor using VHDL
Register Files
Register File consists of 8 registers:n Two 16-bit output busses: SR1 and SR2n One 16-bit input bus: DR
SelSR1
SelSR2SR1 SR1
SelSR1
SelSR216
163
3
3
Register is selected by:n SelSR1 selects the register to
put on SR1n SelSR2 selects the register to
put on SR2 SelDR
DR
SR2
DRin
SR2
DR
SelDR
CLK
16
163put on SR2n SelDR selects the register to be
written via DR when DRin is 1
Behaves as a combinational logic block:
w SelSR1 or SelSR2 valid = > SR1
LC-3 Architecture 2
w SelSR1 or SelSR2 valid = > SR1 or SR2 valid after “access time.”
Register Files
3SelSR1
16DR
R0
R1
R2
R3
R4
mux...
16
16 SR1
Decoder R4
R5
R6
R7
mux
...
16 SR2
...
Decoder
LC-3 Architecture 3
3
SelSR23
SelDR DRin Clock
Single Bus Architecture
Accumulator based architecture16SelDR MAR
R0R1R2R3R4R5R6R7
16SelDRDRin
MDR
MARMemory
Unit
R7
1616
16
SelSR1SelSR2
Src1Src2ALUop
PC
IRControl
Unit
LC-3 Architecture 4
InternalSystem
Bus
Unit
I nstruction Set Architecture
ISA = All of the programmer-visible components and operations of the computer
memory organizationn memory organizationw address space -- how may locations can be addressed?w addressibility -- how many bits per location?
n register setw how many? what size? how are they used?
n instruction setopcodesw opcodes
w data typesw addressing modes
ISA provides all information needed for someone that wants towrite a program in machine language (or translate from a high-level language to machine language).
LC-3 Architecture 5
(or translate from a high-level language to machine language).
Registersn temporary storage, accessed in a single machine cycle
w accessing memory generally takes longer than a single cycle
n eight general-purpose registers: R0 - R7n eight general-purpose registers: R0 - R7w each 16 bits widew R7 is used to store the return address in subroutine jumpw how many bits to uniquely identify a register?
n other registersw not directly addressable, but used by (and affected by) instructions
LC-3 Architecture 6
w not directly addressable, but used by (and affected by) instructionsw PC (program counter), CC (condition codes), MAR (memory address
register), MDR (memory data register)
I nstruction Set
Opcodesn 15 opcodesn Operate instructions: ADD, AND, NOTn Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STIn Control instructions: BR, JSR, JMP, RET, TRAPn some opcodes set/clear condition codes, based on result:
w N = negative, Z = zero, C = carry
Data TypesData Typesn 16-bit 2’s complement integer
Addressing Modesn How is the location of an operand specified?n non-memory addresses: immediate, register
Source and destination operands are registersn These instructions do not reference memory.n ADD and AND can use “immediate”mode,
where one operand is hard-wired into the instruction.
LC-3 Architecture 8
Data Movement I nstructions
Load -- read data from memory to registern LD: PC-relative moden LDR: base+offset moden LDI: indirect mode
Store -- write data from register to memoryn ST: PC-relative moden ST: PC-relative moden STR: base+offset moden STI: indirect mode
Load effective address -- compute address, save in register
LC-3 Architecture 9
registern LEA: immediate moden does not access memory
Control I nstructions
Used to alter the sequence of instructions(by changing the Program Counter)
Conditional Branch : BR[nzc]n branch is taken if a specified condition is true
w signed offset is added to PC to yield new PCn else, the branch is not takenn else, the branch is not taken
w PC is not changed, points to the next sequential instruction
Unconditional Branch : JMP, JSR, RETn always changes the PC
TRAP
LC-3 Architecture 10
TRAPn changes PC to the address of an OS “service routine”n routine will return control to the next instruction (after TRAP)
Branch I nstructionBranch specifies one or more condition codes.
I f the set bit is specified, the branch is taken.
n PC-relative addressing: target address is made by adding signed offset (IR[8:0])
R1 ← x3100R3 ← 0R2 ← 12
R4 ← M[R1]R3 ← R3+R4
adding signed offset (IR[8:0]) to current PC.
n Note: PC has already been incremented by FETCH stage.
n Note: Target must be within 256 words of BR instruction.
R2=0? R3 ← R3+R4R1 ← R1+1R2 ← R2-1
NO
YES
LC-3 Architecture 11
256 words of BR instruction.
I f the branch is not taken, the next sequential instruction is executed.
Condition Codes
LC-3 has three condition code registers:N -- negativeZ -- zeroZ -- zeroC -- carry
Set by any instruction that writes a value to a register(ADD, AND, NOT, LD, LDR, LDI, LEA)(ADD, AND, NOT, LD, LDR, LDI, LEA)
Exactly one will be set at all timesn Based on the last instruction that altered a register
LC-3 Architecture 12
I nstruction Format
opcode reg reg 0 reg0 0
opcode reg reg 1 offset5
opcode reg reg 0 reg0 0
opcode reg offset9
opcode reg offset6reg
opcode reg offset9
opcode offset111
opcode 0 0 0 0 0 0reg0 0 0
LC-3 Architecture 13
opcode offset80 0 0 0
Register Addressing Modes
NOT R3, R5R0R1NOT R3 R5
0101 0000 1111 0000
1010 1111 0000 1111
R1R2R3R4R5R6R7
1001 011 101 111111IR
NOT R3 R5
NOT
16
16
16
LC-3 Architecture 14
Immediate Addressing Mode
Immediate field is sign-extended
0000 0000 0000 0100R0
ADD R1 R4 -2
ADD R1, R4, # -2
0000 0000 0000 0100
0000 0000 0000 0110
R1R2R3R4R5R6R7
0001 001 100 1 11110IR
ADD R1 R4 -2
SEXT
1111 1111 1111 1110
5
16
1111 1111 1111 1110
ADD
16
16
16
LC-3 Architecture 15
PC-Relative Addressing Mode
Want to specify address directly in the instructionn But an address is 16 bits, and so is an instruction!n After subtracting 4 bits for opcode and 3 bits for register, we
have 9 bits available for address.
Solution:n Use the 9 bits as a signed offset from the current PC.Use the 9 bits as a signed offset from the current PC.
9 bits:Can form any address X, such that:
Remember that PC is incremented as part of the FETCH phase;
255offset256 +≤≤−255PCX256PC +≤≤−
LC-3 Architecture 16
Remember that PC is incremented as part of the FETCH phase;This is done before the EVALUATE ADDRESS stage.
PC-Relative Addressing Mode
LD R2, x1AFR0
LD R2 x1AF
0100 0000 0001 1001PC
0000 0000 0000 0101R1R2R3R4R5R6R7
0010 010 110101111IR
LD R2 x1AF
SEXT
1111 1111 1010 1111
9
16
1111 1111 1010 1111
ADD
16
16
16
16
LC-3 Architecture 17
MAR MDR
Memory
16 16
Base + Offset Addressing Mode
With PC-relative mode, can only address data within 256 words of the instruction.n What about the rest of memory?
Solution # 2:n Use a register to generate a full 16-bit address.
4 bits for opcode, 3 for src/dest register,3 bits for baseregister -- remaining 6 bits are used as a signed offset.
n Offset is sign-extended before adding to base register.