06CSL38ManualLD

1

Electronic Circuits and Logic Design Laboratory

List of Experiments

Part A

Sl.No Experiment Name

1 a. To study the working of positive clipper, double –ended clipper and positive clamper

using diodes.

OR

b. To build and simulate the above circuits using a simulation package

2 a. To determine the frequency response, input impedance, output impedance, and bandwidth

of a CE amplifier.

OR

b. To build the CE amplifier circuit using a simulation package and determine the voltage

gain for two different values of supply voltage and for two different values of emitter

resistance.

3 a.To determine the drain characteristics and transconductance characteristics of an

enhancement-mode MOSFET.

OR

b. To implement a CMOS inverter using a simulation package and verify its truthtable.

4 a. To design and implement a Schmitt trigger using Op-Amp for given UTP and LTP values.

OR

b. To implement a Schmitt trigger using Op-Amp using a simulation package for two sets of

UTP and LTP values.

5 a. To design and implement a rectangular waveform generator (Op-Amp relaxation

oscillator) for given frequency.

OR

b. To implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a

simulation package and observe the change in frequency when all resistor values are

doubled.

6 To design and implement an astable multivibrator circuit using 555 timer for a given

frequency and duty cycle.

7 To implement a +5V regulated power supply using full-wave rectifier and 7805 IC regulator

in simulation package. Find the output ripple for different values of load current.

Part B

1 a. Given any 4-variable logic expression, simplify using Entered Variable Map and realize

the simplified logic expression using 8:1 multiplexer IC.

b. Write the Verilog /VHDL code for an 8:1 multiplexer. Simulate and verify its working.

2 a. Realize a full adder using 3-to-8 decoder IC and 4 input NAND gates.

b. Write the Verilog/VHDL code for a full adder. Simulate and verify its working.

3 a. Realize a J-K Master/Slave Flip-Flop using NAND gates and verify its truth table.

OR

2

b. Write the Verilog/VHDL code for D Flip-Flop with positive-edge triggering. Simulate

and verify its working.

4 a. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs.

OR

b. Write the Verilog/VHDL code for mod-8 up counter. Simulate and verify its working.

5 a. Design and implement a ring counter using 4-bit shift register.

b. Write the Verilog/VHDL code for switched tail counter. Simulate and verify its working.

6 Design and implement an asynchronous counter using decade counter IC to count up from 0

to n (n<=9).

7 Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy and

resolution.

GENERAL INTRODUCTION TO PSPICE

Why simulate circuits?

In order to ensure a successful circuit design and mitigate costly and potentially dangerous

design flaws, careful planning and evaluation must occur at every stage of the process.

Circuit simulation provides a cost-effective and efficient method for identifying faults before

moving to the more expensive and time-consuming prototyping stage. Including simulation

in the design process reduces design errors and speeds the design cycle by allowing you to

predict and better understand circuit behavior.

The main purpose of simulation is to predict and understand the behavior of electronic

circuits. Experiment with ―What-if‖ Scenarios.

Limitations of simulation

Simulation is never meant to replace prototyping. Certain real-world effects, like cross-talk,

electromagnetic noise, and spurious line noise, can be too difficult, time-consuming, or

costly to model in simulation.

Note: While a prototype helps you to verify and validate your design in the real world,

simulation helps you catch design errors before spending money and time on prototyping.

SPICE is program that simulates electronic circuits on your PC.

WHY USE SPICE?

SPICE is a great tool for learning electronics. You can increase your understanding of

circuits as you play and tinker with them. Modify the circuit and see what happens. Change

a component value and see the effect on a circuit in seconds.

PSPICE by OrCAD is one of the most popular circuit simulators.

Orcad 9.2 Lite Edition Installation

1. Insert Cadence CD into CD-ROM drive

2. Select Products to install

Capture – Schematic entry application – it must be installed

3

Capture CIS – Should be grayed out.

PSpice – For conducting mixed-signal analog and digital simulations

Layout– For creating PC Board layouts from schematics

Then follow the instructions as it appears on the monitor and complete the installation

The steps to simulation:

1. Create a simulation project

2. Draw schematic to simulate

3. Establish a simulation profile

4. Set up simulation type

5. Simulate circuit

6. Analyze results in Probe

To start a simulation session

1. On the start menu select ORCAD FAMILY RELEASE 9.2 LITE EDITION - CAPTURE LITE

EDITION

2. Once the capture window appears, select FILE - NEW - PROJECT

The following window appears:

3. Give the project a descriptive name (spaces can be included).

4. Select ANALOG OR MIXED-SIGNAL CIRCUIT WIZARD.

5. Specify a location where the project is to be stored

a. Click Browse to change the location the files will be stored

6. Click OK.

4

The following window appears:

7. Select Create a blank project and click OK. The following window appears:

8. To place parts, click PLACE PART (Shift+P) The following window appears:

5

If Libraries are not appearing in the window then click Add Library. The

library files will generally be available in the following path by default C:\Program Files\Orcad_Demo\Capture\Library\Pspice.Select all Library files

by pressing Ctrl A and then press Open. All the Library files will appear in the window.

9. Select the part you wish to place in the schematic. Insert as many as

needed

10. Right Click and select END MODE to stop inserting parts

6

11. To wire parts together, click Place Wire Icon from the Right hand side

vertical Icons list (Shift+W). Place cursor over boxes at ends of parts and draw wires connecting parts.·When done, right click and select End Wire.

12. To insert a ground node, click Place – Ground Icon·Window appears with caption Place Ground with only ground nodes available for selection.

7

Altenative method:Click on place Net alias Icon N1 on the Right hand side

vertical Icons list.

Always select 0/SOURCE for the ground node of an analog circuit

– every analog circuit must contain atleast one 0 ground. This is not a requirement for digital circuits.

13. To change component values that are displayed·Double click the displayed value· Change the desired value in the dialog box that appears.

To set up a simulation profile

Select PSPICE ---NEW SIMULATION PROFILE from the menu

8

Give a descriptive name to the type of simulation .

Select the desired parameters for the particular circuit and then click OK

Place voltage, current, and power markers from the PSPICE --- MARKERS menu where needed

Click PSPICE -- RUN.

Simulation Experiments

General procedure for all experiments:

1. Select the required components from the menu.

2. Place all the required components in the schematic. 3. Simulate the circuit using RUN option from the menu.

4. Observe the waveforms form the output

1 a. To study the working of positive clipper, double –ended clipper and positive

clamper using diodes.

COMPONENTS REQUIRED: Diode (BY-127 / IN4007), Resistors-10 K & 3.3k , DC

regulated power supply (for Vref), Signal generator (for Vi) and CRO.

CIRCUIT DIAGRAM OF POSITIVE CLIPPER

9

Fig.1 a Positive clipper Circuit b. Transfer Characteristics

Clippers clip off a portion of the input signal without distorting the remaining part of the

waveform. In the positive clipper shown above the input waveform above Vref is clipped off.

If Vref = 0V, the entire positive half of the input waveform is clipped off.

Plot of input Vi (along X-axis) versus output Vo (along Y-axis) called transfer characteristics

of the circuit can also be used to study the working of the clippers.

Choose R value such that rf RRR where Rf = 100 and Rr = 100k are the resistances

of the forward and reverse diode respectively. Hence R = 3.3k .

Let the output resistance RL = 10k . The simulations can be done even without RL.

WAVEFORMS

Fig. 2. Input and output waveform for positive Clipper

DOUBLE ENDED CLIPPER

Fig.3 Double ended clipper Circuit b. Transfer Characteristics

10

Fig.4. Input and output waveform for double-ended clipping circuit

Note: The above clipper circuits are realized using the diodes in parallel with the load (at the

output), hence they are called shunt clippers. The positive (and negative) clippers can also

be realized in the series configuration wherein the diode is in series with the load. These

circuits are called series clippers.

POSITIVE CLAMPER

COMPONENTS REQUIRED: Diode (BY-127), Resistor of 200 K , Capacitor - 0.1 F, DC

regulated power supply, Signal generator, CRO

Fig. 5 Positive Clamper

The clamping network is one that will “clamp” a signal to a different DC level. The network

must have a capacitor, a diode and a resistive element, but it can also employ an

independent DC supply (Vref) to introduce an additional shift. The magnitude of R and C

must be chosen such that time constant ζ=RC is large enough to ensure the voltage across

capacitor does not discharge significantly during the interval of the diode is non-conducting.

Aim: To simulate clipper circuit

POSITIVE CLIPPER

Components to be placed in the schematic: ac voltage source, diode IN 4002,

Resistor 10k and 3.3k

11

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

POSITIVE CLIPPER WITH REFERENCE VOLTAGE


Resistor 10k, Resistor 3.3k,dc voltage source

R1

3.3kV

R2

10k

v 1

FREQ = 1khzVAMPL = 5vVOFF = 0

V

0

D1

D1N4002

Time

0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

V(V1:+) V(R2:2)

-5.0V

0V

5.0V

12


NEGETIVE CLIPPER


Resistor 10k, Resistor 3.3k

V

2V

R1

3.3k

v 1


0

V

D1

D1N4002

R2

10k

Time


V(V1:+) V(R2:2)

-5.0V

0V

5.0V

13


NEGETIVE CLIPPER WITH REFERENCE VOLTAGE


Resistor 10k,Resistor 3.3k, dc voltage source

R1

3.3kV

R2

10k

D1

D1N4002

0

Vv 1


Time


V(V1:+) V(R2:2)

-5.0V

0V

5.0V

14


DOUBLE ENDED CLIPPER

V

R2

10k

v 1


2V

R1

3.3k

D1

D1N4002

0

V

Time


V(V1:+) V(R2:2)

-5.0V

0V

5.0V

15

Type of analysis: TIME DOMAIN (TRANSIENT)

Run to time: 5msec step size:0.01msec

DOUBLE ENDED CLIPPER WITH REFERENCE VOLTAGE

V

D2

D1N4002R2

10k

R1

3.3k

D1D1N4002

v 1


0

V

Time


V(V1:+) V(R1:2)

-5.0V

0V

5.0V

V12V

R210k

0

V22V

V

R1

3.3k

V3

FREQ = 1khzVAMPL = 5vVOFF = 0 D2

D1N4002V

D1D1N4002

16

CLAMPER



Time


V(V1:+) V(R1:2)

-5.0V

0V

5.0V

V5


V

R2250k

0

V

C2

.1uf

D1D1N4002

17

CLAMPER WITH REFERENCE VOLTAGE



Time


V(V1:+) V(C1:2)

-5V

0V

5V

10V

V5


R2250k

V

C2

.1uf

0

V

D1D1N4002

V6

1v

Time


V(V1:+) V(C1:2)

-5V

0V

5V

10V

15V

18

2b. To build the CE amplifier circuit using a simulation package and determine the voltage

gain for two different values of supply voltage and for two different values of emitter

resistance. Components required:- transistor(QN3904),resistor,VAC,VDC,capacitor

The single stage common emitter amplifier circuit shown above uses what is commonly called

"Voltage Divider Biasing". This type of biasing arrangement uses two resistors as a potential

divider network and is commonly used in the design of bipolar

transistor amplifier circuits. This method of biasing the transistor

greatly reduces the effects of varying Beta, ( β ) by holding the Base

bias at a constant steady voltage level allowing for best stability. The

quiescent Base voltage (Vb) is determined by the potential divider

network formed by the two resistors, R1, R2 and the power supply

voltage Vcc as shown with the current flowing through both

resistors. Then the total resistance RT will be equal to R1 + R2

giving the current as I = Vcc/RT. The voltage level generated at the

junction of resistors R1 and R2 holds the Base voltage (Vb) constant

R5

1k

R2

2.2k

0V

0

R1

10k

C2

.47uf

0

V2

10v

V

C1

2.2uf

0

C4

10uf

R4

3.6k

0

R3

600V7

1mv

0Vdc

V

Q1

Q2N3904

0

R6

10k

19

at a value below the supply voltage. Then the potential divider network used in the common

emitter amplifier circuit divides the input signal in proportion to the resistance. This bias

reference voltage can be easily calculated using the simple voltage divider formula below:

The same supply voltage, (Vcc) also determines the maximum Collector current, Ic when the

transistor is switched fully "ON" (saturation), Vce = 0. The Base current Ib for the transistor is

found from the Collector current, Ic and the DC current gain Beta, β of the transistor.

The voltage gain of an electronic circuit as a function of frequency.

Av = Vout/Vin

Analysis Type: Ac Sweep

Start Frequency: 10hz

End Frequency:100meg

Points/Decade: 40

When the supply voltage is 1mv

Voltage gain Av= 80mv

Frequency

10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz

V(R6:2) V(C2:2)

0V

40mV

80mV

20

When the supply voltage is changed to 2mv


When the supply voltage is 1mv and the emitter resistor value is 1k


When the supply voltage is 1mv and the emitter resistor value is 2.2k


Frequency


V(R6:2) V(C2:2)

0V

50mV

100mV

150mV

Frequency


V(R6:2) V(C2:2)

0V

40mV

80mV

Frequency


V(R6:2) V(C2:2)

0V

20mV

40mV

21

3.b To implement a CMOS inverter using a simulation package and verify its

truthtable.


Run to time: 100usec step size:0.1usec

Time

0s 10us 20us 30us 40us 50us 60us 70us 80us 90us 100us

V(V1:+) V(R1:2)

0V

2.5V

5.0V

V(R1:2)

0V

2.5V

5.0V

V(V1:+)

0V

2.5V

5.0V

SEL>>

22

4b. To implement a Schmitt trigger using Op-Amp using a simulation package

for two sets of UTP and LTP values. COMPONENTS REQUIRED: IC μA 741, Resistor of 10KΩ, 90KΩ, DC regulated power

supply, Signal generator, CRO

Theory: Open loop gain of op amp is defined as:

AOL = Vo / VD

where VD = Vin – Vref

• Open loop gain of op amp is very high (ideally infinite).

• Any small difference between VNI and VINV results into saturation of output voltage

±VSAT

Value of VSAT is limited by the supply voltage of op amp

DESIGN:

From theory of Schmitt trigger circuit using op-amp, we have the trip points,

VR

RRLTPUTPV

KRKR

RRV

RR

VRLTPUTP

RR

VRLTPUTP

VRR

RR

VR

RR

VRLTP

VVRR

VR

RR

VRUTP

ref

sat

sat

ref

ref

satref

ccsatsatref

33.32

))(( have we(1)equation From

90 then ,10Let

9 yields (2)equation then 2V, LTP & 4V UTP10V,Let

-(2)----- 2

-(1)----- 2

used. isdesign following the values,&, thefind to values UTP& LTP given the Hence

&

of 90% opamp theof saturation positive theis where

1

21

12

21

21

1

21

1

21

21

2

21

1

21

2

21

1

UTP=-1 V LTP=-3v

Vref=-2.2v

23



UTP=4v LTP=2v

Vref=3.3v

Hysteresis Curve

U1

uA741

3

2

74

6

1

5+

-

V+

V-

OUT

OS1

OS2

V

0

V4

10v

V1

FREQ = 50hzVAMPL = 5vVOFF = 0

R2

90k

V2

3.3v

0

R1

10k

0

V

V3

10v

0

Time

0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms

V(V1:+) V(U1:OUT)

-10V

-5V

0V

5V

10V

24

To get the Hysterisis curve

1. Choose Axis settings from Plot menu

2. Under X-axis select axis variable

3. Select the input wave

4. Click Apply and ok

5. From the output check the UTP and LTP values

6. When Vin >UTP The o/p changes from +vsat(10v) to –vsat(-10v)

7. When vin< LTP the o/p changes from -vsat(10v) to +vsat(-10v)

UTP=-1 V LTP=-3v

Vref=-2.2v

Hysteresis Curve

V(V1:+)

-5.0V -4.0V -3.0V -2.0V -1.0V 0.0V 1.0V 2.0V 3.0V 4.0V 5.0V

V(V1:+) V(U1:OUT)

-10V

-5V

0V

5V

10V

Time

0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms

V(V1:+) V(U1:OUT)

-10V

-5V

0V

5V

10V

25

V(V1:+)

-5.0V -4.0V -3.0V -2.0V -1.0V 0.0V 1.0V 2.0V 3.0V 4.0V 5.0V

V(V1:+) V(U1:OUT)

-10V

-5V

0V

5V

10V

26

5.b. To implement a rectangular waveform generator (Op-Amp relaxation oscillator) using

a simulation package and observe the change in frequency when all resistor values are

doubled.

TYPE OF ANALYSIS : TIME DOMAIN

RUN TO TIME : 4ms

MAXIMUM STEP SIZE : 0.01ms

Time period =.3ms

Frequency=3.3 KHz

Resistor values Doubled

V1

12v

C1

.1uf

U1

uA741

3

2

74

6

1

5+

-

V+

V-

OUT

OS1

OS2

R3

10k

V

0

V2

12v

RELAXATION OSCILLATOR

0R1

1k

R2

10k

0

0

V

Time

2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

V(R3:1) V(R3:2)

-20V

-10V

0V

10V

20V

27

Time period =.5ms

Frequency= 2khz

Conclusion:As the resistor values are increased Time period increases and so the frequency

decreases

Time

2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

V(R3:1) V(R3:2)

-20V

-10V

0V

10V

20V

28

6. To design and implement an astable multivibrator using 555 Timer for a given frequency

and duty cycle.

COMPONENTS REQUIRED: 555 Timer IC, Resistors of 3.3KΩ, 6.8KΩ, Capacitors of 0.1

μF, Regulated power supply, CRO

Capacitance

This is a measure of a capacitor's ability to store charge. A large capacitance means that more

charge can be stored. Capacitance is measured in farads, symbol F.

Three prefixes (multipliers) are used, µ (micro), n (nano) and p (pico):

µ means 10-6

n means 10-9

p means 10-12

Capacitor Number Code for Electrolytic capacitors

A number code is often used on small capacitors where printing is difficult:

the 1st number is the 1st digit,

the 2nd number is the 2nd digit,

the 3rd number is the number of zeros to give the capacitance in pF.

Ignore any letters - they just indicate tolerance and voltage rating.

For example: 102 means 1000pF = 1nF (not 102pF!)

101 means 100pF=.1nF

Colour Coding For Resistors

Resistor values are always coded in ohms ( symbol Ω), capacitors in picofarads (pF)

A 100 kΩ, 5%

band A is first significant figure of component value

band B is the second significant figure

band C is the decimal multiplier

band D if present, indicates tolerance of value in percent (no color means 20%)

http://en.wikipedia.org/wiki/Ohm

http://en.wikipedia.org/wiki/Capacitor

http://en.wikipedia.org/wiki/Farad

http://en.wikipedia.org/wiki/File:Resistor_cropped.jpg

29

Color Significant

figures Multiplier Tolerance

Temp. Coefficient

(ppm/K)

Black 0 ×100 – 250 U

Brown 1 ×101 ±1% F 100 S

Red 2 ×102 ±2% G 50 R

Orange 3 ×103 – 15 P

Yellow 4 ×104 – 25 Q

Green 5 ×105 ±0.5% D 20 Z

Blue 6 ×106 ±0.25% C 10 Z

Violet 7 ×107 ±0.1% B 5 M

Gray 8 ×108 ±0.05% A 1 K

White 9 ×109 – –

Gold – ×10-1

±5% J –

Silver – ×10-2

±10% K –

None – – ±20% M –

DESIGN: Given frequency (f) = 1KHz and duty cycle = 60% (=0.6)

The time period T =1/f = 1ms = tH + tL

Where tH is the time the output is high and tL is the time the output is low.

For an astable multivibrator using 555 Timer we have

tL = 0.693 RB C ------(1)

tH = 0.693 (RA + RB)C ------(2)

T = tH + tL = 0.693 (RA +2 RB) C

Duty cycle = tH / T = 0.6. Hence tH = 0.6 T = 0.6ms and tL = T – tH = 0.4ms.

Let C=0.1μF and substituting in the above equations,

So RB= tL/0.693 x C =0.4 x 10-3

/0.693 x .1x10-6

=5.8kΩ

RA = tH - 0.693 x Cx RB / 0.693 x C

=0.6 x 10-3

x0.693 x5.8 x 103 0.1x x10

-6/0.693 x .1x10

-6=2.9kΩ

RB = 5.8KΩ (from equation 1) and RA = 2.9KΩ (from equation 2 & RB values).

The Vcc determines the upper and lower threshold voltages (observed from the capacitor voltage

waveform) as CCLTCCUT VVVV3

1&

3

2.

http://en.wikipedia.org/wiki/Black

http://en.wikipedia.org/wiki/Brown

http://en.wikipedia.org/wiki/Red

http://en.wikipedia.org/wiki/Orange_(colour)

http://en.wikipedia.org/wiki/Yellow

http://en.wikipedia.org/wiki/Green

http://en.wikipedia.org/wiki/Blue

http://en.wikipedia.org/wiki/Violet_(color)

http://en.wikipedia.org/wiki/Grey

http://en.wikipedia.org/wiki/White

http://en.wikipedia.org/wiki/Gold_(color)

http://en.wikipedia.org/wiki/Silver_(color)

30

Note: The duty cycle determined by RA & RB can vary only between 50 & 100%. If RA is much

smaller than RB, the duty cycle approaches 50%.

Circuit Diagram

Connect the pin 2 to the CRO to get the capacitor waveform check the amplitude from the

waveform to get the UTP and LTP values

Connect pin 3 to CRO to get the output. Find out the TH and TL values

PROCEDURE:

1. Before making the connections, check the components using multimeter.

2. Make the connections as shown in figure and switch on the power supply.

3. Observe the capacitor voltage waveform at 6th

pin of 555 timer on CRO.

4. Observe the output waveform at 3rd

pin of 555 timer on CRO (shown below).

5. Note down the amplitude levels, time period and hence calculate duty cycle.

Example 2: frequency = 1kHz and duty cycle =75%, RA = 7.2kΩ & RB =3.6kΩ,

Duty cycle = tH / T = 0.75. Hence tH = 0.75T = 0.75ms and tL = T – tH = 0.25ms.

Let C=0.1μF and substituting in the above equations,

So RB= tL/0.693 x C =0.25 x 10-3

/0.693 x .1x10-6

=3.6kΩ

RA = (tH - 0.693 x RB x C) /0.693 x C

=0.75 x 10-3

x 0.693 x 3.6 x 103 x 0.1x 10

-6 / 0.693 x .1x10

-6=7.2kΩ

Choose RA = 6.8kΩ and RB = 3.3kΩ.

RESULT:

The frequency of the oscillations = _1KHz.

WAVEFORMS

31

THEORY:

Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output

waveform is rectangular. The multivibrators are classified as: Astable or free running

multivibrator: It alternates automatically between two states (low and high for a rectangular

output) and remains in each state for a time dependent upon the circuit constants. It is just an

oscillator as it requires no external pulse for its operation. Monostable or one shot

multivibrator: It has one stable state and one quasi stable. The application of an input pulse

triggers the circuit time constants. After a period of time determined by the time constant, the

circuit returns to its initial stable state. The process is repeated upon the application of each

trigger pulse. Bistable Multivibrators: It has both stable states. It requires the application of an

external triggering pulse to change the output from one state to other. After the output has

changed its state, it remains in that state until the application of next trigger pulse. Flip flop is an

example.

Threshold voltage VUT VLT

theoretical (2/3 x Vcc)=3.3V (1/3 x Vcc)=1.6V

practical

Each division in oscilloscope is 0.2

Time=no of div in x-axis x time base

Amplitude= no of div in y-axis x volt/div

Duty cycle= (Ton/Ton +Toff) *100

Duty cycle Duty cycle Ton Toff

Theoretical 75% .6ms .4ms

Practical

32



33

Waveforms:Load Resistor RL=1k

RL=500

RL=100

Conclusion: when The resistor values are decreases Load current increases and the ripple

increases

Time

0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90ms 100ms

V(D2:2) V(R1:2)

-5V

0V

5V

10V

Time


V(D2:2) V(R1:2)

-5V

0V

5V

10V

Time


V(D2:2) V(R1:2)

-5V

0V

5V

10V

34

1.a. Given a four variable expression, simplify using Entered Variable Map (EVM) and

realize the simplified logic using 8:1 MUX.

E.g., Simplify the function using MEV technique

f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)

Components used: IC 74 LS151, patch chords, power chords, trainer kit.

Theory

The term multiplex means “many to one”. A multiplexer (MUX) has n inputs. Each line is

used to shift digital data serially. There is a single output line.

Pin diagram of IC 74LS151

Decimal LSB f MEV map entry

00

1

12

3

24

5

36

7

48

9

510

11

612

13

714

15

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

0

1

1

1

1

0

0

X

X

X

X

0

1

0

1

0------Do

1------D1

1-----D2

0-----D3

X-----D4

X-----D5

d----D6

d----D7

( Solution is given

below)

35

D—Map Entered Variable

000 001 010 011 100 101 110 111

0000

0

0010

1

0100

1

0110

0

1000

X

1010

X

1100

0

1110

0

0001

0

0011

1

0101

1

0111

0

1001

X

1011

X

1101

1

1111

1

D0=0 D1=1 D2=1 D3=0 D4=X D5=X D6=d D7=d

Circuit Diagram

0

1

O/p

`

D

Low

A B C

ABC

0

1

D

04 D0 Vcc 16

03 D1 GND 8

02 D2

01 D3

15 D4

14 D5 Y5

13 D6

12 D7

9 10 11

7 STROBE S2 S1 S0

36

Procedure:

1. Verify all components & patch chords whether they are in good condition or not.

2. Make connections as shown in the circuit diagram.

3. Give supply to the trainer kit.

4. Provide input data to circuit via switches.

5. Verify truth table sequence & observe outputs.

37

VHDL VHDL stands for Very High Speed Integrated Circuit Hardware Description

Language. It describes the behavior of an electronic circuit or system, from which the

physical circuit or system can then be implemented

VHDL was originally intended to serve 2 main purposes-

• It was used as a documentation language for describing the structure of complex

digital circuits.

• VHDL provides features for modeling the behavior of a digital circuit.

General Features of VHDL

• The language can be used as an exchange medium between chip vendors and CAD

tool user and can be used as communication medium between CAD and CAE tools.

• It supports hierarchy.

• It is not a case sensitive language.

• It is strongly type checked language.

• It provides design portability and flexible design methodologies: top down, bottom

up or mixed

• It supports both synchronous and asynchronous timing models.

• Nominal Propagation delays, min-max delays, setup and hold timing constraint and

spike detection can be described in this language.

Usage of the Tool

It is one of most popular software tool used to synthesize VHDL code. This tool Includes

many steps. To make user feel comfortable with the tool the steps are given below:-

Select NEW PROJECT in FILE MENU.

Enter following details as per your convenience

Project name : sample (should be same as the entity name in

your VHDL code

Project location : C:\example( As per convenience use default

Top level module : HDL

In NEW PROJECT dropdown Dialog box, Choose your appropriate device

specification. Example is given below:

Device family : cyclone

Device : EP1C6Q240

Package : PQFP

Pincount :240

Speed grade 8

On File Drop down menu choose new Vhdl file

Type the Vhdl code

Under the Processing Drop down menu choose Start compilation

If there are errors go back to the VHDL code and correct it. Once the

compilation is successfull

38

Under the processing drop down box select simulator tool select the

simulator mode to functional and click on generate functional simulation

netlist. we Get the success message.

Under simulator tool click on open. In the empty location right click . Click on

insert on NODE or BUS. Then click on NODE finder. In the window opened

select pins to unassigned. Click on List . IT will list all the Net list seloct all

and click ok.

The input and output appears give appropriate input.

On the simulator tool click on start simulation. Simulation success message

will be prompted

on simulator tool click on report to see the output.

Create a new project for every new VHDL code

The primary data type std_ulogic (standard unresolved logic) consists of nine character literals in

the following order:

'U' - uninitialized

'X' - strong drive, unknown logic value

'0' - strong drive, logic zero

'1' - strong drive, logic one

'Z' - high impedance

'W' - weak drive, unknown logic value

'L' - weak drive, logic zero

'H' - weak drive, logic one

'-' - don't care

39

1.b. Write the verilog /VHDL code for 8:1 MULTIPLEXER. Simulate


TruthTable

INPUTS OUTPUTS

SEL (2) SEL (1) SEL (0) Zout

0 0 0 I(0)

0 0 1 I(1)

0 1 0 I(2)

0 1 1 I(3)

1 0 0 I(4)

1 0 1 I(5)

0 1 1 I(6)

1 1 1 I(7)

VHDL code for 8 to 1 mux (Behavioral modeling).

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux1 is

Port ( I : in std_logic_vector(7 downto 0);

sel : in std_logic_vector(2 downto 0);

zout : out std_logic);

end mux1;

architecture Behavioral of mux1 is

begin

zout<= I(0) when sel="000" else

I(1) when sel="001" else






I(7);

end Behavioral;

MULTIPLEXER

8 TO 1

8

Zout I

SEL

3

40

41

2.a. Realize a full adder using 3-8 decoder IC and 4 input NAND. Components used: IC 74 LS138, IC 74LS20, patch chords, power chords, trainer kit.

Pin diagram of ICs used:

42

Theory:

The simplest Binary adder is a half adder. It has 2 inputs and 2 output bits. One is the sum

and the other is carry.

A half adder has no provision to add carry of lower order bits when binary numbers are

added. When two input bits and a carry are to be added, the number of input bits become 3

and input combination increases to 8. For this a full adder is used. Like half adder, it has 2

outputs. One is sum and the other is carry. New carry generated is denoted as Cn and carry

generated from addition of previous lower order bits is denoted as Cn-1

Function table

Circuit

Diagram

A B C S C

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

43

Procedure:

1.Verify all components & patch chords whether they are in good condition or not.





44

2.b. Write the verilog/ VHDL code for FULL ADDER. Simulate and verify its working.

Truth Table

INPUTS OUTPUTS

X Y Z SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Expression: Sum(S)=X Y Z

Carry(Cout) = XY +YZ + ZX

FULL

ADDER

S

Cout

X

Y

Z

45

VHDL code for Full adder using data flow

library IEEE;

use IEEE.STD_LOGIC_1164.ALL

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fa IS

Port (X, Y, Z : in STD_LOGIC;

Cout, S : out STD_LOGIC);

End fa;

ARCHITECTURE df OF fa IS

Begin

Cout<= (X AND Y) OR( Y AND Z) OR (X AND Z);

S<= (X XOR Y) XOR Z;

End df;

SUM CARRY

46

3.a.Realize a J-K Master/Slave FF using NAND gates and verify its

truth table.

Components used: IC 74 LS00, IC 74LS10, patch chords, trainer kit.


7400

7410

Clk J K Q ---

Q

comment

0

0

1

1

0

1

0

1

Q0

0

1

Q0

----

Q0

1

0

Q0

No change

Reset

Set

toggle

47

Theory:

The circuit below shows the solution. To the RS flip-flop we have added two new

connections from the Q and Q' outputs back to the original input gates. Remember that

a NAND gate may have any number of inputs, so this causes no trouble. To show that

we have done this, we change the designations of the logic inputs and of the flip-flop

itself. The inputs are now designated J (instead of S) and K (instead of R). The entire

circuit is known as a JK flip-flop.

In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q' outputs

will only change state on the falling edge of the CLK signal, and the J and K inputs will

control the future output state pretty much as before. However, there are some important differences.

Since one of the two logic inputs is always disabled according to the output state of the

overall flip-flop, the master latch cannot change state back and forth while the CLK input is at logic 1. Instead, the enabled input can change the state

of the master latch once, after which this latch will not change again. This was not true

of the RS flip-flop.

If both the J and K inputs are held at logic 1 and the CLK signal continues to change,

the Q and Q' outputs will simply change state with each falling edge of the CLK signal.

(The master latch circuit will change state with each rising edge of CLK.) We can use

this characteristic to advantage in a number of ways. A flip-flop built specifically to

operate this way is typically designated as a T (for Toggle) flip-flop. The lone T input is in fact the CLK input for other types of flip-flops.

The JK flip-flop must be edge triggered in this manner. Any level-triggered JK latch

circuit will oscillate rapidly if all three inputs are held at logic 1. This is not very useful.

For the same reason, the T flip-flop must also be edge triggered. For both types, this is

48

the only way to ensure that the flip-flop will change state only once on any given clock pulse.

Because the behavior of the JK flip-flop is completely predictable under all conditions,

this is the preferred type of flip-flop for most logic circuit designs. The RS flip-flop is

only used in applications where it can be guaranteed that both R and S cannot be logic 1 at the same time.

At the same time, there are some additional useful configurations of both latches and

flip-flops. In the next pages, we will look first at the major configurations and note their

properties. Then we will see how multiple flip-flops or latches can be combined to perform useful functions and operations.

Master Slave Flip Flop:

The control inputs to a clocked flip flop will be making a transition at approximately the

same times as triggering edge of the clock input occurs. This can lead to unpredictable

triggering.

A JK master flip flop is positive edge triggered, where as slave is negative edge triggered.

Therefore master first responds to J and K inputs and then slave. If J=0 and K=1, master

resets on arrival of positive clock edge. High output of the master drives the K input of the

slave. For the trailing edge of the clock pulse the slave is forced to reset. If both the inputs

are high, it changes the state or toggles on the arrival of thepositive clock edge and the

slave toggles on the negative clock edge. The slave does exactly what the master does.

Procedure:

1Verify all components & patch chords whether they are in good condition or not.





3.b. Write the verilog/ VHDL code for D Flip-Flop with positive- edge

triggering. Simulate and verify its working.

Truth table

clk D(input) Q(output) QBar

- 0 No change

49

- 1 No change

0 0 1

1 1 0

VHDL code for D Flip Flop Counter.

library IEEE;


entity dff is

Port ( D,Clk : in std_logic; Q : out std_logic;

Qbar : out std_logic:='1'); end dff;

architecture Behavioral of dff is

begin

process(clk) begin

if rising_edge(clk) then Q<= D;

Qbar<= not D; end if;

end process;

end Behavioral;

D-ff Simulation Results

50

4.a. Design and implement a mod n (a<8)synchronous up counter

using JK FF. Components used: IC 74 LS76, IC 74LS08, patch chords, trainer kit.

PIN DIAGRAM OF JK FLIP FLOP 74LS76 ICS ( TWO JK FLIP FLOP IN ONE ICS))

FOR INITIALIZATION EITHER FOR 1S OR FOR 0S

PR1,PR2-Preset Used To Store 1 By Making PR=LOW AND CLR=HIGH

CLR1,CLR2-Clear Used To Store 0 By Making CLR= LOW AND PR=HIGH

FOR NORMAL OPERATION THAT IS ,DEPENDS ON INPUT:-

PR1 ,PR2,CLR1,CLR2=HIGH

for initialization

for normal

51

PIN DIAGRAM OF 74LS08 ICS( 2 INPUT AND GATE( FOUR

AND IN ONE ICS))

FUNCTIONAL TRUTH TABLE FOR J-K FLIP FLOP

J K Qn Qn+1

0 0 0

1

0

1

0 1 0

1

0

0

1 0 0

1

1

1

1 1 0

1

1

0

STATE SYNTHESIS TABLE FOR JK FLIP FLOP

Present state Next state J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

52

Theory:

The ripple counter requires a finite amount of time for each flip flop to change state. This

problem can be solved by using a synchronous parallel counter where every flip flop is

triggered in synchronism with the clock, and all the output which are scheduled to change

do so simultaneously.

The counter progresses counting upwards in a natural binary sequence from count 000 to

count 100 advancing count with every negative clock transition and get back to 000 after

this cycle.

Synchronous counter design

To successfully design synchronous counters we may employ the following six basic steps:

1. Create the state transition diagram.

2. Create a present state-next state table (often referred to as the next state table).

3. Expand the table to form the transition table for each flip-flop in the circuit. The

transition table shows the flip-flop inputs required to make the counter go from

present state to the desired next state. This is also referred to as the excitation

table.

4. Determine the logic functions of the J and K inputs as a function of the present

states.

5. Analyse the counter to verify the design. 6. Construct and test the counter.

Let us employ these techniques to design a MOD-8 counter to count in the following sequence: 0, 1, 2, 3, 4, 5, 6, 7.

Step1: Creating state transition diagram.

53

Step 2: Creating present state-next state table

Present State Next State

Qc Qb Qa Qc Qb Qa

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

Step 3: Expand the present state-next state table to form the transition table.

Present

State

Next State Present inputs

Qc QB QA QC QB QA JC Kc JB KB JA KA

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 x X 1

1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 0 0 0 X 1 X 1 X 1

„X‟ indicates a "don‟t care" condition.

54

Step 4: Use Karnaugh maps to identify the present state logic functions for each of the inputs.

BA

00 01 11 10

1

X X X X

Jc=QaQb

BA

00 01 11 10

X X X X

1

Kc=QaQb

BA

00 01 11 10

0 1 X X

0 1 X X

JB=Qa

AB

00 01 11 10

X X 1 0

X X 1 0

Kb=Qa

AB

00 01 11 10

1 X X 1

1 X X 1

Ja=1

C

c 0

1

C

0

1

C

0

1

C

0

1

C

0

1

55

BA

00 01 11 10

X 1 1 X

X 1 1 X

Ka=1

Step 5: Trace through indicates circuit should work correctly.

Step 6: Constructing Circuit

A three-bit synchronous counter

*NOTE:-CONNECT PRESET AND CLEAR TO HIGH TO WORK ON NORMAL OPERATION

4.b. Write the verilog/ VHDL code for mod-8 up counter. Simulate


Truth table

rst clock Q2 Q1 Q0

1 x 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

C

0

1

56

0 1 0 1

0 1 1 0

0 1 1 1

0 0 0 0

VHDL code for Mod-8 Counter.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;


entity mod8 is

Port ( rst,clk: in std_logic; q : buffer std_logic_vector(2 downto 0):="000");

end mod8;

architecture Behavioral of mod8 is

begin

process(clk,rst) is begin

IF (CLK'event and clk='0') then If(rst='1') then

q<="000"; Else

q <= q+1; End if;

End if; End process;

End Behavioral;

57

Mod 8 Counter Simulation Results

Output

58

5.a. Design and Implement a Ring Counter using 4 bit Shift Register.

Components used: IC 74 LS95, patch chords, trainer kit.


Pin Diagram of IC: 7495

Mode Control Input : If Mc= 1 Parallel input Mc=0 Serial input

Theory:

Ring Counter is a basic register with direct feedback such that contents of the register

simply circulate around the register when the clock is running. Here last output Qd in a shift

register is connected back to the serial input.

Function Table:

Clk Qa Qb Qc Qd

0

1

2

3

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1

59

Circuit Diagram: CLK(Mono pulse)

Qd

Vcc Qa Qb Qc

A B C D MC gnd

1. Make Mc=1 Give parallel input 1000 through ABCD

2. Then make Mc=0 for shift operation

Procedure: 1 Verify all components & patch chords whether they are in good condition or not.

2 Make connections as shown in the circuit diagram.

3 Give supply to the trainer kit.

2 Provide input data to circuit via switches .


14 13 12 11 10 9 8

IC 7495

1 2 3 4 5 6 7

60

5.b. Write the verilog/ VHDL code for switched tail counter. Simulate and

verify its working.

Truth table

clk Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

1 0 0 1 1

1 0 1 1 1

1 1 1 1 1

1 1 1 1 0

1 1 1 0 0

1 1 0 0 0

1 0 0 0 0

1 0 0 0 1

1 0 0 1 1

1 0 1 1 1

1 1 1 1 1

61

VHDL code for Johnson counter.

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;


entity jc is

Port ( clk : in std_logic;

Q : buffer std_logic_vector(3 downto 0));

end jc;

architecture Behavioral of jc is

begin

process(clk)

begin

IF (CLK'event and clk='1') then

Q(3 downto 1)<=Q(2 downto 0);

Q(0)<=not Q(3);

end if;

end process;

end behavioral;

Johnson Counter Simulation Results

62

OUTPUT

63

6) Design and implement asynchronous counter using decade counter IC to count

up from 0 to n (n≤9).

Components used: IC 74 LS90, patch chords, trainer kit.

Pin Diagram of 7490

Theory:

Asynchronous counter is a counter in which the clock signal is connected to the clock input

of only first stage flip flop. The clock input of the second stage flip flop is triggered by the

output of the first stage flip flop and so on. This introduces an inherent propagation delay

time through a flip flop. A transition of input clock pulse and a transition of the output of a

flip flop can never occur exactly at the same time. Therefore, the two flip flops are never

simultaneously triggered, which results in asynchronous counter operation.

1.Cp0(pin 14) to be connected to clock

2.Cp1(pin1) to be connected to Q0.( The output of the first flip flop drives the second clock)

64

For decade counter(mod 10)

MR1 AND MR2-CLEAR ALL FILPFLOP (HIGH ACTIVE AND LOW FOR NOT

ACTIVE)

MS1 AND MS2- SET ALL FLIP FLOP (HIGH ACTIVE AND LOW FOR NOT

ACTIVE)

CPO-CLOCK PULSE TO FIRST FLIP FLOP

CP1-CLOCK PULSE TO SECOND FLIP FLOP (OUTPUT OF FIRST FLIP FLOP

CLOCK FOR SECOND FILP FLOP)

For mod 9

connect Q0 and Q3 to reset(clear) through an AND gate.

Note :reset should not be connected to the switch

For mod8

Connect Q3 to reset

For mod7

Connect Q2, Q1,Q0 to reset through an And Gate

For Mod 6

Connect Q2 and Q1 to reset through an AND gate

65

For mod 5


For Mod 4

Connect Q2 to reset through an AND gate

For mod 3


For mod 2

Connect Q1 to reset

Function Table:

Clock Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

8 0 1 1 1

9 1 0 0 0

10 1 0 0 1

Procedure:

1 Verify all components & patch chords whether they are in good condition or not.





66

7.Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy

and resolution.

AIM:

EQUIPMENTS AND COMPONENTS REQUIRED:

Op-amp 741, Resistors , dual power supply, VRPS ,CRO, Bread board.

PROCEDURE:

1. The circuit is connected as per the diagram

2. Give digital inputs from 0000 (2) to 1111(2) in steps using switch arrangement and note down

the corresponding analog voltage.

3. For each case verify the theoretical value with practical value.

4. To find linearity plot the practical analog output values Vs digital inputs on a graph sheet. A

straight line connecting input and output values is drawn.

DESIGN:

Analog output voltage Vo for 4-bit DAC is given by

Vo = (8 D3 + 4 D2+2 D1+1 D0)*V

Where V = Vref. (2R) /24 . (3R)

= Vref/ 24 =5/24=0.20833 Example:

For Digital input D1D,D,D0 1 011

Vo=(8+0+2± 1 ) 0.20833

Vo= 2.291 volts.

•Resolution: This is the number of possible output levels the DAC is designed to reproduce.

This is usually stated as the number of bits it uses, which is the base two logarithm of the number

of levels. Resolution is related to the effective number of bits (ENOB) which is a measurement

of the actual resolution attained by the DAC.

67

Example:-

1 bit DAC is designed to reproduce 2 (21) levels while an 8 bit DAC is designed for 256 (2

8)

levels.

(a)Resolution for 4bit DAC is designed to reproduce 16(24) levels

(b)Accuracy formula= 100-(Theoretical value- Practical value)

Example:-

100-(3.12-3.00)=100-.12=99.88%

Decimal

Equivalent

Digital Input Analog Output voltage

D3 D2 D1 D0 Theoretical Practical

0 1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

68

06CSL38ManualLD

Documents

ua741 v v

ms frequency

ms vr3

ms vu1

ms time period

utp ltp utp ltp

ltp utp values

ltp values