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Digital Two-Loop Controller Design for Fourth

Order Split-Inductor ConverterMummadi Veerachary

Dept. of Electrical Engineering, IIT Delhi, New Delhi, India

E-mail: [email protected]

Abstract- In this paper a digital two-loop controller designmethodology is proposed for the fourth order split inductorconverter load voltage regulation. The salient features of thesplit-inductor converter are compared with the conventional

SEPIC converter and then discrete-time mathematical modelsare established. Digital two-loop controller, inner current-loopand outer voltage-loop, is designed using direct digital designapproach. A two-pole two-zero compensator is adopted in theouter voltage-loop, while one-pole and one zero is used in theinner current-loop design. Compensator design is validatedthrough simulations and then experimental measurements. Load

voltage regulation characteristics are obtained against line andload perturbations. A 25 watt 15 to 36 V prototype converter is

built and experimental investigations are carried out. Themeasured results obtained from the prototype converter are inclose agreement with those obtained in the analysis.

I. I NTRODUCTION

Application of high frequency switch-mode power

conversion is increasing in the low power compact electronic

circuits. As the power conversion system is becoming

miniaturized, increasing the power density is one of the

challenging issues for the power supply designers. One of the

main orientations in power electronics in the last decade has

been the development of switching-mode converters with

higher power density and low electromagnetic interference

(EMI). Light weight, small size and high power density are

also some of the key design parameters [1]-[3].

Switch-mode power supplies (SMPS) are becoming an

integral part of many electronic systems [1] and the dc-dc

converters are mainly used in these application areas.

Technological developments are is taking place in order to:

(i) improve converter performance, (ii) achieve better

reliability, and (iii) increasing the power density, etc. The

aspect of increasing the power density is mainly related to the

converter design and packaging. Performance improvementof the dc-dc converter topologies is broadly classified into

two different categories, which are: (i) steady-state

performance, and (ii) dynamic performance. Among these

two, the converter system dynamic performance mainly

governed by the type of controller used. Conventional SEPIC

converter based topologies are well established for

applications requiring both bucking and boosting the up-

stream voltages. However, in the applications where the

voltage gain requirement is higher, not possible to realize

with single conventional converter, then there are two

alternate solutions, which are: (i) cascading the boost

converters, (ii) cascading the SEPIC converters. Although

these methods are capable of resulting higher transformation

ratios, but more number of components are required for their

realization and also results in lesser efficiency. Some times to

realize the predefined transformation ratio the converter

needs to be operated at the extreme duty ratios wherein the

device utilization is poor with increased thermal loading. In

order to alleviate some of these limitations coupled inductor

boost converters and quadratic topologies have been proposed

in the literature [1]-[4]. However, more device stress is themajor limitation of these topologies. By using the split-

inductor [2] concept it is possible to increase the voltage gain

of the conventional SEPIC converter, without increasing the

device stress, and one such fourth order split-inductor

converter (FSC) is discussed in this paper.

The dynamic performance of the converter is primarily

decided by the control strategy employed for a particular

topology. The two most commonly used control schemes in

dc-dc switching power converters are: (i) single loop voltage-

mode control, (ii) current-mode control. It is well known that

the single loop voltage-mode control is slow in its response

against supply disturbances [7]. On the other hand the two-

loop control strategy, inner current mode control together

with outer voltage loop, results in faster dynamic response.

However, selection of a particular control scheme is

essentially decided by the complexity and cost trade-offs

requirements imposed by the end-user. In any case selection

of the control strategy is also depends on the speed of

response and robustness requirement. Considering speed of

response as the requirement a two-loop digital controlling

scheme is designed in this paper for the FSC and detailed

design methodology is given in the following paragraphs.

2 2, L r

3

3

,

L

r

1 1,c

C r

0

0

,

c

C

r1 1, L r

Fig. 1. Fourth-Order Split Inductor Converter circuit diagram.

IEEE PEDS 2011, Singapore, 5 - 8 December 2011

978-1-4577-0001-9/11/$26.00 ©2011 IEEE 1137

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Fig. 2. Control block diagram of voltage-mode controlled FSC.

TABLE I. PERFORMANCE COMPARISON

SEPIC FSC

Voltage gain Low High

Efficiency Moderate Moderate

Transient response Moderate Low

Switching stresses

on elements

High Low

II.

MODELING A ND A NALYSIS OF THE FOURTH ORDER

SPLIT-I NDUCTOR CONVERTER

The fourth order split-inductor converter is shown in Fig. 1.

This converter is derived from the conventional SEPIC

converter where-in the source side inductance is divided into

two halves and then arranged in a bridge form as shown in

Fig. 1. In comparison to the conventional SEPIC converter, as

it is indicated within the box, it consists of three additional

diodes (D1, D2 and D3) and inductors (L1, L2). Due to this

structural arrangement the circuit exhibits more important

features as compared to the conventional SEPIC converter,

which are: (i) the FSC is capable of giving higher load

voltage boosting at lower duty ratios, (ii) switchvoltage/current stress is almost same as conventional

converter, and (iii) inductance requirement is almost same as

the conventional converter. Steady-state performance

comparison of this converter with SEPIC converter is given

in Table I for ready reference.

This FSC can operate either in continuous or discontinuous

inductor current mode of operation. However, for a given

power rating and boosting factor requirement the source

current magnitude is high for most of the loading conditions

and correspondingly the current is continuous in all the three

inductors. In view of this, the FSC analysis as well as itsdiscrete-time model formulation is discussed here for the

continuous inductor current mode of operation. As stated

earlier the high voltage gain of this converter is mainly due to

the presence of the split inductors (L1, L2), while there is no

change in the load side ripple current as there is no structural

change in the circuit configuration. The split inductor

combination will draw the energy from the dc-voltage source

during switch-ON time period and then pumps into the load

for the remaining time period. In this process the split

inductors will be connected in series during the switch-OFF

period contributing to additional boosting as compared to

conventional SEPIC converter. The split inductor

combination resulting in an additional boosting at the expense

of increased source current ripple.

A. Converter parameter Design Equations

The steady-state analysis of the FSC is carried out in this

section and the analysis is developed here after including thefollowing simplifying assumptions: (i) switching devices are

ideal, i.e voltage drops in the switching devices are neglected

and the transition time is very small, (ii) ripple current/

voltage magnitude is very small, (iii) converter time constant

is very high as compared to the switching period, and (iv)

non-idealities of the energy storage elements are neglected.

By employing the “KVL and KCL” the steady-state

relationships among the various voltage and currents are

established. Assuming voltage drops across inductors L1, L2

are same, various voltages across inductor elements L1, L2

and L3 during switch-ON/OFF periods respectively are:

Inductor ON-time OFF-Time

L1 Vg (Vg- Vc- Vo)/2

L2 Vg (Vg- Vc- Vo)/2

L3 Vc -Vo

Applying volt-sec balance to the inductor L1 and L3 the

following voltage gain [7] of the converter is obtained.

( )

( )0

1

1 - g

D DV

V D

+=

(1)

Using the power balance, VgIg=V0I0, and time-domain

analysis the FSC design equations are established. The

minimum and maximum inductor current expressions can

easily be obtained by using the ripple quantities,

L1 g 1i V DT L ;∆ = L2 g 2i V DT L∆ = and the capacitor

voltage ripple relationships are:

C1 L2 1V I DT C ,∆ = 2

C0 g 2 0V V (DT) (8L C ).∆ = These

expressions together with current/ voltage ripple requirements

give the basis for the design of energy storage components

L1, L2, L3 and C1, C2.

B. State-space Models For Continuous Inductor Current

Mode of Operation

Application of state-space modeling is widely used in the

switch-mode power conversion systems. Conventionally, thediscrete-time models are obtained through suitable

transformation applied to the state-space models. However,

accuracy of such discrete-time models mainly governed by

the type of transformation used and the switching frequency

employed. In ref[4] discrete-time modeling of digitally

controlled converters has been reported, where-in it has been

demonstrated that it is possible to include type of pulse width

modulation strategy as well as the sampling instant

information in the model itself. This methodology is used to

formulate the discrete-time model for the proposed FSC

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operating at trailing-edge OFF-time sampling [7]. In

continuous inductor current mode of operation the circuit has

two operating modes; Mode-1: S-ON (0<t<DT s); Mode-2: S-

OFF ( DT s<t<T s). In each mode of operation the circuit is

linear, and its behavior can easily be described by the state-

space model [13] given by

[ ] [ ] [ ]

[ ] [ ] ( 1)

j j

j j j

x A x B u

t t t y E x +

⎡ ⎤ ⎡ ⎤= +⎣ ⎦ ⎣ ⎦< <

⎡ ⎤= ⎣ ⎦

(2)

where [A j]- state matrix, [B j]- input matrix, [E j]- output

matrix, and [x]- state vector, [y]- output vector, [u]- forcing

function vector.

1 1

1 3 3

1

2

1 2

/ 0 0 0

0 / 1/ 0;

0 1/ 0 0

0 0 0 1/ ( ( ))

c

c

r L

r L L A

C

C R r

−⎡ ⎤⎢ ⎥

− −⎢ ⎥=⎢ ⎥⎢ ⎥

− +⎣ ⎦

2

3 3 3 3 3

2

1

2 2 2 2

[ ] / / 1/ / ( * )

/ [ ] / 0 / ( * );

1/ 0 0 0 0

/ ( ) / ( ) 0 1/ ( ( ))

e c

c c

c

a r L a L L a r L

a L a r L a r L A

C

R C R R C R C R r

− + −⎡ ⎤

⎢ ⎥− +⎢ ⎥=⎢ ⎥⎢ ⎥

− − +⎣ ⎦

[ ]2 11/ 0 0 0 ;T

B L= [ ]2 1/ 0 0 0T

B L=

C31 2

C3 C3

Rr R E =E = 0 0 0

(R+r ) (R+r )

⎡ ⎤⎢ ⎥⎣ ⎦

The above matrices gives an idea of the system that they are

linear in each mode of operation, and the circuit behavior caneasily be obtained by the discrete-time state- model [4] given by eqns. (3) and (4).

^ ^ ^[ ] [ 1] [ 1] x n x n d nφ γ = − + − ; (3)

0 k v = E x ; (4)

s d d1 2 1DT -t ) TA ( A AD Ts=e e e ;φ ′ s d2 1 DT -t )A A (D Ts

s=KT e eγ ′

where [ ]T

L1 L3 c1 c0x = i i v v ,⎡ ⎤⎣ ⎦ gu=[V ]. Detailed discrete-

time formulations are reported in ref[4] are used and they arelisted here, eqns. (5)-(9), for ready reference.

-1

vgG ( ) E (zΙ- ) γ+F z φ = ′ ′

(5)

-1

vdG ( ) E (zΙ- ) γ z φ = ′ (6)-1

( ) P [(ZI- ) γ]in Z z φ = ′ (7)

-1( ) [E (zI- ) γ+J ]o Z z φ = ′ ′ (8)

3 23 2 1 o

vd 4 3 24 3 2 1 o

p z +p z +p z+aG (z)=

[q z +q z +q +q z+q ] z

⎡ ⎤⎣ ⎦ (9a)

Substituting the converter parameters, given in Section IV,results in the following control-to-output transfer function.

3 2

vd 4 3 2

12.68z -31.85z +28.66z-8.982G (z)=

[z -3.519z +4.833 -3.072z+0.76] z

⎡ ⎤⎣ ⎦ (9b)

3 2

id 4 3 2

6.632z -16.83z +15.64z-5.383G (z)=

[z -3.519z +4.833 -3.072z+0.76] z

⎡ ⎤⎣ ⎦ (9c)

TABLE II. FOURTH ORDER SPLIT-I NDUCTOR CONVERTER PARAMETERS

Parameter Value

Vg 15 V ± 20%

Vo 36 V

R 26 Ω ± 50%

L1, r 1 100 μH, 0.08 Ω

L2, r 2 100 μH, 0.05 Ω

L3, r 3 200 µH, 0.07 Ω

C1, r c1 50 µF, 0.14 Ω

C0, r c0 100 µF, 0.22 Ω

f s 50 kHz

III.

DIGITAL CONTROLLER DESIGN GUIDELINES

Once the power stage transfer functions are known, thenthe digital controller can easily be designed to obtain the

desired closed-loop dynamical performance. Several

compensator design approaches [5]-[10] have been reported

in the literature for the analogue controllers. However, there

are two different approaches can be used while designing the

digital compensator, which are: (i) digital redesign approach,

(ii) digital direct design approach (DDDA). The detailed

discussion about these methods have been given in Ref[7].

The second method, DDDA, is used in this paper for digital

controller design. Pole-zero placement technique is used

while arriving at suitable digital compensator, and it’s brief

description for one such compensator, two-zero two-polestructure, is given in the following steps: (i) to reduce

regulation error of the load voltage, the loop gain crossover

frequency, f c, should be as high as possible, (ii) set the loop

gain crossover frequency, ‘f c’ be in the range of 1/20 ~ 1/50

of the switching frequency ‘f s’, (iii) select ‘f 3’ as multiples of

‘f c’ like (3 2 c f f = ), (iv) select the frequencies ‘f 2’ and

‘f 3’ such that they are in geometric mean with respect to ‘f c’

i.e.,1 3c f f = , (v) place the two compensator zeroes

below the crossover frequency (f 1 < f 2 < fc), f 1=f 2/10, f 2=f c/f 3,

(vi) place the two compensator poles above the cross over

frequency (f c < f 3 < f 4), f 4=10f 3. These design steps have been

taken into consideration while designing the digital

compensator. However, fine tuning of these locations is

needed depending on the nature of converter transfer

functions. The closed-loop block diagram is shown in Fig. 2.

Use of this approach allows the designer to incorporate the

inherent digital delays present in the actual system. By using

above steps the compensator design can be carried out with

the help of any software program. However, MATLAB [11]

platform is the good choice for compensator design as it is

having all the control related functions. Check all the closed-

loop converter performance specifications, and if the design

is not fulfilling the requirements repeat the process by

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changing the crossover frequency, location of pole-zero’s and

controller gain. By embedding the closed-loop converter into

any of the power electronic simulators it is easy to verify the

time domain responses through simulations. The overall loop

gain of the closed loop system, including inner current-loop

and outer voltage loop, is in the form given in eqn. 10.

( ) i vT z T T = + (10)

( ) ( ) ( ) ( ) ,( ) ( ) ( ) ( ) ,

i c i d p

v c v d p

T z G z G z G z T z G z G z G z

=

=

(11)

1 2

3

1

( )( )( )

( 1)( )

( )( )

( 1)

vcv

ici

k z a z aG z

z z a

k z bG z

z

− −=

− −

−=

−

(12)

Among all the above equations the control-to-output

transfer function, Gvd(z), and control-to-inductor current,

Gid(z), given by eqn. 9, is required while designing the outer

voltage-loop and inner current-loop controllers. After

substituting the required matrices in the mathematical

identities the resulting transfer function is given by (9). Once

having these transfer functions the individual loop design caneasily be carried out and the corresponding steps explained

above the compensator is designed with the help of

MATLAB [8] platform, wherein almost all linear system

theory related functions are readily available. Check all the

closed-loop converter performance specifications, gain

margin (GM) at least 6 dB and phase margin (PM) in between

300 ~ 750, and if the design is not fulfilling the requirements

repeat the process by changing the crossover frequency,

locations of poles/zeros.

IV.

DISCUSSIONS O N THE SIMULATION A ND

EXPERIMENTAL R ESULTS

In order to demonstrate the proposed converter salient

features and its controlling capability a 25 W, 15 –to- 36 VFSC is considered here and its parameters are listed in TableII. State-space models, derived in Section II, have been usedand then important small-signal frequency responsecharacteristics have been obtained, using MATLAB. Forillustration, the overall loop design frequency response bode plot is shown in Fig. 3. In order to stabilize the two-loop

system, the overall loopgain should follow the ‘Tv’ in the lowfrequency region and ‘Ti’ in the high frequency region. Toachieve this, a two pole two zero compensators in outer loopand one pole-zero in the inner loop is now included and thecorresponding loopgain frequency response plot is alsoshown in Fig. 3. The digital controllers, Gcv(z) and Gci(z),

parameters are: k v=0.9123, a1=0.941, a2=0.704, a3=0.849,k i=0.5623, b1=0.941. This overall loopgain plot is exhibitinga GM= 6.11 dB, PM=610 which are within the acceptable

stability limits.

To test the designed controller performance severalsimulations, using PSIM simulator [12], have been performedand then found that load regulation together with fasterdynamic response achieved in each case. Detailed simulation

results will be given in the final paper. The steady-statevoltage gain of the FSC has been verified by varying the dutyratio, and found that the gain is increasing with increasedduty ratios. In order to validate the mathematical analysis andsimulation results a 25 Watts laboratory prototype FSC is built and tested for its steady-state and dynamic performance.

To validate the developed theoretical analysis and

simulation results, a laboratory prototype closed-loopconverter has been built and then tested for its load voltageregulation feature against source and load perturbations. Thedigital control algorithm has been implemented using aAMDC401digital signal processor (DSP) [10]. The devices

used in the prototype converter circuits are: Switch IRF540,Diode MUR860, Driver circuit IR2110, Opto-coupler 6N137.The load voltage is sensed and is brought down into the range(0~1 V), which is passed on to the onboard ADC of the DSP.

The digital controller, given by eqn. 12, has been transformedinto a discrete-time control law given by:

( ) 1.849 ( 1) 0.849 ( 2) 0.9123 ( )

1.5 ( 1) 0.6044 ( 2)

v v v v

v v

d n d n d n e n

e n e n

= − − − +

− − + −

( ) ( 1) 0.5623 ( ) 0.5297 ( 1)i i i id n d n e n e n= − + − −

where d(n), d(n-1) and d(n-2) are the new, one-cycle-before

and two-cycles-before duty ratios, respectively; while e(n),

e(n-1) and e(n-2) are the new, one-cycle-before and two-

cycles-before error signals, respectively.

For demonstration of the principle sample experimentallymeasured load voltage dynamic response characteristics forthe following cases: (i) load disturbance from 52 → 26 Ω

(50% variation), (ii) supply voltage change from 15 → 19 V(20% variation). These measured results, Fig. 5, clearly

indicate that the designed digital controllers are regulating theload voltage to the reference value of 36 V and exhibitingfaster dynamics response against source and loaddisturbances.

-50

0

50

100

M a g n i t u d e ( d B )

100

101

102

103

104

105

-270

-180

-90

0

90

P h a s e ( d e g )

Bode Diagram

Frequency (Hz)

Ti

Tv

T1

Fig. 3. Frequency response bode plot of Ti, Tv, overall loopgain T transferfunctions.

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(a) Load perturbation (R: 52 → 26 )

(b) Source perturbation (Vg: 15 → 19 V)

Fig. 4. Simulated dynamic response of the load voltage.

(a) Load resistance perturbation (R: 52 → 26 )

(b) Source voltage perturbation (Vg: 15 → 19 V)

Fig. 5. Measured dynamic response of the load voltage.

V.

CONCLUSION

Digital two-loop controller was designed for fourth order

split inductor converter. The comparative study shown that

the proposed converter has resulted in better performance

over the conventional SEPIC converter. Digital two-loop

controller, with inner current-loop and outer voltage-loop has

resulted better dynamic response against the source and load

perturbations. Simulation and experimental were in close

agreement with each other and thus validating the controller

design.

R EFERENCES [1] Veerachary. M, ``Two-loop voltage-mode control of coupled inductor

step-down buck converter,'' IEE Proc. On Electric Power Applications,

Vol. 152(6), pp. 1516 - 1524, 2005.[2] Jian Liu, Zhiming Chen, Zhong Du, “A new design of power supplies

for pocket computer system”, IEEE Trans. on Ind. Electronics, 1998,

Vol. 45(2), pp. 228-234.[3] Barrado. A, Lazaro. A and etc, "Linear-non-linear control for DCDC

Buck converters: stability and transient response analysis", IEEE

Applied Power Electronics Conf. (APEC), 2004, pp.1329 - 1335.[4] B. Krishna Mohan, “Robust Digital Voltage-mode Controller for fifth

order Boost Converter,” IEEE Trans. Ind. Electron., Jan. 2011, vol.58,

no.1, pp. 263-277.

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[5] M. Veerachary, "Design of Robust Digital PID Controller for H-Bridge

Soft-Switching Boost Converter," IEEE Trans. Ind. Electron., July2011, vol. 58, no.7, pp. 2883-2897.

[6] Sungsik Park, Sewan Choi, “Soft Switched CCM Boost Converters

With High Voltage Gain For High-Power Applications”, IEEE Trans.On Power Electronics, 2010, Vol. 25(5), pp. 1211-1217.

[7] R. Sekhar, “Digital Voltage-mode Controller Design for High gain

Soft-Switching Boost Converter,” IEEE Proc. on PEDES2010, Dec.2010, pp. 1-5.

[8] Jianping Xu and C.Q.Lee, “Unified Averaging Technique for the

Modeling of Quasi-Resonant Converters”, IEEE Transactions on PowerElectronics, Vol. 13(3), 1998, pp. 556-563.

[10] A. C. Bartlett, C. V. Hollot, and H. Lin, “Root locations for a polytopeof polynomials: Check the edges,” Math. Contro., Signals Syst., 1988,

no. 1, pp. 61-71.

[11] H. Chapellat, and S. P. Bhattacharyya, "A Generalization ofKharitonov's theorem: Robust Stability of Interval Plants," IEEE Trans.

on Automat. Contr., Mar. 1989, vol. AC34, no.3, pp. 306-311.

[12] A. Katbab and E. I. Jury, "Robust Schur-stability of Discrete-TimeInterval Plants," IEEE Proc. on American Control Conference, 1990,

vol. 51, no. 6, pp. 1343-1352.

[13] MATLAB, user manual, 2005.[14] PSIM, user manual, 2005.

[15] dSPIC30F2020, Microchip, user manual, 2009.

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