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William Stallings
Computer Organization
and Architecture
8th Edition
Chapter 5
Internal Memory
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Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility
Random-access
memory (RAM)Read-write memory Electrically, byte-level Electrically Volatile
Read-only
memory (ROM) Read-only memory Not possible
Masks
Nonvolatile
Programmable
ROM (PROM)
Electrically
Erasable PROM
(EPROM)
Read-mostly memory
UV light, chip-level
Electrically Erasable
PROM (EEPROM)Electrically, byte-level
Flash memory Electrically, block-level
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Semiconductor Memory
RAM
Misnamed as all semiconductor memory israndom access
Read/Write
VolatileTemporary storage
Static or dynamic
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Memory Cell Operation
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Dynamic RAM
Bits stored as charge in capacitors
Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue
Level of charge determines value
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Dynamic RAM Structure
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DRAM Operation
Address line active when bit read or written
Transistor switch closed (current flows)
Write
Voltage to bit line
High for 1 low for 0
Then signal address line Transfers charge to capacitor
Read
Address line selected
transistor turns on
Charge from capacitor fed via bit line to sense amplifier
Compares with reference value to determine 0 or 1
Capacitor charge must be restored
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Static RAM
Bits stored as on/off switches
No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital
Uses flip-flops
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Stating RAM Structure
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Static RAM Operation
Transistor arrangement gives stable logic
state State 1
C1high, C2low
T1T4off, T2T3 on
State 0C2high, C1low
T2T3off, T1T4 on
Address line transistors T5T6is switch Write apply value to B & compliment to
B
Read value is on line B
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SRAM v DRAM
Both volatile
Power needed to preserve data
Dynamic cell
Simpler to build, smaller
More denseLess expensive
Needs refresh
Larger memory units
Static
Faster
Cache
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Read Only Memory (ROM)
Permanent storage
Nonvolatile
Microprogramming (see later)
Library subroutines
Systems programs (BIOS)
Function tables
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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10thed
Summary
Read-Only Memory (ROM)
A ROM symbol is shown with typical inputs and outputs.
The triangles on the outputs indicate it is a tri-stated device.
ROM 256 4
0
&EN
7
A0
255
D
D
D
D
To read a value from the ROM, an address
is placed on the address bus, the chip is
enabled, and a short time later (called theaccess time), data appears on the data bus.
Address
input lines
A0
A1
A2
A3
A4
A5
A6
A7
E0
E1
O0
O1
O2
O3
Dataoutput
lines
Address
input lines
Data
outputs
Address transition
Data output
transition
ta
Chip
select
Valid data on output lines
Valid address on input lines
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Types of ROM
Written during manufacture
Very expensive for small runs
Programmable (once)
PROM
Needs special equipment to programRead mostly
Erasable Programmable (EPROM)
Erased by UV
Electrically Erasable (EEPROM) Takes much longer to write than read
Flash memory
Erase whole memory electrically
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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10thed
Summary
Flash Memory
Flash memories are high density read/write memories that
are nonvolatile. They have the ability to retain charge for
years with no applied power.
Flash memory uses a MOS transistorwith a floating gate as the basic storage
cell. The floating gate can store charge
(logic 0) when a positive voltage is
applied to the control gate. With little or
no charge, the cell stores a logic 1.
Control
gate
Floatinggate Drain
Source
MOStransistorsymbol
logic 0 is stored logic 1 is stored
The flash memory cell can be read by applying a positive voltage to the
control gate. If the cell is storing a 1, the positive voltage is sufficient to
turn on the transistor; if it is storing a 0, the transistor is off.
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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10thed
Summary
Flash Memory
Flash memories arranged in arrays
with an active load. For simplicity,
only one column is shown. When a
specific row and column is selected
during a read operation, the active
load has current.
Row select 0
Row select 1
Row select n
Reference
Active load
+V
ComparatorData out 0
Bit line 0
Column select 0
One drawback to flash memory is that
once a bit has been set to 0, it can be
reset to a 1 only by erasing an entireblock of memory. Another limitation is
that flash memory has a large but finite
number of read/write cycles.
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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10thed
Memory Expansion
Memory can be expanded in either word size or word
capacity or both.
To expand word size:
m bits
m bitsAddress
bus
m bits
2nbits
Controlbus
Data bus
RAM 2m
2n
Datain/out
RAM 22mn
RAM 12
mn
Datain/out
DD
nbits n bits
Notice that the data bus
size is larger, but the
number of address is
the same.
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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10thed
Databus
RAM 2M 8
Addressbus
21 bits
Control
bus
20 bits
EN
EN
RAM 21M 8
RAM 11M 8
8 bits
8 bits
8 bits
20 bits
Memory Expansion
To expand word capacity,
you need to add an address
line as shown in this example
Notice that the data bus size does
not change.
What is the purpose of the inverter?
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Organisation in detail
A 16Mbit chip can be organised as 1M of
16 bit words
A bit per chip system has 16 lots of 1Mbitchip with bit 1 of each word in chip 1 and
so on A 16Mbit chip can be organised as a 2048
x 2048 x 4bit array
Reduces number of address pins
Multiplex row address and column address
11 pins to address (211=2048)
Adding one more pin doubles range of values so x4capacity
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Refreshing
Refresh circuit included on chip
Disable chip
Count through rows
Read & Write back
Takes time
Slows down apparent performance
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Typical 16 Mb DRAM (4M x 4)
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Packaging
256kB t M d l
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256kByte Module
Organisation
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1MByte Module Organisation
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Interleaved Memory
Collection of DRAM chips
Grouped into memory bank
Banks independently service read or writerequests
K banks can service k requestssimultaneously
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Error Correction
Hard Failure
Permanent defect
Soft Error
Random, non-destructive
No permanent damage to memory Detected using Hamming error correcting
code
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Error Correcting Code Function
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Hamming Code Syndrome
If we compare the read K bits compared with thewrite K bits, using an EXOR function, the result is
called the syndrome.
If the syndrome is all zeros, there were no errors.
If there is a 1 bit somewhere, we know it represents
an error.
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Hamming Code Design determining K
To store an M bit word with detection/correction takes M+K bit words
If K =1, we can detect single bit errors but not correct them
If 2K
- 1 >= M + K , we can detect, identify, and correct all single biterrors, i.e. the syndrome contains the information to correct anysingle bit error
Example: For M = 8: and K = 3: 231 = 7 < 8 + 3 (doesnt work)and K = 4: 241 = 15 > 8 + 4 (works!)
Therefore, we must choose K =4,i.e., the minimum size of the syndrome is 4
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Increased word length for error correcting
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Hamming Code Syndrome Design Criteria
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A Layout of Data and Check Bits that Achieves Our Design Criteria:
Bit position 12 11 10 9 8 7 6 5 4 3 2 1
Bit number 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001Data bit D8 D7 D6 D5 D4 D3 D2 D1
Check bit C8 C4 C2 C1
C1 is a parity check on every data bit whose position is xxx1
C1 = D1 exor D2 exor D4 exor D5 exor D7
C2 is a parity check on every data bit whose position is xx1x
C2 = D1 exor D3 exor D4 exor D6 exor D7
C4 is a parity check on every data bit whose position is x1xx
C4 = D2 exor D3 exor D4 exor D8
C8 is a parity check on every data bit whose position is 1xxx
C8 = D5 exor D6 exor D7 exor D8
Why this ordering? Because we want thesyndrome, the Hamming test word,
to yield the address of the error.
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Example:
Data stored = 00111001
Check bits:
Putting it together:
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Example:
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Example:
Word fetched: Check Bits:
Putting it all together:
Comparing:
C8 C4 C2 C1
0 1 1 1 Orig Check Bits0 0 0 1 New Check Bits
0 1 1 0 Syndrome
0110 = 6 bit position 6 is
wrong, i.e. bit D3 is wrong
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Increased word length for error correcting
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SEC-DEC Example Requires One Extra Check Bit
Single Error
Correction:
Single Error Correction,
Double Error Detection:Word With Even Parity Word With Even Parity With Two Errors
With Errors Identifying Error SEC Attempt IS SEC Correct? Extra Bit Confirms DE
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Increased word length for error correcting
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Advanced DRAM Organization
Basic DRAM same since first RAM chips
Enhanced DRAM
Contains small SRAM as well
SRAM holds last line read (c.f. Cache!)
Cache DRAMLarger SRAM component
Use as cache or serial buffer
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Synchronous DRAM (SDRAM)
Access is synchronized with an external clock
Address is presented to RAM
RAM finds data (CPU waits in conventionalDRAM)
Since SDRAM moves data in time with system
clock, CPU knows when data will be ready
CPU does not have to wait, it can do somethingelse
Burst mode allows SDRAM to set up stream of
data and fire it out in block
DDR-SDRAM sends data twice per clock cycle(leading & trailing edge)
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SDRAM
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SDRAM Read Timing
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RAMBUS
Adopted by Intel for Pentium & Itanium
Main competitor to SDRAM
Vertical package all pins on one side
Data exchange over 28 wires < cm long
Bus addresses up to 320 RDRAM chips at1.6Gbps
Asynchronous block protocol
480ns access timeThen 1.6 Gbps
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RAMBUS Diagram
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DDR SDRAM
SDRAM can only send data once per clock
Double-data-rate SDRAM can send datatwice per clock cycle
Rising edge and falling edge
DDR SDRAM
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DDR SDRAM
Read Timing
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Simplified DRAM Read Timing
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Cache DRAM
Mitsubishi
Integrates small SRAM cache (16 kb) ontogeneric DRAM chip
Used as true cache
64-bit linesEffective for ordinary random access
To support serial access of block of data
E.g. refresh bit-mapped screen
CDRAM can prefetch data from DRAM into SRAMbuffer
Subsequent accesses solely to SRAM
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Reading
The RAM Guide
RDRAM
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Consider a dynamic RAM that must be
given a refresh cycle 64 times per ms.Each refresh operation requires 150 ns; amemory cycle requires 250 ns.Whatpercentage of the memorys totaloperating time must be given torefreshes?
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1. Static RAM is
a. nonvolatile read only memory
b. nonvolatile read/write memory
c. volatile read only memory
d. volatile read/write memory
2009 Pearson Education
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2. A nonvolatile memory is one that
a. requires a clock
b. must be refreshed regularly
c. retains data without power applied
d. all of the above
2009 Pearson Education
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3. The advantage of dynamic RAM over static RAM is that
a. it is much faster
b. it does not require refreshing
c. it is simpler and cheaper
d. all of the above
2009 Pearson Education
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4. The first step in a read or write operation for a random
access memory is to
a. place a valid address on the address bus
b. enable the memory
c. send or obtain the data
d. start a refresh cycle
2009 Pearson Education
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2009 Pearson Education
5. The output enable signal (OE) on a RAM is
active
a. only during a write operation
b. only during a read operation
c. both of the above
d. none of the above
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2009 Pearson Education
6. When data is read from RAM, the memory location is
a. cleared after the read operation
b. set to all 1s after the read operation
c. unchanged
d. destroyed
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7. An EPROM has a window to allow UV light to enterunder certain conditions. The purpose of this is to
a. refresh the data
b. read the datac. program the IC
d. erase the data
2009 Pearson Education
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8. The small triangles on the logic diagram indicate that
these outputs are
a. not used
b. tri-stated
c. inverted
d. grounded
2009 Pearson Education
ROM 256 4
0
&EN
7
A0
255
D
D
D
D
Address
input lines
A0
A1
A2
A3
A4
A5
A6
A7
E0
E1
O0
O1
O2
O3
Dataoutput
lines
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9. Using two ICs as shown will expanda. the word size
b. the number of words available
c. both of the above
d. none of the above
2009 Pearson Education
m bits
m bitsAddress
bus
m bits
2nbits
Controlbus
Data bus
RAM 2m2n
Datain/out
RAM 22m n
RAM 12
mn
Datain/out
DD
nbits n bits
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10. On a hard drive. information about file names, locations,
and file size are kept in a special location called the
a. file location list
b. file allocation table
c. disk directory
d. stack