04ECE108Ch3Two Termina Pull Up Inverters2015

3. Two-Terminal Pull up MOSFET Inverters: General Characteristics

ECE 108

1 Esener ECE108

A fluidic inverter

Esener ECE108 2

3. 1. Inverter Currents and Voltages

3 Esener ECE108

S

V DD

LOAD or PULL-UP

D

V G

+

V in = V GS

DRIVER or PULL-DOWN

V 0 = V DS

+

VL=VDD-VO

ID

Device Equations

IL = fL(VL)

ID = fD(VGS; VDS; VT )

Circuit Equations

VL=VDD-VO

ID = IL

fL(VDD-VO) = fD (VIN; VO; VT )

VIN =VGS VO =VDS

=> Transfer characteristics

S

V DD

KL

D

V G

+

V in = V GS

V 0 = V DS

+

IL=KL(VDD-VO) IL

3.2. INVERTER THRESHOLD VOLTAGE

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T T T

T

2

inv inv

inv DD T

2 2V V V V V V 0

B B

1 V V [1 1 2 V V ]

B

DD

B

The inverter logic threshold voltage is the input voltage that results in an equal

output voltage (Vinv =VGS = VDS = VO) (Text book uses VM for Vinv)

Using the constraint, Vinv=VGS = VDS

2

inv

L

DinvDD

invDS

2

invD

DSDDLT

T

VV2K

kVV

VV

VV2

k)V(VK

VIN > Vinv Output Low

VIN < Vinv Output High

V B Note BK

kLet 1-

L

D

3.3. COMPUTING VOH & VOL

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0II LD

Neglecting the leakage current in the pull down MOSFET (off)

IL=KL(VDD-VO) } =>

=> VOH = VDD

VIN=VGS=0 => VGS < VT => Pull down off ID = 0

VOH for VIN=0

VOL for VIN = VDD

TDD

DDOL

2

OL

DDOLTDD

2

OL

2

OLOLDDDOLDDL

VVB1

VV

small very is V sinceand

0B

2VVVV

B

12V

2

VVVVk)V(VK T

VGS > VGS*=> Pull down is Linear

with B.decreases

V seen, can be As OL

fL(VDD-VO) = fD (VIN; VO; VT )

KL(VDD-VO) = 0

3.4. DECIDING ON DRIVER STATE

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V KI assumingand

VV VV

LLL

in

GSDSo

2**

*

2*

22

)(T

T

VVK

kVVV

VVV

VVk

VVKGS

L

DDDTGS

TGSDS

GSD

DSDDL

2* *

-1

*

22 0.........

Note B V

11 2 1

T T

T

L LGS GS DD

D D

D

L

GS DD

K KV V V V V

k k

kLet B

K

V V BVB

Saturation - Linear Transition (Vin=VGS*)

VGS* is the input voltage that biases the driver at the edge of saturation and linear

modes of operation. We need to solve for

Rearranging

fL(VDD-VO) = fD (VIN; VO; VT )

With the constraint T

*

GSDS VVV

Defining

VIN > VGS* pull down Linear

VIN < VGS* pull down Saturated

ESTIMATING

VOLTAGE TRANSFER CHARACTERISTICS (VTC)

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linear.or saturationin down PullVV if

V = V0Ioffdown PullVV if

V and to V toV Compare

TGS

DDDSDTGS

T

*

GSGS

TGSDS

2

TIND

ODDL

*

GSGS

VVV ifcheck sure, makeTo

)V(V2

k )V-(Vf Compute

saturation VV

*

GS GS

DS GS T

V V linear

To make sure and to pick the right result,

check if V <V -V

A. Determine VT and VGS*

]2

V-)VV[(V k)V-(Vf Compute

2

OOTINDODDL

B.

C.

D.

fL(VDD-VO) = 0

3.5. POWER DISSIPATION

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When VGS VT , the driver is "on".

DD D DD L L DD O

2

DD L DD O DD L

P V I =V I ; I G (V -V )

=> P V G (V -V ) ~ V G

L

•

Power dissipation includes the power dissipated in the stable states (Static Power Dissipation)

plus the power dissipated during the transition (Dynamic Power Dissipation).

For MOS inverter with 2-terminal loads, SPD >> DPD

For MOS inverters driving a capacitive load SPD (“Low”) >> SPD (“High”)

Calculating SPD (Low)

For a two-terminal load MOS inverter the power is mostly dissipated at the load

3.6. VTC FEATURES:

3.6.1 Dynamic Range & Slope of VTC

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TDD

OL

OH

TDD

DDOLDDOH

VVB1V

V = Range Dynamic

VVB1

VVand VV Using

As can be seen, the dynamic range increases with B.

Dynamic Range

Dynamic range is the ratio of the output high to outpul low voltage (or current).

It is a measure of the separation of logic levels and can affect the noise performance

Slope of VTC

The slope determines the width of the transition region

DD

2

inO

2

inD

ODDL VVV2

BV VV

2

k)V(VK TT

OIN T

IN

dVslope of VTC B(V -V )

dV

with B.increases slope theseen, can be As

Assuming pull down saturated

Slope= -B(Vin-VT)

3.6.2 NOISE MARGINS

Noise margin is the maximum noise voltage added to the input signal that does not cause an undesirable change at the output.

• Low input Vin < V*IL

• Transition V*IL< Vin < V*IH

• High input Vin > V*IH

NML = V*

IL -V*OL NMH = V*

OH -V*IH

dV o

dV i = - 1

dV o

dV i = - 1

V iL * V iH

* V OH

* V OL *

V OH *

V OL *

V DD

V DD

VOL= VIL

VIH

Both input and output axis have same units

VOH*

VOL*

NMH NML

VOL* VIL* VOH* VIH*

VOL= VIL

VIH

NOISE MARGINS - LOGIC REGENERATION

Assumptions: •Both inverters have

identical VTC •Both input and output

axis have same units

VOH*

VOL*

NMH NML

VOL* VIL* VOH* VIH*

VOL= VIL

VIH

LOGIC REGENERATION

VOH*

VOL*

NMH NML

VOL* VIL* VOH* VIH*

VOH= VIH

VIL

LOGIC REGENERATION

VOH*

VOL*

NMH NML

VOL* VIL* VOH* VIH*

VOL= VIL

VIH

LOGIC REGENERATION

VOH*

VOL*

VOH*

VOL*

NMH NML

IMPACT OF VTC ON NOISE MARGINS

VOH*

VOL*

VOH*

VOL*

NMH=0 NML

IMPACT OF VTC ON NOISE MARGINS

VOH*

VOL*

VOH*

VOL*

NMH=0 NML

IMPACT OF VTC ON NOISE MARGINS

VOH*

VOL*

VOH*

VOL*

NMH< 0 NML

IMPACT OF VTC ON NOISE MARGINS

NOISE MARGINS

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Finding VIL* (Assume pull down Saturated)

O D DD

L

1V I V

K

* * **

IL T2

*DD IL T

11

B V V 1k

I V V2

O O D D

LIL D IL IL

dV dV dI dI

dV dI dV K dV

*

IL T T

* 2DOH T T DD

L

*

OH DD

V V +1/B V

kV (V +1/B-V ) V

2K

1V V

2B

Then,

v in

VO

VOH

VOL

VDD VT

*

OHV

*

ILV

VTC FEATURES: NOISE MARGINS

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3.5.3. Finding VIH* (Assume pull down Linear)

VVVk=V

I ;Vk

V

I

2

VVVVkI

1

OTin

O

DOD

in

D

2

OOTinDD

)V

I)/(

V

I(

dV

dV

O

D

in

D

in

O

D

L

DDO

2

O23

DTOin

OTin

O

IK

1V=Vand

kVIand V2VV

1VVV

V

Theorem: If f(x,y) is continuous in a region and its partial derivatives with respect to x and y are also

continuous in this region, and y can be expressed in function of x then

dy/dx = -(df/dx)/( df/dy); Using y= VO, x = Vin and f = ID; we obtain,

=> V*OL = VDD - B (3/2 V*

OL2)

TDD

*

IH

DD

*

OL

V16BV13B

2V

16BV13B

1V

=>

]2

V-)VV[(V kI

2

OOTINDD

v in

VO

VOH

VOL

VDD VT

*

OLV

*

IHV

VTC FEATURES: NOISE MARGINS

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Using noise margin definitions let’s compute

NMH VOH

* VIH

* and NML VIL

* VOL

*

*

IL T T

*

OH DD

V V +1/B V

1V V

2

B

TDD

*

IH

DD

*

OL

V16BV13B

2V

16BV13B

1V

H DD DD T

L T DD

1 2NM V 1 6BV 1 V

2B 3B

1NM V +1/B- 1 6BV 1

3B

v in

VO

VOH

VOL

VDD

*

OHV

*

IHV*

OHV

*

OLV

*

ILV*

OLV

NML NMH

Non Ideal Transfer Characteristics of a real inverter

NM H

V in (V)

NM L

V M

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

V out (V)

VO

L = VIL

VIH

Non Ideal speed response

Typically switching does not occur instantaneously • Rise and fall times are finite • Leading to a significant inverter

propagation delay

Ideal speed response with Negligible rise and fall time And no propagation delay

Bit Error Rate

• BER is closely related to the distortion introduced by the inverter including finite rise and fall times, overshoots and signal jitter. One way to measure BER is through eye diagrams that are obtained by integrating the output of an inverter that is fed by a random sequence of bits that is sufficiently long. By looking at the closing of the eye one can approximately determine the BER.

• A direct measurement can also be performed by counting the errors at the output of the inverter. This can take a very very long time and is generally only practiced in communication circuits where the BER is around 10-9 and bit rates exceed 1Gb/s

Vin

Vout

t

10%

90%

Vdd

0V

t

m1

m0

0

1

BER = Qm1 - m0

+1 0

Speed Response -Bit Error Rate - Eye Diagram