04799231-2.pdf

938 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009

Design of a CMOS Tapered CascadedMultistage Distributed Amplifier

Amin Arbabian, Student Member, IEEE, and Ali M. Niknejad, Member, IEEE

Abstract—This paper presents the design and measurement ofa distributed amplifier (DA) in a standard 90-nm CMOS process.To improve the gain and bandwidth (BW) of the DA, the use ofan elevated coplanar waveguide line and also impedance taperingin the synthesized sections are proposed. The effects of elevationand shielding filaments on the impedance, loss, and effective di-electric constant of the transmission line are investigated and ac-companied by measurements. A methodology for CMOS DA de-sign is described that can take advantage of the multiple degrees offreedom in terms of device size, topology, and aspect ratio availablein these processes. The fabricated tapered cascaded multistage DAachieves a 3-dB BW of 73.5 GHz with a passband gain of 14 dB.This results in a gain-BW product of 370 GHz. The realized 0-dBBW is 83.5 GHz and the input and output matchings stay betterthan 9 dB up to 77 and 94 GHz, respectively. The chip consumesan area of 1.5 mm 1.15 mm, while drawing 70 mA from a 1.2-Vsupply.

Index Terms—Broadband amplifiers, cascaded multistagedistributed amplifier (DA), CMOS DA, CMOS millimeter-waveintegrated circuits, elevated coplanar waveguides (E-CPWs),millimeter-wave amplifiers, tapering, transmission lines.

I. INTRODUCTION

W IDEBAND circuits find applications in various fieldssuch as high-speed links, broadband radio transceivers,

high-frequency instrumentation circuitry, and high-resolutionradar and imaging systems. With the scaling of CMOS tech-nology and transistor cutoff frequencies in excess of 100 GHz,considerable research effort is invested in CMOS broadband cir-cuits. CMOS is a low-cost (high-volume) alternative to III–Vtechnologies that are currently the main option for millimeter-wave components. CMOS technology provides many advan-tages as flexibility in number and topology of active devices anddisadvantages mainly related to the passive components on thelossy substrate. Mainstream CMOS technology does not pro-vide additional options for RF and microwave circuits and thisresults in excessive conductive (series) and dielectric (shunt)losses in passive components. Lower intrinsic gain from the de-vices also decreases the margin for modeling errors and requirescareful prediction of device characteristics.

Manuscript received August 01, 2008; revised December 20, 2008. First pub-lished March 10, 2009; current version published April 08, 2009. This workwas supported by the Berkeley Wireless Research Center, the National Sci-ence Foundation (NSF) under NSF Infrastructure Grant 0403427, by STMi-croelectronics under a foundry donation, and by the NSF under NSF GrantECCS-0702037.

The authors are with the Berkeley Wireless Research Center, Departmentof Electrical Engineering and Computer Sciences, University of California atBerkeley, Berkeley, CA 94720 USA.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2009.2014433

Distributed amplifiers (DAs) provide a large bandwidth(BW) in a given process with low sensitivity to mismatches andmodeling deficiencies, and therefore, are a prime solution forextremely wideband amplification. The operation of a DA relieson the operation of a synthesized transmission line formed byexternal inductive elements with the parasitic capacitancesfrom active devices. The addition of signal currents on thelow-impedance drain line leads to a relatively low gain, albeit alarge BW. Numerous CMOS and silicon-based DAs in variousforms have been reported [1]–[6].

Increasing the gain of CMOS DAs usually comes at the heav-iest tradeoff in BW. Other amplifiers that achieve high BWscan only provide high gains at the lower part of the availablespectrum (based on the speed of the process) and this is mainlythrough multiresonant and compensation techniques that oftenprovide nonpredictable peaking and droops, and hence, severegroup delay variations. In the DA regime, previous techniquesto increase the gain rely on cascading elements and sections [2],[4] and this, without provisions, can significantly reduce the BWthrough the introduction of multiple poles or cause of unpre-dictable effects in gain and BW. This paper discusses the designof a multistage cascaded DA with tapered segments, as well asfilter-synthesis-based pole placement in the artificial line sec-tions [7]. It is shown that tapering can provide some of the ben-efits of open idle termination while not sacrificing BW in inputand output matching.

Here, we also present a new methodology to pick the optimaldevice size and topology for use in the DA. Additional devicemodeling is performed to take into account specific topolog-ical layout issues in a multistage DA and to pinpoint the cru-cial traces for stability and gain rolloff prevention. This com-bination of concurrent device modeling and circuit design withcareful custom layout optimization allows for a large achievableBW. To realize a high characteristic impedance, elevated trans-mission lines are used for the synthesized segments. Design andmeasurement results of a prototype tapered cascaded multistagedistributed amplifier (T-CMSDA) will be described.

II. PASSIVE ELEMENTS

One of the main issues with the design of a CMOS DA is theinductive elements in the synthesized transmission lines. Tra-ditionally, these elements have been realized using spiral in-ductors in CMOS circuits. On-chip spiral inductors are verycommon and by using the right geometry, the quality factorand the self-resonant frequency (SRF) could be optimized forthe required inductance value. However, when small inductancevalues are required, spirals introduce a problem. In a DA, thespiral inductor (an inherently one-port element) is driven from

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ARBABIAN AND NIKNEJAD: DESIGN OF CMOS T-CMSDA 939

opposite sides as a two-port element (the signal comes in fromone side and exits the other side). This further complicates thepicture with the additional leads dependent on the size of thespiral, as well as the way it would fit with the rest of the DA.Given that the spirals do not lend themselves to an accurate scal-able model, it is rather difficult to design using these elementsunless several iterations between the full-wave electromagnetic(EM) solver and the circuit analyzer are performed. Even then,the position of nearby elements and unavoidable ground planesin the final layout could alter the inductance value and/or changethe self-resonance frequency.

For large BW DAs, the desired value of the inductor for theline is quite small. This is because the ratio of inductance to ca-pacitance being constant (and proportional to the required char-acteristic impedance of the line), the product determines the BWof the synthesized line beyond which the operation of the DA isnot possible. The required inductance value is in the 40–140-pHrange where the lower side corresponds to the inductances in the

-derived sections.Transmission lines are used as inductive elements in the syn-

thesized sections of a DA to remedy some of the issues forhigh-frequency operation. CMOS transmission lines can be rel-atively accurately modeled and they are inherently two-port de-vices. Our approach has been to use a set of measurement-baseddata to calibrate the loss parameters in the EM simulator and toverify this with measurements from various passive components(transmission lines, inductors, and transformers). This allowsfor dependable data from the EM solver and makes accuratemodeling of transmission lines possible. Note that we requiretransmission lines of high characteristic impedance . Onecan calculate the equivalent impedance by modeling the sectionbetween two transistors by a -model and with a short line ap-proximation

(1)

where is the delay in the section. Equation (1) shows that theinductance of the segment can be approximated by . Sim-ilarly, the total capacitance of the section can be approximatedby , half of this on each side of the model. A transmissionline with extra parasitic capacitances loading it periodically hasan approximate characteristic impedance of

(2)

Replacing by and replacing by withbeing the wave velocity in the line, one can derive the re-

quired segment length similar to [8] as

(3)

On the other hand, the maximum attainable BW of the line de-pends on the length of the segment. Quantitatively, the BW of asynthesized line is given by .

Fig. 1. Line BW limitation due to the initial � of transmission line.

Fig. 2. Equivalent loss tangent of the dielectric (to model the shunt losses) forvarious gap spacings and two different CPW structures (M7 only and M6–M7combination).

Fig. 1 illustrates the required initial for a desired cutoff fre-quency given realistic loading from 90-nm CMOS devices. Im-pedances in excess of 85 will be required to achieve amplifierswith BW larger than 70–80 GHz. This is a challenge in a scaledstandard CMOS process with low-resistivity silicon substrate,thin oxide stack, and no thick metal option.

For the realization of high-impedance transmission lines,the coplanar waveguide (CPW) structure is the best optionamong conventional topologies, especially in a digital CMOSprocess where the stack height does not suffice for design ofhigh-impedance microstrip lines. The grounded CPW mayalso produce higher losses at high frequencies [14], as well ashaving a lower overall characteristic impedance. In an inte-grated CPW, the impedance increases by decreasing the ratio

where is the width of the signal conductorand is the gap spacing. Increasing will increase the shuntlosses. Fig. 2 shows the increase in the equivalent loss tangentof the dielectric as a function of the gap spacing for two dif-ferent CPW structures. The data is from measurements in the90-nm standard CMOS process used in the study. The ofthe lines covers the range from 32 to 65 based on the choiceof linewidth and spacing. It is interesting to note that movingaway from very small gap spacings can actually slightly de-crease the conductive losses since it reduces field concentrationin the sides of the signal conductor and can result in a moreeven current distribution. However, the overall losses increasesharply (since increases) for a large gap spacing required


Fig. 3. Conceptual layout of shielded E-CPW (left) and illustration exagger-ating current flow and electric field in both cases (right).

for impedances larger than 70 . Decreasing will also havesome effect in increasing line impedance (depending on the

ratio); however, this will result in increase in conductivelosses through the signal conductor.

To provide the higher impedance while minimizing theincrease in losses, we propose using elevated CPW (E-CPW)transmission lines in the DA structure. Here, the ground con-ductors will be lowered with respect to the signal conductor.This way, the lateral capacitance of the line is reduced (bypreventing a “face to face” structure) and also the physical dis-tance of the line to ground is increased. This will lead to higherimpedance CPW lines. Lower loss is achieved as more fieldsare “captured” by the ground line and also the current is moreevenly spread across the signal conductor. To further reducelosses, shielding metal filaments could be added underneath thetransmission line. This would add shunt capacitances withoutaltering the inductance very much, and hence, “slow down” thewave and require shorter length lines for the same inductance.Line elevation, on the other hand, leads to minor decrease inthe effective dielectric constant of the line. Although the twoeffects are opposite, the final wave-velocity could remain lowerthan a conventional CPW with the right choice of elevationand spacing. Fig. 3 shows the conceptual layout of a shieldedE-CPW together with an illustration that exaggerates currentflow and electric field in both cases for clarification.

To confirm the effect of elevation, simulations were per-formed via Ansoft’s High Frequency Structure Simulator(HFSS) using the 90-nm CMOS process stack properties andloss parameters. The signal line is assumed to stay on thetop metal line and the ground line is shifted for comparitivepurposes. In these simulations, the ground line thickness is notchanged. This could be achieved in practice by stacking twometal lines together. Fig. 4 shows the simulated characteristicimpedance, loss, and resonator of the E-CPW lines (withno shielding filaments). Resonator is plotted to show thateven accounting for the change in wave velocity elevation, theoverall equivalent losses for a given phase shift reduces. InFig. 5, the simulated losses for various elevations are shown interms of frequency.

Fig. 6 shows the effective dielectric constant derived fromtransmission parameters of the elevated line. As predictedabove, line elevation does actually increase the effective wavevelocity. This is explained in part due to the fringing fieldsover several stack materials in the oxide layers similar to amicrostrip line with air interface.

Fig. 4. HFSS simulations of: (a) � , (b) loss, and (c) resonator � for variouselevation and burial conditions and two lateral gap spacings ��.

To verify the simulations, a set of test structures werefabricated and measured. Fig. 7 shows the measurements ofcharacteristic impedance and also loss (decibels/millimeter)for a wide-gap E-CPW both with and without the shieldingelements [11]. Measurements are accompanied by simulationsfrom HFSS (for the nonshielded case). A relatively close matchbetween simulations and measurements are obtained, with thepossible explanation for the minor discrepancy arising fromthe effective dielectric constant of the oxide layers employedin HFSS. Metal filaments reduce losses at the cost of reducedimpedance. This will lead to a lower inductance, and hence,a longer required line, but at the same time lower losses, andhence, a tradeoff.


Fig. 5. HFSS simulations of loss for various elevations with respect to fre-quency.

Fig. 6. HFSS simulations of effective dielectric constant for various elevationsin terms of frequency.

Fig. 7. Measurements of� (top) and loss (bottom) of a wide-gap E-CPW lineboth with and without shielding filaments.

To verify the extent to which elevation can reduce losses,a further step was taken with using filaments on the poly and

Fig. 8. Measurements of a shielded E-CPW with M1 and poly as filaments.

Fig. 9. Schematic diagram (right) of cascode device with important parasiticelements shown. Stability factor (top) and � (bottom) in case of added induc-tance in the gate of the cascode device are also shown.

M1 layer with the signal line being on the aluminium cappinglayer. This is an extreme case of elevation and shielding. Fig. 8shows the measurements of the loss of this transmission line.This shows that the losses are considerably lower in the pro-posed case, and therefore, these transmission lines can even beused in cases where moderate impedances are required. The ef-fective permittivity related to the elevated line reduces from 4.3to 3.7 at frequencies close to 40 GHz.

III. DEVICE SIZE AND TOPOLOGY SELECTION

An issue concerning DA design in CMOS is the selection ofthe optimum device size. Conventional microwave DA designdoes not provide optimal design when applied to CMOS. This isbecause in CMOS technology, device sizing and exact topolog-ical layout (number of fingers) are free parameters and shouldbe exploited for DA design.

In order to exploit the extra degrees of freedom availablein CMOS technology, we exported first-order scalable devicemodel parameters into MATLAB. Together with CPW linemodels that were extracted from measurements, a parametricexpression for the gain of a conventional DA stage was derivedand optimized for a given BW. The gain function has differentsensitivities to various design parameters in our design space.


Fig. 10. Simulated DA gain at: (a) 60 GHz with varying device size/ number of devices and (b) for six devices with varying frequency/device sizes.

For a well-chosen line and finger width, it is seen that devicetopology, number of devices, and number of fingers are thethree most significant factors determining the gain. For devicetopology, cascodes and common-source topologies are the twomain candidates. The cascode device provides a higher stablegain at lower frequencies limited by a pole at approximatelyhalf the device cutoff frequency. Extra care must be taken withthe cascode device since parasitics can easily lead to instabilityand/or undesired gain peaking. HFSS co-simulations to captureextra layout-dependent parasitics were performed to ensurepredictable performance by the cascode elements. Fig. 9 showsthe schematic diagram of a cascode device with the importantparasitics annotated. To emphasize the significance of smallparasitic components, the effect of added inductance on the gateis illustrated both on the stability factor and of a sampleDA incorporating these cascode elements. To circumvent theseissues, apart from careful modeling using EM simulators,DA-friendly layout topologies for the cascode device (withappropriate rotation and aspect ratio for the input/output trans-mission lines and capacitances) were used with appropriatelocal bypass capacitors close to the gate. Any interconnectsection was designed to have the least added inductance.

Once the device topology is chosen (cascode versus commonsource), MATLAB simulations of the overall gain and BW wereperformed with number of devices and number of device fingersas the two main variables. Fig. 10 shows the simulated gain ofthe DA with finger width of 1.2 m. As these device models areapproximate scalable models, after this step, the closest tran-sistors to the candidates are chosen from the custom library andaccurate in-house models were used in the optimization process.It is observed that the gain is not constant for a constant “totalwidth” of all devices. Nor is the sensitivity to each parameterconstant for different decompositions of total width. Larger de-vices provide more gain with the same total width, but are moresensitive to various parameters, as well as showing more par-asitics in their structure. Fig. 11 shows the 2-D version of thesimulations for clarity. For our design, the 40- m cascode de-vice provides the optimal gain with 3–5 devices (depending onthe required BW).

This procedure will select the optimal topology for maxi-mizing gain and/or BW. There are additional figures of merit for

Fig. 11. Simulated DA gain versus number of devices for various number offingers.

a DA (output power, noise figure, efficiency, etc.) that could beused for the optimization process with the appropriate functions.

IV. TAPERING IN THE TRANSMISSION LINE SEGMENTS

The multistage DA has the advantage of having an extra de-gree of freedom in the choice of internal idle termination im-pedances. For a cascade of single-stage DAs, [9] suggests openterminations for maximizing the gain. However, this comes withthe cost of limitations on the BW from destructive combinationsof forward and backward traveling signals and limits the numberof stages. This results in poor input and output return losses. Theidle termination technique also cannot be used on the input andoutput lines since the return loss is not acceptable.

We propose tapering the impedance of the line segments,which can also be used on the interface sections if the taperingcoefficients are not too large as to cause undesired matchingproperties for the amplifier. In this tapering, the line segmentimpedances is tapered starting from the load impedance of 50and increased by (the tapering coefficient) per stage. Thiscould be achieved by the change in line lengths (and, hence,in the inductances) or by varying the spacing/height of the ele-vated-CPW to change the of the transmission lines. In thiswork, we have employed the former technique for better pre-dictability of the equivalent section impedance change. The ac-tive elements are kept identical in size, and hence, reflectionsoccur. This is in contrast with previous work on downsizing both


Fig. 12. T-section of a synthesized transmission line.

the active and passive impedance for improved BW [5] or outputpower [13].

To analyze a tapered synthesized line, one can follow severalapproaches. To begin, we predict the impedance of a uniformline based on the matrix of cascaded two-port sections[15]. The image impedance can be calculated as follows:

(4)

Here, the parameters are used to describe the inputimpedance of a T-section (Fig. 12). When an infinite numberof sections are added, the input impedance becomes

(5)

Equation (5) shows the impedance seen at the input of manyidentical cascaded T-sections with . It can beseen that if the frequency is much lower than the cutoff fre-quency of the line (a good assumption with high-impedancetransmission lines), then the familiar is a good ap-proximation.

One can observe the tapered transmission line in a DA as aloaded transmission line in which the loading is not periodic.Therefore, if (by approximation) the capacitive loadings are ab-sorbed into the specific sections, assuming a uniform absorp-tion, leads to for impedance ofeach section. Taking a step further, one may neglect the line ca-pacitance with respect to the parasitic capacitance of active ele-ments, a relatively good approximation for high- lines. Effec-tively, the line segment acts as an inductor and one may in factassume equal length cascaded lines with nonequal impedances.In the limit of short segments, this would lead to conventionalcontinuous impedance tapering (as in [15]) applied for matchingpurposes. The internal reflections are approximated as

(6)

If the segments are not so small for the continuous approxi-mations [15] to hold, one can sum all the reflections in (6). Thiswill lead to

(7)

Fig. 13. Schematic diagram of a tapered DA.

Here, is the sum of the length of all the lines before the threflection. In this work, as briefly discussed above, a multiplica-tive taper is assumed with the approximation of the length of theline being scaled by and the impedance by . Quan-titatively, for this tapering profile,

and one may obtain the following:

(8)

The final fraction in (8) is equal to for small valuesclose to unity. With this tapering profile, all the reflections areof equal size . Taking advantage of the propagation losseffect , one can allow the impedances further away fromthe termination to be more abruptly increased since their effectis somewhat mitigated by the loss. With the above equations andknowing device and transmission line frequency characteristicsand also the voltage standing-wave ratio (VSWR) tolerances,one can obtain the tapering coefficient.

From a different perspective, one can combine a linear incre-mental or exponential taper with filter synthesis methods [10] toachieve the impedance profile desirable for higher BWs in spiteof gain rolloff of active or passive elements. From a filter theoryperspective, once poles are brought closer to the imaginary axisin the synthesis process, the peaking will increase, which canpotentially cancel droops of active elements. Another factor thatneeds to be taken into account is the line cutoff frequency (or,equivalently, the low-pass filter cutoff) that is obtained once thetapering and other techniques are applied. Large segments of theline tend to dominate the cutoff frequency and this causes prob-lems, especially for more aggressive tapering coefficients.

In a DA, the current injection on the drain lines favors one di-rection for tapering rather than the other. One would desire thatcurrents be directed towards the final load rather than the idletermination and this would, for example, favor an “up-tapering”from the load impedance on the drain line towards the idle ter-mination. Fig. 13 shows the schematic diagram of a DA withtapering from the load. It is important to notice that apart fromthe reflections seen by the load impedance (determining theof the amplifier), internally, each of the active elements’ currentis divided unequally ( and in the figure) at the drain and isalso reflected multiple times before getting terminated on either


Fig. 14. Simulated gain with: (a) no tapering, (b) uniform tapering, (c) tapering with an open termination, and also (d) the return loss from uniform tapering.

side. The current divisions at the drain can be formulated usingthe section impedances as follows:

(9)

(10)

where the index increases towards the load to the right. Eachof the and components are reflected at all the intersec-tions to left and right before terminating at the load. To calcu-late the reflections, we need to keep track of the phase of thecombinational signals. The functions can be approximatedby or rather by the continuous approximation assumingsmooth impedance transitions.

Fig. 14 illustrates the effect of tapering by first-order simula-tions. Here, a simple model of DA neglecting higher order re-flections, which are mitigated by loss, has been utilized to pro-vide intuitive results. Fig. 14(a) shows the effect of having no ta-pering and terminating a DA drain line with various large loads.Fig. 14(b) uses multiplicative tapering all the way to the termi-nating resistance (with the same coefficient). Fig. 14(c) uses anopen termination with various tapering coefficients for the seg-ments. Here, there is a relatively large mismatch between the lastsegment and the termination element. In Fig. 14(d), first-ordercircuit simulations have been used for the case of uniform multi-plicative tapering [as in Fig. 14(b)] to verify possible applicationin the input and output stages. As observable in this figure, ta-pering provides means of extending the gain while having con-trol over different local gain variations (similar to conditionswith pole/zero placement).

V. EXPERIMENTAL RESULTS OF THE T-CMSDA

A T-CMSDA was designed and implemented in a 90-nm1P7M digital CMOS process with no additional RF options.

Fig. 15. Schematics of the T-CMSDA.

The native NMOS device has a post-layout GHz.The schematic of the T-CMSDA is shown in Fig. 15. Multistage


Fig. 16. �-parameter simulation and measurements of the T-CMSDA.

Fig. 17. Chip micrograph of the of the T-CMSDA.

amplifiers allow for extra degrees of freedom in the choice ofinternal and external termination impedances. The amplifier istested in a 50- environment.

A large series capacitor is used to ac couple the input of theamplifier. -derived matching sections are used to improvematching to required impedances. Intermediate terminations, aswell as the input and output terminations, are tapered (with dif-ferent coefficients) according to the descriptions in Section IV.To achieve the required frequency response, both line segmentsizes and input capacitance at the intersection nodes are varied.Series capacitors are used to control the equivalent inputcapacitance.

Fig. 18. Output compression point measurements of the T-CMSDA.

Fig. 19. Measured group delay of the amplifier in frequency band of interest.

Measurements were taken directly using wafer probes. Allthe pads and parasitics are included in the design, and hence,the measurements. The measured -parameters are shown in


TABLE ICOMPARISON TO OTHER PUBLISHED DAs

Fig. 16. The amplifier has an average passband gain of 14 dBwith a 3-dB BW of 73.5 GHz. The 0-dB BW of the ampli-fier is at 83.5 GHz. and of the T-CMSDA stay below

9 dB up to 77 and 94 GHz, respectively. The gain BW (GBW)product of this amplifier is 370 GHz. The 0-dB GBW is 419GHz. The chip micrograph is shown in Fig. 17, it consumes anarea of 1.15 mm 1.5 mm. The output referred 1-dB compres-sion point is shown in Fig. 18. The output power remains higherthan 0.2 dBm up to 60 GHz. Fig. 19 demonstrates the groupdelay of the T-CMSDA in the frequency band of interest. At lowfrequencies, the group delay variations are due to the ac cou-pling capacitor used. The amplifier draws 70 mA from a 1.2-Vsupply. Comparison to other published CMOS DAs is given inTable I.

VI. CONCLUSION

The design of wideband DAs in standard CMOS technologyhas been investigated and its issues highlighted. Several solu-tions to remedy the shortcomings in terms of gain, BW, and un-desirable rolloff effects have been proposed.

Passive element design is essential in the deeply scaledCMOS era for extremely high BW amplifiers. Although thecore active elements have been improving continuously, thepassive elements and the parasitic elements surrounding theactive components have not improved (if not worsened). Theapplication of E-CPW structures has been proposed for im-proved performance. Simulations and measurements confirmthat the E-CPW has a higher impedance with lower lossescompared to the CPW counterpart.

Conventional DA design often assumes a fixed size activedevice. In this design methodology, however, device size,topology, and aspect ratio are all free parameters that couldbe used to partially cancel the negative issues associated withlower gain and lossy substrates. An approach that restricts thedesign space to the most important parameters and optimizesfor given constraints was described in this paper. Absoluteperformance, as well sensitivity to various design parameters,can be investigated and designed for using this approach.

To increase the gain of the DA with minimal loss in BWthrough cascading gain stages, we used impedance tapering andresponse synthesis for the artificial sections. It was shown thattapering can provide some of the benefits of open idle termina-tion while not sacrificing BW in input and output matching.

An experimental prototype 73.5-GHz CMOS DA was imple-mented in a standard digital 90-nm CMOS process. The de-sign consists of the proposed device sizing and topology opti-mization methodology, concurrent device level layout optimiza-tion and modeling, E-CPW lines for high-impedance on-chiptransmission lines, and impedance tapering with filter-based re-sponse synthesize (pole placement) on the input/intermediate/output lines for increased BW and immunity to gain rolloff. Thefabricated amplifier achieves 370 GHz/419 GHz of 3-dB/0-dBGBW product. The entire circuit consumes 84-mW power from1.2-V supply.

ACKNOWLEDGMENT

The authors extend special thanks to B. Heydari, M. Bohsali,E. Adabi, B. Afshar, and S. Gambini for valuable discussions.

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Amin Arbabian (S’06) received the B.S. degree(ranked first in his field of electrical engineering,communications) from the Sharif University ofTechnology, Tehran, Iran, in 2005, the M.S. degreefrom the University of California at Berkeley, in2007, and is currently working toward the Ph.D.degree at the University of California at Berkeley.

In 2004 and 2005, he was a Research Consultantand the leader of the “Telecomm. Access for Ruraland Remote Regions” project with the Electronic Re-search Center (ERC), Iran University of Science and

Technology (IUST), and a Research Engineer with VSP Inc., Emad Semicon-ductor, and Basamad Azma Inc. During the summers of 2007 and 2008, hewas a Design Engineer with Tagarray Inc., Los Altos, CA, where he was in-volved with the sub-microwatt RFID project. He is currently an active memberof the Berkeley Wireless Research Center (BWRC), University of California atBerkeley. His research interests span microwave and millimeter-wave circuitsto imaging systems.

Mr. Arbabian was the recipient of the 2005 University of California atBerkeley departmental fellowship, the 2007 Natural Sciences and EngineeringResearch Council (NSERC) Canadian fellowship, the 2008 Analog DevicesOutstanding Design Award, and the Second Place 2008 RFIC Best StudentPaper Award.

Ali M. Niknejad (S’93–M’00) received the B.S.E.E.degree from the University of California at Los An-geles, in 1994, and the Master’s and Ph.D. degreesin electrical engineering from the University of Cali-fornia at Berkeley, in 1997 and 2000, respectively.

During his graduate studies, he authored ASITIC,a computer-aided design (CAD) tool that aids in thesimulation and design of passive circuit elementssuch as inductors into silicon integrated circuits.ASITIC is actively used by industry and academicresearch and development centers. Upon graduation

from the University of California at Berkeley, he worked in industry, wherehe focused on the design and research of analog RF integrated circuits anddevices for wireless communication applications. He is currently an AssociateProfessor with the Electrical Engineering and Computer Science Department,University of California at Berkeley, and Co-Director of the Berkeley WirelessResearch Center and the BSIM Research Group. His research interests are inthe area of wireless and broadband communications, including the implemen-tation of integrated communication systems in silicon using CMOS, SiGe, andBiCMOS processes. Focus areas of his research include analog and RF circuits,device physics and modeling, and numerical techniques in electromagnetics,with an emphasis on the analysis and modeling of active and passive devices atmicrowave frequencies for integrated circuit (IC) applications.

Prof. Niknejad has served as an associate editor for the IEEE JOURNAL OF

SOLID-STATE CIRCUITS. He currently serves on the Technical Program Commit-tees for the IEEE Custom Integrated Circuits Conference and the IEEE Interna-tional Solid-State Circuits Conference. He was a corecipient of the OutstandingTechnology Directions Paper Award presented at the 2004 IEEE InternationalSolid-State Circuits Conference for co-developing a modeling approach for de-vices up to 65 GHz.

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