02-ECE612-S14-CMOS Inverter.pdf

ECE 612 Design of Digital Integrated Circuits

Spring 2014

Lecture 2

CMOS Inverter

S. A. Ibrahim

Ain Shams University

ICL

Outline

The CMOS Inverter Noise Margin and Threshold

Voltage

The CMOS Inverter Propagation Delay and Switching

Speed

The CMOS Inverter Power Consumption

Sizing of the CMOS Inverter

FinFET Inverter

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Transfer Function

Switching waveforms

The Ideal Inverter

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Gain = 0

Gain = 0

Gain = ∞

Noise in Digital Circuits

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Inductive Coupling Capacitive Coupling Power and Ground

Noise

NML

NMH

VM = gate threshold voltage (mid-swing)

Noise margins = NML and NMH

The Real Inverter Transfer Function

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VOH VIH VIL VOL

VOH

tPLH , tPHL , tP , tr, tf

Propagation time (or propagation delay time or simply delay time):

tP = (tPLH + tPHL)/2

VSS = 0 V =

VDD =

VSS = 0 V =

VDD =

The Real Inverter Switching Waveforms

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The CMOS Inverter

Polysilicon

In Out

V DD

GND

PMOS 2l

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

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Notice:

Transistor threshold = Vtn or Vtp

Inverter threshold = VM

Normally VM = VDD/2 for symmetric NMs

ON OFF

LIN SAT

SAT SAT

SAT LIN OFF ON

CMOS Inverter Static Operation

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MOSFET Equations

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Long channel or small VDD Short channel and normal VDD

Inverter Threshold VM

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If VDD>>VDSAT and VT

pn

tnpntpDD

Mkk

VkkVVV

/1

/

For non-velocity-saturated devices

Inverter Threshold Variation

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MOSFET Switch Model

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How is a MOS transistor different from an ideal switch ?

Non-zero switch ON resistance

Parasitic capacitances

S D

CG G

CS S D

G

CD

Ideal switch One possible model of the

MOS transistor as a switch

RON

MOS ON Resistance

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S D

G

• The switch ON resistance RON ≠ 0

• RON is a non-linear resistor

• it changes with VDS

• region of MOS operation matters

• Suppose switch turns ON suddenly

• i.e. VGS jumps from 0 to VDD

• RON varies (as slope–1 of the red curve)

• A simple estimate of average RON

• RON ≈ slope–1 of blue line

Vo=2.5

0 0 . 5 1 1 . 5 2 2 . 5 0

1 0 0

2 0 0

3 0 0

4 0 0

5 0 0

6 0 0

Ids (mA)

Vds

𝑅𝑂𝑁 =𝑉𝐷𝑆𝐼𝐷𝑆

= 𝑅□𝐿

𝑊

The R□ of a MOSFET is inversely

proportional to the gate overdrive, VGS -VT

RON During Transition

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MOS Capacitance

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• Parasitic (undesirable) elements are everywhere

• Devices are small enough such that inductive effects are negligible.

• Capacitances dominate; and there are MANY

1. Cchannel – since channel connects S/D, it is split

2. Coverlap – gate overlaps S/D, and there is fringe cap from Gate

3. Cjunction – S/D form reverse-biased PN junctions with the body

4. Cj_sidewall – S/D different doping to the bottom and side

5. Cbody – from channel to body, quite small b/c of small L

Gate

Source Drain

C1 C2

C2

C3

C4 C5

C3

C4

Gate Capacitance

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Channel cap characteristics

• Split between S/D

• Varies with region of operation

Off MOSFET

• Cch = CGB

On MOSFET

• Cch = W*Lch*eox/tox

• Triode region

– C1A = C1B = Cch/2

• Saturated region

– C1A = 2/3Cch, C1B = 0

Cov = Cox*W*Lov*k, where k is a constant accounting for fringing

Removing technology dependence and assuming minimum channel length

Cgate = CG * W

Gate

Source Drain

C1A C1B

Self-Loading Capacitance

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• A transistor pulls current from its S/D,

so the S/D junction is often called the

Self-Loading Capacitance.

• CS/D = Cj_area + Cj_sidewall

• Cj_area = W*Ldiff*CJ(VS/D)

• Cj_sidewall = (W+2Ldiff)*CJSW(VS/D)

• Note that CJ and CJSW are

– layout dependent

– voltage dependent

– Ldiff is typically 5l (unshared and

contacted)

Ldiff

W

M

ORBOJ VVCC )/1/(

Where CO, VO, and M are

junction dependent constants

Can also be simplified as

Cjunction = CD,S * W

CMOS Inverter: Transient Response

t pHL = f(R on .C L )

= 0.69 R on C L

V out

R p

V DD

(a) Low-to-high (b) High-to-low

V out

R n

V DD

C L C L

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VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vout(V

)CMOS Inverter: Propagation Delay

tp = 0.69 CL (Rn+Rp)/2

tpHL tpLH

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𝑅𝑒𝑞 ≅3

4

𝑉𝐷𝐷

𝐼𝐷𝑆𝐴𝑇 (neglecting

Channel length mod.)

Choosing Wp/Wn Ratio

For symmetric inverter VM = VDD/2 and tPHL = tPLH, β

=Wp/Wn=µn/µp=Reqp/Reqn=r.

However, this does not guarantee minimum delay.

tPLH decreases with β whereas tPHL increases with β.

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Power Consumption

• Static (leakage) (low for low transistor count and perfected technology)

• Dynamic (to charge and discharge CL at a certain frequency: appreciable)

• Short-Circuit (when both PMOS and NMOS are ON: reduced in fast transitions)

circuitshortdynamicstatictotal PPPP

may be the most important

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Static Power

leakageDDstatic IVP

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• Leakage power increases exponentially with temperature.

• Leakage power affects stand-by time heavily.

Techniques to Reduce Static Power

Using transistors with higher

threshold voltages (HVT). Difficult

at low supplies.

Using technologies that contain

devices with sharper turn-off

characteristic for example SOI.

Using body biasing to increase

threshold voltage when off

(dynamic biasing used especially

in memories).

Increasing length and/or stacking

devices.

Power gating of different blocks

when not used (supply off or

reduced).

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>0

Dynamic Power

* An equal energy is needed to discharge CL (in the next half cycle)

* Therefore in one switching cycle we need an energy of CLVDD2

activityDDLDDL

dynamic fVCT

VCP

22

During

output

transition

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Techniques to Reduce Dynamic Power

Reducing the supply reduces

power substantially (quadratic) as

long as we can keep fclk (VDD>2VT).

Reducing the activity factor by

revisiting the Boolean functions on

top level. Reduce Glitches too.

Reducing capacitance by reducing

sizes of transistors and

interconnects whenever possible.

Dynamic voltage scaling (DVS).

Clock gating.

Parallel hardware may be used to

reduce global interconnect and

allow a reduction in supply voltage

without degrading system

throughput.

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[Burd, JSSC00]

Short-Circuit Power

• This average short-circuit current drawn from VDD results in Pshort-circuit

• Fast rise and fall times of input waveform reduce short-circuit power

During

input

transition

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activityDDSCDDpeakSCSC fVCfVItP2

Techniques to Reduce Short Circuit Power

Short-circuit current is reduced when we lower the

supply voltage. In the extreme case, when VDD < VTn +

|VTp|, short-circuit dissipation is completely eliminated.

With threshold voltages scaling at a slower rate than

the supply voltage, short-circuit power dissipation is

becoming of a lesser importance in deep-submicron

technologies.

Short-circuit power is consumed by each transition (increases with input transition time). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Increasing the output load capacitance reduces short-circuit power.

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Power-Delay & Energy-Delay Product

Used as quality measure of logic gates.

PDP is energy, so not so useful.

Assuming that NMOS and PMOS

transistors have comparable threshold

and saturation voltages,

where

This equation is only accurate as long as

the devices remain in velocity saturation,

which is probably not the case for the

lower supply voltages. S. A. Ibrahim

28

Outline

The CMOS Inverter Noise Margin and Threshold

Voltage

The CMOS Inverter Propagation Delay and Switching

Speed

The CMOS Inverter Power Consumption

Sizing of the CMOS Inverter

S. A. Ibrahim 29

Inverter with Load

Load (CL)

Delay

Assumptions: no load -> zero delay

CL

tp = k ReqCL

Req

k is a constant, equal to 0.69 (note ln (2) =0.69)

Req

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Layout-Aware Inverter with Load

Cint CL

Delay = kReq(Cint + CL) = kReqCint + kReqCL = kReq Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

2W

W

Intrinsic or internal or self-loading cap

External loading cap

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Load

Delay

kREQCint

Load

Delay = tp

Cint CL

Delay = tp = kReq Cint(1+ CL /Cint) = tpo(1+ CL /Cgin)

Cgn

Cgp = 2Ccgn

2W

W tpo CL

Cg

Cint Cg = Cg

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Cg vs. Cint

Cint = Cg ( for simplicity one assumes 1, it is indeed close

to 1 for most submicron processes)

f = CL/Cg = effective fanout (also called “electrical effort”)

tpo = 0.69ReqCint (zero-load delay or intrinsic delay)

Delay = tp = kReq Cint(1+ CL /Cint) = tpo(1+ CL /Cg)

= tpo(1+ f /)

Relative (Normalized) Delay d = tp /tpo = (1+ f /)

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Delay Formula

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Delay = tp = kReq Cint(1+ CL /Cint) = tpo(1+ CL /SCg)

tpo = k(Req/S) (SCint) f(S) = kReqCint Scaling W by a factor S: Req Req/S and Cint SCint

SCint

Req/S

Req/S

Size of a Single Inverter for a Given CL (1)

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Size of a Single Inverter for a Given CL (2)

large area and

wasted effort

SCint>>CL

Sizing an Inverter Chain

CL

In Out

1 2 N

tp = tp1 + tp2 + …+ tpN

jg

jg

popjC

Ctt

,

1,1

LNg

N

i jg

jg

p

N

j

jpp CCC

Cttt

1,

1 ,

1,

0

1

, ,1

Load cap

as if a gate N+1 exists

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The Tapered Buffer

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Cint fCint f2Cint fN-1Cint

Optimum Delay and Number of Stages

1/ gL

N CCFf

When each stage is sized by f and has same eff. fanout f:

N Ff

/10N

pp FNtt

Path (N-stages) delay

Effective fanout of each stage:

f

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Optimum Number of Stages

For a given load, CL and given input capacitance Cin

Find optimal sizing f

ff

fFtFNtt

pN

pplnln

ln1/

0/1

0

0ln

1lnln2

0

f

ffFt

f

t pp

f

FNCfCFC g

N

gLln

ln with 11

ff 1exp For = 0, f = e, N = ln F Special case: no self loading:

Exponential Buffer

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Optimum 𝒇 vs. 𝜸 in Tapered Buffers

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Exponential buff

(no self-loading)

tapered buff

(self-loading at = 1)

Cint = Cg

3.6 ( 4)

Buffer Design

1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3 (≈ exponential)

(Typical instead of 3.6)

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FO4 Delay

Want a way to characterize the delay of a circuit

(roughly) independent of technology

Most common metric:

Delay of an inverter driving four copies of itself (tFO4)

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UTB=ultra-thin body

FinFET Key Benefits

Lg Scaling: Supports smaller Leff at same Ioff Faster

Vg-Vt Scaling: Supports smaller Vt at at same Ioff lower supply

Lower power

Smaller Ioff lower sub-threshold leakage

A versatile model for double-gate, triple gate, even cylindrical gate

FET is available now from BSIM group at Berkeley. Passed

Industry FinFET standard balloting in Jan. 2012. (BSIM-CMG)

Fabs: Intel, Global, IBM, Samsung, TSMC

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FinFET vs. Planar MOSFET

Increase effective width for a given footprint: increase

Hfin and/or reduce fin pitch

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FinFET Inverter Layout

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Reading

Rabaey: Sections 1.3 and 3.3 and chapter 5.

Weste: Chapters 2 and 5 and Sections 2.1 and 2.2.

K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand,

“Leakage current mechanisms and leakage reduction

techniques in deep-submicrometer cmos circuits,”

Proceedings of the IEEE, vol 91, no. 2, pp. 305–327, Feb

2003.

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