01combinational Circuits

7/31/2019 01combinational Circuits

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Combinational Circuit

There are two types of circuits: Combinational circuit

Sequential circuit

Combinational Circuit performs an operation that

can be specified logically by a set of Booleanfunctions

A combinational circuit consists of logic gates

whose outputs at any time are determined from

the present combinations of input

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Combinational circuits are circuits without memory where theoutputs are obtained from the inputs only. A n-input m-output

combinational circuit is of the form

where, oi = f (i1; : : : ; in);


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Example:

Half/Full adder/substractor

- Binary ripple adder/substractor

- Look-ahead carry adder

- Code converter, Encoder/Decoder

- Magnitude comparator

- Multiplexer/Demultiplexer

- Read-only memory - Programmable logic array

- Programmable array logic

- Arithmetic logic unit

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Combinational Circuit Design

Design Procedure:

1. Determine the required number of inputs

and outputs

2. Derive the truth table that defines the

required relationship

3. Obtain the simplified Boolean functions for

each outputs

4. Draw the logic diagram and verify its

correctness

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Half AdderThe half adder accepts two binary digits on its input and produce

two binary digits on its outputs, the sum bit and carry bit as

shown above.

S = X YC = XY


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Full Adder

The full adder accepts three inputs and generates a sum

and carry out put.

Three inputs. Third is Cin

Two outputs: sum and carry


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Full Adder

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K Map for S

What is this?


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K Map for C

Carry out:

L i di


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Logic diagram

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Two Half Adders (and an OR)LOGIC CIRCUIT


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Four bit parallel adder

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Four bit parallel adder (Ripple carry adder)

It is possible to create a logical circuit using multiple full adders to addN-

bit numbers. Each full adder inputs a Cin, which is the Coutof the

previous adder. This kind of adder is a ripple carry adder, since each

carry bit "ripples" to the next full adder. Note that the first (and onlythe first) full adder may be replaced by a half adder.

In Ripple Carry Adder

Multiple full adders with carry ins and carry outs

chained together Small Layout area

Large delay time

If the delay for each full adder is 8ns then the total delay

for four bit parallel adder is 32ns. 13


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Subtractor

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Four bit subtractor

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Four bit parallel adder/Subtractor

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Serial Adder with Accumulator

Block Diagram for Serial Adder with Accumulator

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: Operation of Serial Adder

X Y Ci Si Ci+

t0

t1

t2

t3

t4

0101

0010

0001

1000

1100

0111

1011

1101

1110

0111

0

1

1

1

0

0

0

1

1

(1)

1

1

1

0

(0)

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State Graph for Serial Adder ControlNext State Sh

St = 0 1 0 1

S0

S1

S2

S3

S0

S1

S2

S3

S1

S2

S3

S0

0

1

1

1

1

1

1

1

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Derivation of Control Circuit Equations

AB A+B+

0 1

S0

S1

S2

S3

00

01

10

11

00

10

11

00

01

10

11

00

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Design of Fast Adders (CLA)

Carry lookahead logic uses the concepts ofgenerating andpropagating carries. Although in

the context of a carry lookahead adder, it is most natural to think of generating andpropagating in the context of binary addition, the concepts can be used more generally than

this. In the descriptions below, the word digitcan be replaced by bitwhen referring to binary

addition.

In carry look ahead adder ,the carry signals are calculated in advance , based on the input

signals.

Carry Ci+1

= XiY

i+ Y

iC

i+ C

iX

i= XiYi + Ci (Xi Yi)

= Gi + CiPi. (Generate Carry + Ci* Propagate Carry)

Where Gi is carry generate function and Pi is carry propagate function

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Carry Ci+1 = Gi + Ci Pii.e. Ci = (Gi-1 + Pi-1Ci-1) &

Ci-1 = (Gi-2 + Pi-2Ci-2).


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Design of 4-bit CLA

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Pi Ci + Gi = Ci +1

Si = Pi CiPi

Gi

Ai

B

i

Ci


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Design of 4-bit CLA

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Design of 4-bit CLA

The carry bits are the look-ahead carry bits.they are

expressed in terms of generate and propagate functions

along with initial carry C0.Thus the sum and carry from

the any stage can be calculated with out waiting for thecarry to ripple through all the previous stages.

The disadvantage of the carry-look-ahead is that the look

ahead carry logic is not simple.it gets completed for more

than 4 bits. For that reason carry look ahead adders areusually implemented as 4-bit modules and are used in a

hierarchical structure to realize adders that have multiple

of 4 bits.

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Design of 4-bit CLA

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Design of 4-bit CLA

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16 bit carry-look ahead adder


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Carry select adder

The Carry select adder generally consists of two Ripple CarryAdder and one multiplexer. Adding two n-bit numbers with a

Carry select adder is done with two adders (therefore 2 Ripple

Carry Adder) in order to perform the calculation twice, one time

with the assumption of the carry being zero and the other being

one. After the two results are calculated the correct sum, as well

as the correct carry is then selected with the multiplexer, which

is usually controlled by the carry from the previous Ripple carry

adder. multiplexers are used to select the correct one of both

precalculated partial sums. Also, the resulting carry-out isselected and propagated to the next carry-select block.

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http://en.wikipedia.org/wiki/Adder_(electronics)http://en.wikipedia.org/wiki/Adder_(electronics)http://en.wikipedia.org/wiki/MUXhttp://en.wikipedia.org/wiki/MUXhttp://en.wikipedia.org/wiki/Adder_(electronics)http://en.wikipedia.org/wiki/Adder_(electronics)


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4 bit Carry select adder

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2 bit Carry select adder

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P it t


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Parity generator Binary information is normally handle by a digital system in a group of bits called

words. A word always contains either an even or an odd number of ones. A parity

bit is attached to the group of information bits in order to make the total number of

1s even or always odd. An even parity bit makes the total number of ones even, and

an odd parity bit makes total odd.

The parity bit is attached to the at either

beginning or at the end of the code.

note that total number of 1s,including

the parity bit,is always even for even

parity and always odd for odd parity.

Table : 8421 BCD code with parity bits.

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Even

parity

Odd

parity

P 8421 P 8421

0 0000 1 0000

1 0001 0 0001

1 0010 0 0010

0 0011 1 0011

1 0100 0 0100

0 0101 1 0101

0 0110 1 0110

1 0111 0 0111

1 1000 0 1000

0 1001 0 1001


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Parity bits and parity checking

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Parity generator/checker

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Parity checking

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Three bit odd parity generator

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3-bit even parity generator

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Digital Comparators

Digital or Binary Comparators are made up from standard AND, NOR and

NOT gates that compare the digital signals at their input terminals andproduces an output depending upon the condition of the inputs. For

example, whether input A is greater than, smaller than or equal to input B

etc.

Digital Comparators can compare a variable or unknown number for

example A (A1, A2, A3, .... An, etc) against that of a constant or knownvalue such as B (B1, B2, B3, .... Bn, etc) and produce an output depending

upon the result. For example, a comparator of 1-bit, (A and B) would

produce the following three output conditions.

A>B; A


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Equality Comparator

XNOR

X

Y

Z

Z = not(x y)

X Y Z

0 0 1

0 1 0

1 0 0

1 1 1

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4-Bit Equality Comparator

A 0

A 1

A 2

A 3

B 0

B 1

B 2

B 3

A _ E Q _

C 0

C 1

C 3

C 2

FIELD A = [A0..3];

FIELD B = [B0..3];

FIELD C = [C0..3];

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One bit comparator

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You may notice two distinct features about the comparator from the above truth table.

Firstly, the circuit does not distinguish between either two "0" or two "1"'s as an output A =

B is produced when they are both equal, either A = B = "0" or A = B = "1". Secondly, the

output condition for A = B resembles that of a commonly available logic gate, the

Exclusive-NOR or Ex-NOR gate giving Q = A B


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Magnitude comparator

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Magnitude comparator

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Four bit Magnitude comparator

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Design Approaches

The truth table 22n

entries - too cumbersome for large n

use inherent regularity of the problem reduce design

efforts reduce human errors



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The Binary Multiplication

x

+

Partial products

Multiplicand

Multiplier

Result

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 1


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4*4 Array Multiplier X3 X2 X1 X0 Multiplicand

Y3 Y2 Y1 Y0 Multiplier

X3Y0 X2Y0 X1Y0 X0Y0 Partial product 0

X3Y1 X2Y1 X1Y1 X0Y1 Partial Product 1

C12 C11 C10 1st row of carries

C13 S13 S12 S11 S10 1st

row of sums X3Y2 X2Y2 X1Y2 X0Y2 partial product 2

C22 C21 C20 2nd row of carries

C23 S23 S22 S21 S20 2nd row of sums

X3Y3 X2Y3 X1Y3 X0Y3 partial product 3

C32 C31 C30 3rd row of carries

C33 S33 S32 S31 S30 3rd row of sums

P7 P6 P5 P4 P3 P2 P1 P0 Final Product

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4*4 Array Multiplier X3 X2 X1 X0 Multiplicand

Y3 Y2 Y1 Y0 Multiplier

X3Y0 X2Y0 X1Y0 X0Y0 Partial product 0

X3Y1 X2Y1 X1Y1 X0Y1 Partial Product 1

C12 C11 C10 1st row of carries

C13 S13 S12 S11 S10 1st

row of sums X3Y2 X2Y2 X1Y2 X0Y2 partial product 2

C22 C21 C20 2nd row of carries

C23 S23 S22 S21 S20 2nd row of sums

X3Y3 X2Y3 X1Y3 X0Y3 partial product 3

C32 C31 C30 3rd row of carries

C33 S33 S32 S31 S30 3rd row of sums

P7 P6 P5 P4 P3 P2 P1 P0 Final Product

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4*4 Array Multiplier

Y0

Y1

X3

X2

X1

X0

X3

HA

X2

FA

X1

FA

X0

HA

Y2X3

FA

X2

FA

X1

FA

X0

HA

Z1

Z3Z6Z7 Z5 Z4

Y3X3

FA

X2

FA

X1

FA

X0

HA

Z2

Z0


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4*4 Array Multiplier

The 4*4 array multiplier requires 16 AND gates, 8 full

adders, and 4 half adders.

In array multiplier the propagation delay is more.

If tad is the worst case delay through an adder,and tg is the

longest AND gate delay then the worst case to complete

the multiplication is 8ad+t8.

In general,an n-bit by n-bit array multiplier requires n*n

AND gates, n(n-2) full adders and n-half adders.

For an nXn array multiplier, the longest path from input to

output goes through 2n adders, and the corresponding

worst-case multiply time is 2ntad + t8.

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Design of a Binary Multiplier

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Binary multiplication requires only shifting and adding. For example,multiplication 1310 by 0510 in binary:

Multiplicand 1 1 0 1 (13)

Multiplier 0 1 0 1 (05)

Partial Product 1 1 0 1

0 0 0 00 1 1 0 1

1 1 0 1

1 0 0 0 0 0 1

0 0 0 0

0 1 0 0 0 0 0 1 (65)

Note that each partial product is either the multiplicand (1101) shifted over by

the appropriate number of places or zero.

Multiplication of two 4-bit numbers requires a 4-bit multiplicand register, a 4-

bit multiplier register, a 4-bit full adder, and an 8-bit register for the product


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Block diagram of Binary Multiplier

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Operation of multiplier

Multiplication Steps:Initial contents of product register 0 0 0 0 0 0 1 0 1 M (5)

(add multiplicand since M=1) 1 1 0 1

after addition 0 1 1 0 1 0 1 0 1

after shift 0 0 1 1 0 1 0 1 0M

(skip addition since M=0) 0 0 0 0after addition 0 0 1 1 0 1 0 1 0

after shift 0 0 0 1 1 0 1 0 1M

(add multiplicand since M = 1) 1 1 0 1

after addition 1 0 0 0 0 0 1 0 1

after shift 0 1 0 0 0 0 0 1 0

(skip addition since M=0)after shift (final answer) 0 0 1 0 0 0 0 0 1

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