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242 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 2, MARCH 2000

A Comprehensive Study of Neutral-PointVoltage Balancing Problem in Three-Level

Neutral-Point-Clamped Voltage Source PWM

InvertersNikola Celanovic, Student Member, IEEE,and Dushan Boroyevich, Member, IEEE

AbstractThis paper explores the fundamental limitations ofneutral-point voltage balancing problem for different loading con-ditions of three-level voltage source inverters. A new model in DQcoordinateframe utilizing current switching functions is developedas a means to investigate theoretical limitations and to offer a moreintuitive insight into the problem. The low-frequency ripple of theneutral point caused by certain loading conditions is reported andquantified.

Index TermsNeutral-point voltage balancing, space vectormodulation, three-level converter.

I. INTRODUCTION

SINCE its introduction in 1981 [1], the three-level neutral-

point-clamped (NPC) voltage source inverter (VSI), Fig. 1,

has been shown to provide significant advantages over the con-

ventional two-level VSI for high-power applications.

The main advantages are as follows.

1) Voltage across the switches is only half the dc bus voltage.

This feature effectively doubles the power rating of VSIs

for a given power semiconductor device. Moreover, thisis achieved without additional, often cumbersome, hard-

ware for voltage and current sharing.

2) The first group of voltage harmonics is centered around

twice the switching frequency [1], [7]. This feature en-

ables further reduction in size, weight, and cost of passive

components while at the same time improving the quality

of output waveforms.

On the other hand this topology also has its disadvantages.

1) Three-level VSIs require a high number of devices.

2) The complexity of the controller is significantly in-

creased.

3) The balance of the neutral-point has to be assured.

The three-level VSI was first considered with respect to high-capacity high-performance ac drive applications [1]. To this day,

it remains the area where this topology is most widely used

[2][4], [7][9], [15],and[16]. Other interesting applications of

Manuscript received March 10, 1999; revised September 22, 1999. Recom-mended by Associate Editor, F. Z. Peng.

The authors are with the Department of Electrical and Computer Engi-neering, Virginia Polytechnic Institute and State University, Blacksburg, VA,24061-0111 USA.

Publisher Item Identifier S 0885-8993(00)02327-9.

Fig. 1. Circuit schematic of a three-level VSI.

this technology include static VAR compensation systems [11],

[12], HVDC transmission systems [18], active filtering applica-

tions, as well as applications in power conditioning systems for

superconductive magnetic energy storage (SMES) [13].

The neutral-point (NP) voltage balancing problem of

three-level NPC VSIs has been widely recognized in litera-ture. Various strategies have been presented, and successful

operation has been demonstrated with a dc-link voltage balance

maintained. In addition, some of the proposed algorithms avoid

the narrow pulse problem [5], [9], minimize losses by not

switching the highest current [10], or share the balancing task

with front-end converters as in [2].

NP control for the carrier-based PWM has been studied

in [15][17]. In [15], the switching frequency optimal PWM

method is introduced. This method controls the NP by, essen-

tially, adding the zero sequence voltage to the inverter output.

This work was extended in [16], where the authors propose an

analytical method for analysis of the NP potential variation,

show some limitations of the NP control, and also deal with thedc-link capacitors design issues. In [17], the authors analyze

the stability of the NP control based on an insightful dynamic

model of the NP control they developed.

This paper discusses the issues of NP control from the space

vector modulation (SVM) point of view. In addition, the broader

range of inverter operating conditions is addressed, and a new

mathematical formulation of NP balancing problem is given.

Furthermore, low-frequency NP voltage ripple, normalized with

the output current and the size of the dc-link capacitors, is given

for all operating conditions.

0885-8993/00$10.00 2000 IEEE

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CELAN OVIC AND BOROYEVICH: COMPREHENSI VE STUDY OF NEUTRA L-POINT VOLTAGE BALANCING PROBLEM 243

II. PRINCIPLE OFOPERATION

All available voltage space vectors for three-level VSIs are

shown in Fig. 2. These vectors, called switching-state vectors,

represent inverter output line voltages in two-dimensional ( ,

, ) plane, and are produced by switching different states

of the inverter, also shown in Fig. 2. Each phase , or can

be connected to either the positive ( ), negative ( ), or neutral

( ) point of the dc link. Shown in Fig. 2, switching state pon,

for example, is producing line voltages and

. In this case, the phase output is connected to the

neutral point, which results in the current disturbing the NP

voltage balance.

Not all the vectors affect the NP balance. The ones that do are

summarized in Table I. Large vectors do not affect the NP bal-

ance because they connect the phase currents to either the posi-

tive or negative dc rail, and the NP remains unaffected. Medium

vectors connect one of the phase currents to the NP making the

NP potential dependent in part on the loading conditions. They

are the most important source of the NP potential unbalance.

Small vectors come in pairs. Each vector in a pair generatesthe same line-to-line voltages. A small vector that connects a

phase current to NP point without changing the sign of the cur-

rent will be referred to as a positive small vector. The other

one, connecting the phase current with the negative sign, will be

called a negative small vector. The majority of the NP voltage

balancing schemes used in SVM relies on some form of manip-

ulation of small vectors in a pair, where the relative duration of

positive and negative small vectors in a pair is usually adjusted

in order to compensate for the error in NP.

III. NEUTRALPOINTCURRENTMODULATION

Generally, the task of three-level VSIs is to synthesize the

desired output phase voltages , , , represented by the ref-

erence voltage space vector

(1)

where the modulation index is the ratio between the desired

amplitude of the output phase voltages, , and the maximum

possible amplitude of undistorted sinusoidal phase voltages that

can be generated, . In this paper, only the case

will be considered. Due to circular symmetry of the three-phase

system, it is sufficient to consider only the case , asshown in Fig. 3. The reference vector may be synthesized using

the space vector modulation (SVM) of the three switching state

vectors that are nearest to the reference vector at every sampling

instant. The nearest three vectors are selected by locating the

reference vector in one of the four small triangles illustrated in

Fig. 3.

For the outer small triangle shaded in Fig. 3, the reference

vector is synthesized as

(2)

(3)

Fig. 2. Switching state vectors of three-level VSI.

TABLE INEUTRAL POINT CURRENT FOR

DIFFERENTSPACEVECTORS

Fig. 3. Synthesis of in outer small triangle region.

where

duty cycle of the small switching state vector;

duty cycle of the medium switching state vector;duty cycle of the large switching state vector.

From (2) and (3), the duty cycles are

(4)

(5)

(6)

The NP current in outer small triangle has two components,

the noncontrollable component from the medium vector, and the

controllable component from the small vectors. The controllable

component of the NP current can be selected by adjusting the

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CELAN OVIC AND BOROYEVICH: COMPREHENSI VE STUDY OF NEUTRA L-POINT VOLTAGE BALANCING PROBLEM 245

Fig. 6. Duty cycles of SVM for modulation index .

TABLE IICURRENTSWITCHINGFUNCTION FORMEDIUMVECTORS

By extending this reasoning to small vectors and all six

sectors a set of current switching functions can be defined for

small vectors as well. Small vectors switching functions are

shown in Tables III and IV. Finally, all these pieces can be com-

bined into a single expression valid for the NP current over the

entire line cycle

(20)

In order to simplify the analysis of the NP current under dif-

ferent loading conditions, it is convenient to transform (20) into

TABLE IIICURRENTSWITCHINGFUNCTION FOR SMALLVECTORS

TABLE IVCURRENTSWITCHINGFUNCTION FOR SMALLVECTORS

a synchronously rotating, , reference frame. This can by

done by transforming the phase currents

(21)

where the -axis is aligned with the voltage reference vector,

. In a steady state, and are constant and represent

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246 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 2, MARCH 2000

Fig. 7. Weighing factors for medium vectors for .

active and reactive components of the load current, respectively.

By substituting (21) into (20), the NP current can be expressed

as

(22)

where

, and so on.

Note that (22) is essentially the composite expression com-bining (7), (13), and (18) into one matrix equation valid over

the full line cycle of the output voltage. The NP current in this

formulation still consists of noncontrollable current produced

by the application of the medium vector, and the controllable

current produced by the small vectors.

NP current, resulting from application of medium vectors,

can be found by multiplying the direct current by the direct

weighing factor , and the quadrature current , by the

quadrature weighing factor. These factors are given in Fig. 7,

for the case when the modulation index . It is apparent

that quadrature component of the current will be weighed much

more heavily, and will produce much larger low-frequency (LF)

ripple than the direct component current.Similarly, NP current resulting from application of small vec-

tors depends on controllable direct and quadrature weighing

factors multiplying the direct, , and quadrature, , load cur-

rent. These factors are given in Fig. 8 for .

These four weighing factors depend not only on small vec-

tors duty cycles and the current switching functions that are de-

termined by particular type of SVM used, but also on the con-

trol inputs and as defined earlier. Two distinct sets of

weighing factors are given in Fig. 8. One set of weighing factors

when only positive small vectors are used (i.e.,

) is indicated by a solid line. The other set of weighing factors

when only negative small vectors are used (i.e.,

) is indicated by a dashed line. Between these two extreme

cases the weighing factors can be controlled by adjusting cur-

rent modulation indexes.

The weighing factors for medium vectors are periodic func-

tions with zero average value over a line cycle. This means that

in the ideal steady-state case, and currents are constant and

the NP current from medium vectors naturally balances over a

line cycle. Finding the size of the LF ripple under these con-

ditions will be used to help determine the size of the dc-link

capacitor for a given NP voltage ripple.

Note that the ratio of active and reactive weighing factors is

opposite for medium and small vectors. Large means large

control authority over the NP current through the manipula-tion of current modulation indexes of small vectors, and small

means small disturbance from middle vectors. On the other

hand, large means large disturbance from middle vectors, and

small means small control authority over NP from small vec-

tors. This confirms the fact that it is much easier to suppress the

LF ripple in the NP when the load has a high power factor.

V. NP BALANCECONTROL

There seems to be equivalence in the NP balance control

mechanism between carrier-based, and SVM-based PWM

schemes. For carrier-based PWM modulation, all the control

schemes appear to be based on the same concept: they all usesome form of manipulation of output zero sequence voltage.

Similarly, all the NP control schemes for SVM-based PWM

schemes appear to use some form of manipulation of the

redundant small vectors. Note that the difference between the

phase voltages of two small vectors in a pair is, in fact, the zero

sequence voltage. This seems to be another proof of the duality

of the two PWM methods.

Regarding NP balancing control for SVM, and with the re-

striction to NTV, three distinctive approaches to the control of

NP might be as follows.

1) Passive control, where the positive and negative small

vector is selected alternatively in each new switching

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CELAN OVIC AND BOROYEVICH: COMPREHENSI VE STUDY OF NEUTRA L-POINT VOLTAGE BALANCING PROBLEM 247

Fig. 8. Weighing factors for small vectors for .

cycle. This method can work only in the case of perfectly

balanced load and perfectly balanced PWM scheme,

which is unlikely to happen in practice. This method

would have difficulties to recover from line or load

transients [15]. Still, this control method can be used

to establish a benchmark for NP controller performance.

This benchmark can then be used to evaluate the perfor-

mance of other NP control methods.

2) Hysteresis type control is perhaps the simplest and most

popular closed loop NP control scheme. This method

requires the knowledge of the current direction in each

phase. Based on that information, the small vectors thatwill move the NP voltage in the direction opposite from

the direction of unbalance can be selected. The downside

of this method is the current ripple at half the switching

frequency.

3) Active control schemes that control the current modula-

tion indexes m and m . In general, these schemes re-

quire measurement of the voltage unbalance in the NP,

and often require measurement of the amplitudes of the

phase currents as well. The benefits of these schemes

is that they do not have the ripple at half the switching

frequency, and some variations of these control schemes

can balance the NP exactly. Unfortunately, they all in-

Fig. 9. Region where LF ripple can be suppressed.

crease the switching losses due to introduction of addi-

tional switching states, and may be less robust than the

hysteresis type control schemes.

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248 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 2, MARCH 2000

Fig. 10. Normalized amplitude of the LF charge ripple.

Fig. 11. Capacitor sizes for specified NP ripple with and without NP control.

From the analysis in the previous section, it should be ob-

vious that, regardless of control scheme, the control authority

over the NP current is limited, and the region where exact bal-

ancing can be achieved in each switching cycle must exist. This

region is given as a shaded area in Fig. 9. Note that the graph is

symmetrical, and that the unity power factor load represents the

most favorable case. For that case, the NP voltage can be bal-

anced in every switching cycle for a modulation index as high

as .If the converter happens to operate outside the shaded region,

LF ripple current flows into the NP, producing LF voltage ripple

in the NP. The size of that ripple is determined mostly by the size

of the dc-link capacitors, amplitude of the phase currents, and

the output power factor.

Peak-to-peak value of low frequency charge ripple in the NP

divided by the amplitude of output phase current is given in

Fig. 10. The first graph shows the normalized NP charge ripple

for the passive control of NP voltage balance. The second graph

shows the best that can be done using hysteretic and/or control

of current modulation indexes. The shaded region represents the

same ripple-free area as the one given in Fig. 9.

The size of the dc-link capacitors required for given

NP voltage ripple and the amplitude of the phase cur-

rent can be computed from (22). The essential param-

eter in this computation is the normalized charge ripple,

given in Fig. 10, for every

modulation index , and load power factor

(23)

This should provide sufficient guidelines to size the dc linkcapacitors for any expected operation mode and desired neutral

point voltage ripple value.

Consider an example with 1800 V dc-link voltage and

A, peak phase current, and allow 1% voltage ripple

( V) in the NP. For modulation index ,

the comparison of capacitor sizes for the feedback NP control

and the case with passive NP control is summarized in Fig. 11.

The greatest savings in the size of capacitor can be achieved

when the inverter is predominantly supplying active power,

while for the operation with purely reactive power the benefits

of feedback NP control diminish.

VI. CONCLUSION

In this paper, NP balancing was investigated for all possible

operating conditions of a three-level VSI. A new and general

model in the DQ coordinate frame was introduced as a way to

investigate the theoretical and practical limitations of NP bal-

ancing problem regardless of the type of SVM used. Addition-

ally, the low-frequency ripple of the neutral point voltage caused

by all possible loading conditions was reported and quantified.

Results presented in this study should clarify the tradeoffs be-

tween the size of the dc-link capacitor, size of the NP voltage

ripple, and the NP balancing method.

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CELAN OVIC AND BOROYEVICH: COMPREHENSI VE STUDY OF NEUTRA L-POINT VOLTAGE BALANCING PROBLEM 249

Based on the investigations reported in this paper and the re-

sults reported by other researchers, it can be concluded that the

NP balancing problem in three-level NPC VSI topology does

not limit the usefulness of this topology for practical applica-

tions. This problem can be solved in a satisfactory way using

various techniques, depending on the particular system, and its

operating point constraints.

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Nikola Celanovic (S95) received the B.S. degreein electrical engineering from the University ofNovi Sad, Yugoslavia, in 1994, the M.S. degree inmechanical engineering from Vanderbilt University,Nashville, TN, in 1996, and is currently pursuingthe Ph.D. degree at the Virginia Polytechnic Instituteand State University (Virginia Tech), Blacksburg.

He is a Graduate Research Assistant with theCenter for Power Electronics Systems, VirginiaTech. During the summer of 1999, he was a summerintern with the General Electric CR&D Center,

Schenectady, NY, where he was working on modeling and control of multilevel

three-phase drive systems. His research interests include modeling, controldesign, and applications of high-power, high-frequency power electronicssystems.

Dushan Boroyevich (M99) receivedthe B.S. degreefromthe Universityof Belgrade, Yugoslavia, in 1976,the M.S. degree from the University of Novi Sad, Yu-goslavia, in 1982, and the Ph.D. degree from the Vir-ginia Polytechnic Institute and State University (Vir-ginia Tech), Blacksburg, in 1986.

From 1986 to 1990, he was an Assistant Professorand Director of the Power and Industrial ElectronicsResearch Program, Institute for Power and Elec-tronic Engineering, University of Novi Sad, andlater, Acting Head of the Institute. In 1990, he joined

the Bradley Department of Electrical and Computer Engineering, VirginiaTech, as an Associate Professor. From 1996 to 1998, he was an AssociateDirector with the Virginia Power Electronics Center, and since 1998, hasbeen the Deputy Director of the NSF Engineering Research Center for PowerElectronics Systems, where he is now a Full Professor. His research interestsinclude multiphase power conversion, high-power PWM converters, modelingand control of power converters, applied digital control, and electrical drives.He has published over 100 technical papers, has three patents, and has beeninvolved in numerous government and industry-sponsored projects in the areasof power and industrial electronics.

Dr. Boroyevich is a member of the IEEE Power Electronics Society AdCom,IEEE Industry Applications Society Industrial Power Converter Committees,and Phi Kappa Phi.