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DUAL PORT STATIC R MTESTINGMANUEL J RAPOSASun Microsystems Inc

Mountain View, CA 94043ABSTRACT

The introduction of Dual-Port S tatic RAMs(DPSRAM) has meant solutions for designers of multipleprocessor systems, and confusion for the engineerswho are required to implement component level test.This paper will show the basics of that test methodologywhich has been approved by Integrated Device Tech-nology, the leading manufacturer of Dual-Port StaticRAMs.

DUAL-PORT BASICSJust what is a Dual-Port?

A Dual-Port Static RAM is actually a singlememory array with two wholly independent sets of inter-face log ic (Figure A). Dup licate sets of address inputs,control lines, and I/Os, are both capable of accessingthe same memory cell simultaneously, yet separately.This allows for truly asynchronous opera tion of this de-vice by two completely unrelated processors or sys-tems.

One of the m ost common tasks performed bythe DPSRAM is message passing. The ability of thisdevice to be operated by two non-compatible systemsmakes it the ideal interface to pass data or messages.A function of this data transfer is the ability of either portto alert the opposing port of a pending message. Thisfeature has been implemented in some Dual-Portsthrough the use of an interrupt flag (ANT), triggered bywriting to a specific memory cell in the array.

When not used for message passing, the de-vice can be utilized unrestricted by either port, whichleads to the possibility of both ports addressing thesame cell. Should either of the ports be in a write

mode, this state of contention must somehow be re-solved, with access granted to only one port. This arbi-tration can be implemented through software, orthrough the hardware features of a busy flag (/BSY),and semaphore flags (/SEM).

Difficult to test.With little more than this background nforma-

tion and a data sheet, the test engineer must now de-velop a test strategy for this device. The strategy itselfis not nearly as difficult to define as it is to implement.A standard Dual-Port has twice as many address, dataand control lines as a typical SRAM of equal size. Thearbitration and interrupt circuitry must be tested, and allthe normal DC and AC tests must be perfo rmed oneach port.

The fundamental problem in testing Dual-Port Static RAMs is how to address the entire arrayfrom both sides individually. Any memory tester withdual pattern ge nerators and dual timing systems wouldsuffice, but most existing memory testers were de-signed and built before DPSRAMs were introduced,and offer no such solution. Therefore, the followingthree methods have been proposed, and the advan-tages and disadvantages of each will be explored.

1. Same address, b oth ports.Tie the address lines from both ports to-gether so that Xn drives both LXn and RXn. (L=leftport, R=right port) With this method, both ports receivethe same address.

2. Complement address.Combine the above method with inverteddrivers so that LXn = Xn, while RXn = /Xn. Using thismethod, the right port address is always the comple-ment of the left port address.

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/LI\ ROW2K x 8MEMORYARRAY w SELECT

ARBITRATIONLOGIC

1

Figure A: Dual-Port Static R A M block diagram.

3. X Y Separation of ports.Assign XO thru Xn to the Left port A0 thruAn. Assign YO thru Yn to the Right port A0 thru An.(Figure B.) This method will provide independent ad-dressing.

Same address, both ports.This is a ccomplished by tying correspondingaddress lines together on the loadboard . The advan-tages of this scheme are readily apparent. This sim-plistic approach is easily implemented without requiringextensive hardware, but the disadvantages are equallyobvious. Although the ports can opera te indepen dentlywith selective enabling, they cannot be tested simulta-neously. Enabling both ports will force the dev ice intoaddress contention.

TEST HEAD

P0RT

Figure B: X / Y Separation of Ports.

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Complement address.This approach can be implemented either byman ipulat ing the address formatters, or with the addi-tion of inverters on the loadboard. The advantagesagain include simplicity, and the fact that the two portswill never be in contention. This is also a disadvantagethough, as it becomes impossible to test the arbitrationcircuits. Complementing with inverters will certain lycause an unacceptable timing delay and reduce theaccuracy of any measurements.

X Y Separation of ports.This design uses the X address drivers tomanipulate the left port, and the Y address drivers tomanipulate the right port. It requires the tester to havetwice as many VOs as the device, and at least 6 clockdrivers. The advantage of this combination is totallyindepende nt addressing of ports. The disadvantagesappear when writing topologically correct patterns, andas a requirement for address format control to ade-quately perform co ntention testing.

It is apparent that iY separation of ports isthe most logical solution. The pattern issue is solvedthrough software, and the format control is handled withtester hardware. Plus, independent port acces s allowssimultaneous AC testing of both ports.TESTING A DUAL-PORTSo how is it done?

By not distinguishing between rows and col-umns, we are misleading the tester with regard to thearray configuration. For example, a 2K array may have32 rows and 64 columns, bu t by combining all of therow and column address and assigning them to thetester X drivers, we are telling the tester that there are2 48 rows in a single column. This eliminates the use-fulness of any standa rd pattern library. In fact, usingthis addressing scheme with a standard pattern, thetester would be expecting a 4 Meg array. New algo-rithms must be designed to produce the desired topo-logical effect.

Figure C shows a standard Checkerboardpattern in an array, and Figure D shows how that samepattern must be visualized and implemented to achievethe desired results.

Another thing to consider when writing thesepatterns, is the AC testing of both ports simultaneously.With a March pattern for instance, the left port may be-gin writing at the top of the array, incrementing ts waydown. At the same time, the right port can beg in writ-ing opposite data a t the bottom of the array and decre-ment its way up. By keeping this a one to one relation-ship, the even number of cells in the array will naturallyavoid any contention.

0 i l ; O ; l

1 : 0 : 1 : 0

o j 1 ; 0 : 1

Figur e C: Stand ardCheckerboard Pattern

Figur e D: Dual-Port Static RamCheckerb oard Pattern

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Care must be taken at the crossover point,which occurs in the exact center of the array. At thispoint, each port must switch from writing data toread opposite data, write data , continuing this to theend of the array. At that point, each port repeats thesequence in the reverse direction writing opposite data.At the conc lusion, each po rt will have marche d both 1 sand 0 s through the entire array, although not in theclassic sequence.

This technique of simultaneous testing canbe applied to any pattern.

Jntempt testing.Interrupt testing is performed by writing datato the interrupt location while monitoring the ANT outpu t

of the opposing port. If the test system has sufficientcomparators, one can be dedicated to the ANT output.Otherwise, a comparator may have to be sw itched froma data output to the ANT output. This can be accom -plished with relays or FET switches on the loadboard.

Arbitration testingAArbitration circuitry has taken on two majorforms. First, contention circuitry which continuouslymonitors the address applied to both ports, activating abusy output (/BSY) when they match, and second,semaphore flags.

STEP1.2.3.4.5.6.789.10.

SemaDhore testing.Semaphores are simply a set of latcheswhich can be accesse d by either port. Once a sema-

phore has been requested, and granted, it can only bereleased by the port it has been granted to. Normallythere are m ultiple semaphores available, and they ca nbe used for any purpose. While they are not physicallytied to the memory array, they may utilize the samedata and address lines. The simplest method of testingsemaphore flags are to request, verify, and releaseevery latch. A typical test sequence for 8 semaphoreflags is outlined in Table 1.

Contention testinp.Contention testing is by far the most difficultelement of Dual-Port testing to perform. t requires a

great deal of forethought and planning, and a firsthandknowledge of the hardware. In order to corre ctly testcontention, we must first understand and then visualizethe completed test. Only then can we develop an algo-rithm to implement it.

A state of con tention arises when bo th portsattempt to address the same cell simultaneously. Thecontention circuitry will arbitrate between the two ports,granting write access to the winner, and read only ac-cess to the loser. This arbitration is decided solely onthe signal timing relationship, with the won / loss statusbeing displayed by the busy flags (IBSY).

TABLE 1: Semaphore flag test sequenceLeft Port Right Port

Release all semaphores (0..7)Request all even semaphores (0,2,4,6)Verify even semaphores grantedRequest all odd semaphoresVerify odd semaphores not grantedVerify even semaphores unchangedRelease all even semaphoresVerify even semaphores were releasedVerify odd semaphores were grantedRepeat steps 1-9 for odd semaphores

Release all semaphores (7..0)Request all odd semaphores (7,5,3,1)Verify odd semaphores grantedRequest all even semaphoresVerify even semaphores not grantedVerify odd semaphores unchangedRelease all odd semaphoresVerify odd semaphores were releasedVerify even semaphores were grantedRepeat steps 1-9 for even semaphores

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If we use the IDT7132 as an example, thedata sheet states that in order for a port to be guaran-teed access to a cell, its address m ust arrive at least 5nanoseconds prior to being addressed by the oppositeport. This is spec ified as the Arbitration Priority Set UpTime (Taps). In other words, if we want to test thiscircuitry, we must be certain that the address applied toone port is stable for at least 5 nanoseconds before theopposing address arrives.

Xaddress

When the test system has separate timinggenerators for the X and the Y address drivers, then wecan simply speci fy different timing for each . If however,there is a single timing generator for all address drivers,(as is the case with most existing memory test sys-tems), we must be more clever in our approach.

N-l X x N

Bas ically what we must do is to apply thesame signal at the same time to both ports, and have

Yaddress

TEST FOR NON-CONTENTION, COMX, HOLDYIGNORE ERRORS COMX, INCYTEST FOR CONTENTION INCX HOLDY

I IN l x x N

This pattern is designed for use with the Yaddress complementor disabled, and will allow that portaddressed by the Y drivers to win the arbitration. Thepattern is initiated with the X address at 0 and the Yaddress at N (address max). The pattern to test for theX drivers to win contention is identical except that theaddress states are switched, with the X complementordisabled.

Xaddress

Sample waveforms resulting from this combi-nation of pattern, format, and timing are displayed inFigure F.

N l x N

DC testing.

Yaddress

DC testing is very much the same forDPSRAMs as it is for standard SRAMs. One areawhere differences do occur is standby current (Isb).With two ports, and each port at one of two possiblelevels (CMOS vs. TTL), 4 possibilities must be testedfor. See Table 2 for the conditions of each.

one arrive before the other. This can be accomplishedby using both the single timing generator, and the ad-dress formatters. Suppose we specify the timing asfollows: Period length 60nSAddress start 1OnSAddress stop 15nS

N l i: N

Both ports enabledIf in conjunction with this, we specify an address formatof XYBAR, XY (inverted address followed by true ad-dress) we will get signals such as those in Figure E (1).Ifwe now disable the Y complementor, we modify thosesignals to match those in Figure E (2). The effect, asyou can see, is that of one signal arriving 5nanoseconds before the other.

Now that we can achieve the timing required,we must turn our attention to the sequence. This is atwo step process, forcing the condition that one portwins, then the other, and is easiest performed by writ-ing separate patterns for left port and right port conten-tion. Once contention has been tested for, it must beremo ved, and the /BSY flag under test verified to havereturned to an inactive state. Once again, additionalcomparators are used, or switched into place to moni-tor the /BSY output.

The pattern used must increment througheach ce ll in the array, testing for both the active, andinactiv e state of the /BSY flag. The following 3 steppattern does just that, using step 2 as an ignore cycleto reconcile X and Y for the following step.

OnS lOnS 15nSI I I 60nSI

Figure E. Combination effect of timing format.

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TABLE 2: STANDBY CURRENT (Isb) CONDITIONSSYMBOLIsbl

lsb2

lsb3

lsb4

CYCLE

Right ort

PARAMETERStandby CurrentBoth ports TTL level inputsStandby CurrentOne port TTL level inputs

Full Standby CurrentBoth ports all CMOS leve l inputsFull Standby CurrentOne port all CMOS level inputs

TEST CONDITION/CEL and /CER Vih

/CEL and /CER VihActive port outputs openF = Fmax/CEL and /CER Vcc 0.2VVin Vcc 0.2V or Vin 0.2VOne port /CE 2 Vcc 0.2VVin 2 Vcc - 0.2V or Vin 5 0.2VActive port outputs openF = Fmax

address

SYexpected)

Strobe

Ay - 1iII II Ii

I II II II II I

I II I

III 1IIiII I

I II I INACTIVEI II II II II II II II II II I

I II II II I* AC T IV lI II II II II II II II II I

I I A x = AyI INON LINEAR SCALE

Figure F. Content ion test resultant waveforms

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TESTER REOUIREMENTSWhat is needed?

In order to successfully employ the X/YSeparation, the memory test system used must havesufficient address pins. In the case of a 2K x 8DPSRAM, each port has 11 address inputs, and there-fore requires the tester to have at least 22 address driv-ers (1 X , 11Y). The data pins on each port necessi-tates a minimum of 16 tester I/O pins, with either 4 addi-tional comparators, or the ability to switch relaysneeded in order to test /BSY and ANT. At least oneparametric measurement unit (PMU) must be used toperform the DC tests.

Performance of the AC tests requires a pa t-tern generator capable of complex algorithms, sometype of address format control, and a minimum timingpulse width less than or equal to Taps. Six clo ck pulsegenerators are required to isolate the chip enable(/CE), write enable (/WE), and output enable (/OE)functions of each port.

CONCLUSIONWhat has been described is a successful

way of correctly testing Dual-Port S tatic RAMS. How-ever, posse ssion of this information alone does notmake it an easy task. Loadboard design, software cod-ing, debugging, and understanding the process are alltime consuming and difficult . But with the above infor-mation, these difficulties can all be overcome.

ACKNOWLEDGMENTSI would like to acknowledge Dave Barta forhis work developing this methodology, and I would like

to thank Chris Schott alid Jeff Vesey for their assis-tance in preparing this manuscript.

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