00/00/2008 00/00/2008 1 Tunnel dielectric Trapping layer Blocking layer Gate material SiO 2 (nitrided ) Si 3 N 4 Al 2 O 3 Ta Standard TANOS Options investigated in GOSSAMER SiO 2 different growth conditions Nitrided SiO 2 different growth conditions BE dielectric (SiO 2 /Si 3 N 4 /HTO or re-ox) Si 3 N 4 different stochiometries HfO 2 different deposition/thermal treatment ZrO 2 different deposition/thermal treatment ZrAlO and ZrSiO nanolaminates LaAlO nanolaminates Al 2 O 3 different deposition/thermal treatment “ “ with SiO 2 buffer layers HfAlO, LaAlO DyScO, GdScO, TbO, TbSCO TiN TaN different deposition TaC technologies TaCN
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00/00/2008 1 Tunnel dielectric Trapping layer Blocking layer Gate material SiO 2 (nitrided) Si 3 N 4 Al 2 O 3 Ta Standard TANOS Options investigated in.
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1
Tunnel dielectric
Trapping layer
Blocking layer
Gate material
SiO2
(nitrided)
Si3N4
Al2O3
Ta
Standard TANOS Options investigated in GOSSAMER
SiO2 different growth conditionsNitrided SiO2 different growth conditionsBE dielectric (SiO2 /Si3N4/HTO or re-ox)
Si3N4 different stochiometriesHfO2 different deposition/thermal treatmentZrO2 different deposition/thermal treatmentZrAlO and ZrSiO nanolaminatesLaAlO nanolaminates
Al2O3 different deposition/thermal treatment “ “ with SiO2 buffer layersHfAlO, LaAlODyScO, GdScO, TbO, TbSCO
TiNTaN different depositionTaC technologiesTaCN
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1Gb TANOS demonstrator
Picture of 1Gbit NAND Charge Trap Flash
Numonyx inserted the Charge Trap cell into a 1Gbit 1.8V NAND device adapting cell pitch at row and column decoders thanks to an advanced copper metallization
The device includes 1.8 billion cells but only 1 G is addressable due to the re-use of an existing cell design.
~40nm
500
Mb
it arra
y
500
Mb
it arra
y
RAM
Schematic layout
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22nm demonstration
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– In Self-Aligned structure, W narrowing increases P/E efficiency– Down to 1x nm node we estimate no significant degradation of P/E windows
Active
Metal gate
Alumina
Oxide
Nitride
19.4nm
4.6nm
BE-Tunnel
24.8nm
BE-Tunnel
Active
Nitride
Alumina
Metal gate Oxide
4Mbit addressable array at 25nm
0
1
2
3
4
5
6
10 20 30 40 50 60Lgate [nm]
P/E
[V
]
W=30nm
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3-D architectures
30nm
25nm
OXIDE
gate
- Effect of floating body channel- Effect of poly-silicon channel- Effect of wrap-around SONOS