· Web viewOne or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog inputs, with conversion times as low as 2.44 μs per channel.

CHAPTER 2

ARM 7 MICROCONTROLLER

2.1 Introduction

The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S

CPU with real-time emulation and embedded trace support, that combines the

microcontroller with embedded high speed flash memory ranging from 32 kB to

512 kB. A 128-bit wide memory interface and a unique accelerator architecture

enable 32-bit code execution at the maximum clock rate. For critical code size

applications, the alternative 16-bit Thumb mode reduces code by more than 30 %

with minimal performance penalty.

Due to their tiny size and low power consumption, LPC2141/2/4/6/8 are ideal for

applications where miniaturization is a key requirement, such as access control and

point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0

Full Speed device, multiple UARTS, SPI, SSP to I2Cs and on-chip SRAM of 8 kB

up to 40 kB, make these devices very well suited for communication gateways and

protocol converters, soft modems, voice recognition and low end imaging,

providing both large buffer size and high processing power. Various 32-bit timers,

single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines

with up to nine edge or level sensitive external interrupt pins make these

microcontrollers particularly suitable for industrial control and medical systems.

2.2 Features

• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

• 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program

memory.128 bit wide interface/accelerator enables high speed 60 MHz operation.

• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader

software.Single flash sector or full chip erase in 400 ms and programming of 256

bytes in 1 ms.

• EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging

with the on-chip RealMonitor software and high speed tracing of instruction

execution.

• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.

In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by

DMA.

• One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total

of 6/14 analog inputs, with conversion times as low as 2.44 μs per channel.

• Single 10-bit D/A converter provides variable analog output.

• Two 32-bit timers/external event counters (with four capture and four compare

channels each), PWM unit (six outputs) and watchdog.

• Low power real-time clock with independent power and dedicated 32 kHz clock

input.

• Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus

(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

• Vectored interrupt controller with configurable priorities and vector addresses.

• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

• Up to nine edge or level sensitive external interrupt pins available.

• 60 MHz maximum CPU clock available from programmable on-chip PLL with

settling time of 100 μs.

• On-chip integrated oscillator operates with an external crystal in range from 1

MHz to 30 MHz and with an external oscillator up to 50 MHz.

• Power saving modes include Idle and Power-down.

• Individual enable/disable of peripheral functions as well as peripheral clock

scaling for additional power optimization.

• Processor wake-up from Power-down mode via external interrupt, USB, Brown-

Out Detect (BOD) or Real-Time Clock (RTC).

• Single power supply chip with Power-On Reset (POR) and BOD circuits:

– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant

I/O pads.

2.3 Architectural overview

The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support,

the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA

Advanced High-performance Bus (AHB) for interface to the interrupt controller,

and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA

Advanced Peripheral Bus) for connection to on-chip peripheral functions. The

LPC2141/24/6/8 configures the ARM7TDMI-S processor in little-endian byte

order.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of

the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB

address space within the AHB address space. LPC2141/2/4/6/8 peripheral

functions (other than the interrupt controller) are connected to the VPB bus.

The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals

are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte

address point. Each VPB peripheral is allocated a 16 kB address space within the

VPB address space.

The connection of on-chip peripherals to device pins is controlled by a Pin Connect

Block. This must be configured by software to fit specific application requirements

for the use of peripheral functions and pins.

2.4 ARM7TDMI-S Processor

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and

related decode mechanism are much simpler than those of microprogrammed

Complex Instruction Set Computers. This simplicity results in a high instruction

throughput and impressive real-time interrupt response from a small and cost-

effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory

systems can operate continuously. Typically, while one instruction is being

executed, its successor is being decoded, and a third instruction is being fetched

from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known

as THUMB, which makes it ideally suited to high-volume applications with

memory restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially,

the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density

of standard ARM code while retaining most of the ARM’s performance advantage

over a traditional 16-bit processor using 16-bit registers. This is possible because

THUMB code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of

the performance of an equivalent ARM processor connected to a 16-bit memory

system.

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S

Datasheet that can be found on official ARM website.

2.5 On-Chip Flash memory system

The LPC2141/2/4/6/8 incorporate a 32 kB, 64 kB, 128 kB, 256 kB, and 512 kB

Flash memory system respectively. This memory may be used for both code and

data storage. Programming of the Flash memory may be accomplished in several

ways: over the serial built-in JTAG interface, using In System Programming (ISP)

and UART0, or by means of In Application Programming (IAP) capabilities. The

application program, using the IAP functions, may also erase and/or program the

Flash while the application is running,allowing a great degree of flexibility for data

storage field firmware upgrades, etc. When the LPC2141/2/4/6/8 on-chip

bootloader is used, 32 kB, 64 kB, 128 kB, 256 kB, and 500 kB of Flash memory is

available for user code.

The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 erase/write

cycles and 20 years of data-retention.

2.6 On-Chip Static RAM (SRAM)

On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-

chip SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2141/2/4/6/8

provide 8/16/32 kB of static RAM respectively.

The LPC2141/2/4/6/8 SRAM is designed to be accessed as a byte-addressed

memory.Word and halfword accesses to the memory ignore the alignment of the

address and access the naturally-aligned value that is addressed (so a memory

access ignores address bits 0 and 1 for word accesses, and ignores bit 0 for

halfword accesses).Therefore valid reads and writes require data accessed as

halfwords to originate from addresses with address line 0 being 0 (addresses

ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal notation) and data accessed as

words to originate from addresses with address lines 0 and 1 being 0 (addresses

ending with 0, 4, 8, and C in hexadecimal notation). This rule applies to both off

and on-chip memory usage.

The SRAM controller incorporates a write-back buffer in order to prevent CPU

stalls during back-to-back writes. The write-back buffer always holds the last data

sent by software to the SRAM. This data is only written to the SRAM when

another write is requested by software (the data is only written to the SRAM when

software does another write). If a chip reset occurs, actual SRAM contents will not

reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does

not reflect the last write operation). Any software that checks SRAM contents after

reset must take this into account. Two identical writes to a location guarantee that

the data will be present after a Reset. Alternatively, a dummy write operation

before entering idle or power-down mode will similarly guarantee that the last

data written will be present in SRAM after a subsequent Reset.

.

2.7 Block Diagram

(1) Pins shared with GPIO.(2) LPCC2144/6/8 only.(3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/8 only.

2.8 Pin Configuration

2.9 Pin Description

Pin description for LPC2141/2/4/6/8 and a brief explanation of corresponding functions are shown in the following table.

Symbol Pin Type Description

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis

and 10 ns slew rate control.

[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis

and 10 ns slew rate control. If configured for an input function, this pad utilizes

built-in glitch filter that blocks pulses shorter than 3 ns.

[3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible

pad. It requires external pull-up to provide an output functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns

slew rate control) and analog input function. If configured for an input function,

this pad utilizes built-in glitch filter that blocks pulses

shorter than 3 ns. When configured as an ADC input, digital section of the pad is

disabled.

[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns

slew rate control) and analog output function. When configured as the DAC

output, digital section of the pad is disabled.

[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions

with TTL levels and hysteresis and 10 ns slew rate control. The pull-up resistor’s

value typically ranges from 60 kΩ to 300 kΩ.

[7] Pad is designed in accordance with the Universal Serial Bus (USB)

specification, revision 2.0 (Full-speed and Low-speed mode only).

[8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis)

function only.

[9] Pad provides special analog functionality.

2.10 General Purpose Input/Output Ports (GPIO)

2.10.1 Features

• Every physical GPIO port is accessible via either the group of registers providing

an enhanced features and accelerated port access or the legacy group of registers

• Accelerated GPIO functions:

– GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged

– All registers are byte and half-word addressable

– Entire port value can be written in one instruction

• Bit-level set and clear registers allow a single instruction set or clear of any

number of bits in one port

• Direction control of individual bits

• All I/O default to inputs after reset

• Backward compatibility with other earlier devices is maintained with legacy

registers appearing at the original addresses on the VPB bus.

2.10.2 Applications

• General purpose I/O

• Driving LEDs, or other indicators

• Controlling off-chip devices

• Sensing digital inputs

2.10.3 Pin Description

Pin Type Description

2.10.4 Register Description

2.11 Applications

• Industrial control

• Medical systems

• Access control

• Point-of-sale

• Communication gateway

• Embedded soft modem

• General purpose applications