Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-1 Arithmetic and CAD Tools CAD tools work great with arithmetic functions Adding,subtracting,multiplying,

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-1

Arithmetic and CAD Tools

• CAD tools work great with arithmetic functions

• Adding,subtracting,multiplying, etc.

• A few things to learn first

• How to work with multi-bit numbers in CAD tools and VHDL

• How to create custom components in CAD tools• I.e. a 7-bit adder/subtractor

• How to include VHDL components in a larger schematic

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-2

Multi-bit Numbers - Busses

• In Quartus II Schematics

• Busses are collections of wires

• mybus[7..0] is an eight bit bus• Composed of mybus[7] (MSB) through mybus[0]

(LSB)

• Busses make it easier to draw circuit diagrams

• In VHDL

• Busses are defined as a type of STD_LOGIC

• X: STD_LOGIC_VECTOR (7 DOWNTO 0)• Composed of X(7) through X(0)

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-3

Connecting by name in Schematics

• Nodes (wires) can be connected by name

• Reduces complexity of drawing

• Input names

• Can be used on any wires

• All wires of the same name are connected

• Intermediate node names

• Just name it – no need to define it

• Busses

• Can connect a single wire from a bus by name

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-4

Busses in Schematics

• Many components have bus inputs

• Adders, for example

• Busses use thick lines

• Drawing from a bus input automatically makes a bus

• May select thick line from the line style menu• Connecting busses

• Just name them the same thing

• Making busses out of wires

• Type all of the components (MSB to LSB) separated by commas

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-5

Creating and Using Custom Schematic Symbols

1. Make your component. Inputs/Outputs are interface to higher level

2. File | Create/Update | Create Symbol File For Current File

3. Make a new schematic for your main file and use your new symbol!

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-6

Making and Using Custom VHDL Symbols1. Make your component. Inputs/Outputs are interface to higher level

2. File | Create/Update | Create Symbol File For Current File

3. Make a new schematic for your main file and use your new symbol!

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-7

MegaFunctions

• Quartus II has many configurable megafunctions

• Adders, subtractors, muxes, etc.

• Use the MegaWizard

• Button on the insert symbol menu

• Answer all of the questions

• see next slide…• Save the new part

• Insert it into your schematic

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-8

Using the MegaWizard

1. Choose “Create a new…” to make a new device

2a. Pick a megafunction to use:Arithmetic includes adders, subtractors, counters, multipliers, etc.Gates include multiple-bit variations of standard logic.

2b. Choose VHDL and give your part a name.

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-9

Using the MegaWizard

3. Pick options:Data bus widthModesEtc.

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-10

Using the MegaWizard

4. Decide if any inputs are constants (i.e. always adding 4)

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-11

Using the MegaWizard

5. Pick optional outputs:Adder has optional carryin, carryout, and overflow out.

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-12

Using the MegaWizard

6. Pipelining – advanced option to speed up the function. Don’t use for now.

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-13

Using the MegaWizard

7. Just click Finish…

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-14

Using the MegaWizard

8. Yes – add to your project so you can use it!

9. Now your new symbol is available for use in schematics!

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-15

Using Busses in VHDL

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY hextosevenseg ISPORT( N : IN STD_LOGIC_VECTOR(3 downto 0); a,b,c,d,e,f,g,dec : OUT STD_LOGIC);

END hextosevenseg;

ARCHITECTURE logicfunc OF hextosevenseg ISBEGIN

a <= NOT((N(2) AND N(1) AND NOT N(3)) OR

(N(1) AND NOT N(2) AND N(0)) );

b <= …

END logicfunc;

Must use the IEEE library to use STD_LOGIC

Bus definition

Using bus signals individually

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-16

Math in VHDL

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_signed.all;

ENTITY addemup ISPORT( A,B : IN STD_LOGIC_VECTOR(15 downto 0);

Sum : OUT STD_LOGIC_VECTOR(15 downto 0));END addemup;

ARCHITECTURE logicfunc OF addemup ISBEGIN

Sum <= A + B;

END logicfunc;

Must use the SIGNED library for math

It’s this easy!

We’re adding two 16-bit numbers and producing a 16-bit sum

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-17

Decisions in VHDL using IF/THEN/ELSELIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_signed.all;

ENTITY addemup ISPORT( A,B : IN STD_LOGIC_VECTOR(15 downto 0);

Sub : IN STD_LOGIC; Out : OUT STD_LOGIC_VECTOR(15 downto 0));

END addemup;

ARCHITECTURE logicfunc OF addemup ISBEGINPROCESS(Sub,A,B)BEGIN

IF (Sub = ‘0’)THEN Out <= A + B;ELSIF (Sub = ‘1’)THEN Out <= A – B;ELSE Out <= “0000000000000000”;END IF;

END PROCESS;END logicfunc;

Expand adder to adder/subtractor:Sub=‘1’ subtract, Sub=‘0’ Add

PROCESS: Identify which inputs may cause output to change

IF / ELSIF / ELSE / END IF;Decision-making statements

Don’t forget to END IF and PROCESS

Vector constantsin double quotes

Scalar constantsin single quotes

Seattle Pacific University EE 1210 - Logic System Design CADNumbers-18

Truth Tables in VHDL

LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY simplefunction IS

PORT( A : IN STD_LOGIC_VECTOR(1 downto 0); Z,Q : OUT STD_LOGIC);

END simplefunction;ARCHITECTURE logicfunc OF simplefunction IS

BEGINPROCESS(A)BEGIN

CASE A ISWHEN “00” => z<=‘0’;q<=‘0’;WHEN “01” => z<=‘1’;q<=‘1’;WHEN “10” => z<=‘1’;q<=‘1’;WHEN “11” => z<=‘0’;q<=‘1’;WHEN OTHERS =>z<=‘0’;q<=‘0’;

END CASE;END PROCESS;

END logicfunc;“Others” catches any unlisted cases.Use it even if you covered them all.

Process block specifies input(s) to process

A case for each rowin truth table

Vector constantsin double quotes

Scalar constantsin single quotes