ε ε -Optimal Minimum-Delay/Area Zero-Skew -Optimal Minimum-Delay/Area Zero-Skew Clock Tree Wire-Sizing in Pseudo- Clock Tree Wire-Sizing in Pseudo- Polynomial Time Polynomial Time Jeng-Liang Tsai Jeng-Liang Tsai Tsung-Hao Chen Tsung-Hao Chen Charlie Chung-Ping Chen Charlie Chung-Ping Chen (National Taiwan (National Taiwan University) University) University of Wisconsin- Madison http://vlsi.ece.wisc.edu
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ε -Optimal Minimum-Delay/Area Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time
ε -Optimal Minimum-Delay/Area Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time. Jeng-Liang Tsai Tsung-Hao Chen Charlie Chung-Ping Chen (National Taiwan University). University of Wisconsin-Madison http://vlsi.ece.wisc.edu. Outline. Background Motivation and contribution - PowerPoint PPT Presentation
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Clock tree is power-hungry (30% in Intel McKinley(0.18um/1GHz/130W) • P = f CV2
• Minimize switching capacitance (wiring area)
Stability affects design convergence• Allow incremental refinement to accommodate local changes
Interconnect delay dominates total delay• Wire-sizing is effective in reducing interconnect delay
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MotivationMotivation
Non-convex zero-skew constraints• No known algorithm solves zero-skew wire-sizing problem optimally
with polynomial runtime
Hence, a good clock tree wire-sizing algorithm can Minimize delay and power Guarantee optimality and runtime Have good stability
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ContributionContribution
First ε-optimal algorithm for solving clock min-delay/power zero-skew wire-sizing optimization problem
Provide complete (Sampled) solution set of the delay/power/area trade-off information for design planning
Efficient pseudo-polynomial runtime (6170-branch clock tree in 6 minutes within 1% optimality)
Runtime v.s. Optimality tradeoff Incremental clock re-balancing to speed up design convergence
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Literature OverviewLiterature Overview
“Reliable non-zero skew clock tree using wire width optimization”, Pillage, et al. [DAC ’93]• Iteratively optimize skew and delay using adjoint sensitivity analysis• Aimed at reliable clock trees under process variation
Integrated Deferred Merging Embedding (IDME) algorithm, Wong, et al. [ISPD’00]• Handles simultaneous routing, buffer-insertion, and wire-sizing• Merging segment set: a set of line samples of a merging region• No optimality guarantee• The size of MSS grows exponentially
“Process variation aware clock tree routing”, Lu, et al. [ISPD ’03]• Based on DME/BST
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OutlineOutline
Background• Motivation and contribution• Literature overview
ClockTune algorithm• Problem formulation• ClockTune algorithm overview• Optimality and complexity analysis