This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Rochester Institute of TechnologyMicroelectronic Engineering
CMOS Factory
Page 2
INTRODUCTION
This document contains items that should be included in the students lab notebook. This includes general information about the processes and products made in the student factory.
Rochester Institute of TechnologyMicroelectronic Engineering
CMOS Factory
Page 3
INTRODUCTION
RIT is supporting two different CMOS process technologies. The older p-well CMOS and SMFL-CMOS have been phased out. The SUB-CMOS process is used for standard 3 Volt Digital and Analog integrated circuits. This is the technology of choice for teaching circuit design and fabricating CMOS circuits at RIT. The ADV-CMOS process is intended to introduce our students to process technology that is close to industry state-of-the-art. This process is used to build test structures and develop new technologies at RIT.
Bruce FurnaceAG-RTPBlue M OvenNanospecSpectromapCDE Resistivity Map
ASM 6”LPCVDP-5000NanospecSpectromapVarian 350D
While in each discipline the students willProcess lots requiring steps in that disciplinePerform follow up Inspection and MetrologyInvestigate and Update SPC dataMonitor non-device process metricsPerform a “pass down” at the end of (2 weeks)Track lots in and out of Mesa
Discipline
RedGroup1. Srishti2. Varshini3.
Every two weeks groups shift discipline (to the right). For example the red group does Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc.
Bruce FurnaceAG-RTPBlue M OvenNanospecSpectromapCDE Resistivity Map
ASM 6”LPCVDP-5000NanospecSpectromapVarian 350D
While in each discipline the students willProcess lots requiring steps in that disciplinePerform follow up Inspection and MetrologyInvestigate and Update SPC dataMonitor non-device process metricsPerform a “pass down” at the end of (2 weeks)Track lots in and out of Mesa
Discipline
RedGroup1. Shrushti2. 3.
Every two weeks groups shift discipline (to the right). For example the red group does Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc.
Rochester Institute of TechnologyMicroelectronic Engineering
CMOS Factory
Page 19
EXAMPLE TEAM REPORT AT END OF ROTATION
Discipline: Lithography Date: Nov 30- Dec 8, 2014Group Members: Matt McQuillan, Dave Pawlik
Lot Advancement: F031013 – CC Photo –Changed Stepper Job to Align using TVPA Marks Only
added 2 µm shift to alignment key locations on pg 4/ in process fileF040119 – Resist StripF040614 – Active PhotoF031013 – LDDP PhotoF040920 – Resist Strip-Changed Stepper Job to Align using TVPA Marks OnlyF040920 – P-Well Photo-Changed Stepper Job to Align using TVPA Marks OnlyF030922- Resist Strip
Other: Short Loop Resist Coat Thickness measurement for Coat.rcp, Xpr=1.0 µmBranson Asher often gives purge timeout error, select continue
Lot No Product Process / Version Current operation
Q P STEP Next Operation
Qty Comments
F111208 JOHN GALT SUB-CMOS 150 PH03 X 70 ET26 2 ORANGE
F120825 JOHN GALT SUB-CMOS 150 IM01 X 46 ET07 4 YELLOW
F121126 JOHN GALT SUB-CMOS 150 CV01 X 35 IM01 2 GREEN
F121208 JOHN GALT SUB-CMOS 150 ET06 X 26 OX04 3 BLUE
F130207 JOHN GALT SUB-CMOS 150 OX04 X 9 ET19 4 RED, TUBE 1
F130620 JOHN GALT SUB-CMOS 150 CL01 X 1 OX05 3 BLUE
F130626 JOHN GALT ADV-CMOS 150 OX05 X 1 CV02 3 RED, TUBE 4
Rochester Institute of TechnologyMicroelectronic Engineering
Dr. Lynn Fuller
Date: 8-26-14 Time: 8:00 amRed (Diffusion) Orange (Lithography) Yellow (Plasma Etch) Green (Implant/CVD) Blue (wet Etch)
ORANGE – determine correct exposure time for lot numbers using MA150 contact exposure
- prepare wafers for testing aluminum plasma etch- test completed wafers
Rochester Institute of TechnologyMicroelectronic Engineering
CMOS Factory
Page 24
MANUFACTURING IMPROVEMENT
If no factory lots are available in a specific discipline then group will do manufacturing improvement projects.
For Example:BOE – Etch rate verificationRTP – Tool operation and recipe verificationPECVD – Tool operation and deposition rate verification,TEOS OxideResist Coat Thickness Measurement using Spectromap for Coat.rcp and
CoatMtl.rcp Recipes used by FactorySPC Chart verification, evaluation and process capability improvementVerify all MESA picture documents are correctVerify MESA instructions are correct