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TS7QFT26220-6S
Transcend Information Inc. 1
品 名: __創見 4GB DDR2 667 FB-DIMM_
創 見 料 號: TS7QFT26220-6S __
規 格: 4GB 240Pin FB-DIMM DDR2-667 ECC Fully Buffered DIMM
廠 商: __研華科技股份有限公司__
廠 商 料 號: ___________________________________
日 期: ________________________________________
頁 數: ________________________________________
結 論: ________________________________________
Transcend 創見資訊股份有限公司 Your Supplier, Your Partner,
Your Friend. Transcend Information Inc.
地址:台北市內湖區行忠路 70 號 TEL: (886) 2-2792-8000
FAX: (886) 2-2793-2222/2-2796-8014
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 1
Description The TS7QFT26220-6S is a 512M x 72bits ECC
DDR2-667 Fully Buffered DIMM. The TS7QFT26220-6S
consists of 36pcs 256Mx4bits DDR2 DRAM in 60 balls
FBGA package, 1 pc AMB IC, and a 2048 bits serial
EEPROM on a 240-pin printed circuit board. The
TS7QFT26220-6S is a 240pin fully buffered dual in-line
memory module.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host,
including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access, and power
management. The Advanced Memory Buffer interface is
responsible for handling channel and memory requests to
and from the local DIMM and for forwarding requests to
other DIMM on the memory channel. Fully Buffered
DIMM provides a high memory bandwidth, large capacity
channel solution that has a narrow host interface.
Features
RoHS compliant products.
240pin fully buffered dual in-line memory module
3.2Gb/s, 4.0Gb/s link transfer rate
1.8V +/- 0.1V Power Supply for DRAM VDD/VDDQ
1.5V +/- 0.075V Power Supply for AMB VCC
3.3V +/- 0.3V Power Supply for VDDSPD
Buffer Interface with high-speed differential
point-to-point Link at 1.5 volt
Channel error detection & reporting
Channel fail over mode support
Serial presence detect with EEPROM
8Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Automatic DDR2 DRAM bus and channel calibration
MBIST and IBIST Test functions
Hot add-on and Hot Remove Capability
Transparent mode for DRAM test support
Support ECC Function.
Placement
FED
B
A
C
G
H
MIJ
KL
AMB
N
PCB: 09-2622
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 2
Dimensions Side Millimeters Inches
A 133.35±0.15 5.250±0.006
B 51.00 2.00
C 67.00 2.64
D 5.00 0.197
E 2.50 0.0980
F 1.50 0.059
G 5.175 0.204
H 2.175 0.086
I 3.00 0.118
J 9.50 0.374
K 17.30 0.681
L 30.35±0.15 1.2±0.006
M 1.27±0.10 0.050±0.004
N 6.80 0.268
(Refer Placement)
Pin Description Symbol Function
SCK System Clock Input, positive line
/SCK System Clock Input, negative line
PN[13:0] Primary Northbound Data, positive lines
/PN[13:0] Primary Northbound Data, negative lines
PS[9:0] Primary Southbound Data, positive lines
/PS[9:0] Primary Southbound Data, negative lines
SN[13:0] Secondary Northbound Data, positive lines
/SN[13:0] Secondary Northbound Data, negative lines
SS[9:0] Secondary Southbound Data, positive lines
/SS[9:0] Secondary Southbound Data, negative lines
SCL Serial Presence Detect (SPD) Clock Input
SDA SPD Data Input / Output
SA[2:0] SPD Address Input, also used to select the DIMM number
in the AMB
VID[1:0]
Voltage ID: these pins must be unconnected for DDR2-base Fully
Buffered DIMMs VID[0] is VDD value:OPEN=1.8V,GND=1.5V VID[1] is Vcc
value:OPEN=1.5V,GND=1.2V
RESET AMB reset signal
RFU Reserved for Future Use
VCC AMB Core Power and AMB Channel interface Power (1.5
Volt)
VDD DRAM Power and AMB DRAM I/O Power (1.8 Volt)
VTT DRAM Address/Command/Clock Termination Power (VDD/2)
VDDSPD SPD Power
VSS Ground
DNU/M_Test
The DNU/M Test pin provides an external connection R/Cs A-D for
testing the margin of Vref which is produced by a voltage divider
on the module. It is not intended to be used in normal system
operation and must not be connected(DNU) in a system. This test pin
may have other features on future card designs and if it does, will
be included in this specification at that time.
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 3
Pinouts: Pin No
Pin Name
Pin No
Pin Name
Pin No
Pin Name
PinNo
Pin Name
PinNo
Pin Name
PinNo
Pin Name
01 VDD 41 /PN13 81 VSS 121 VDD 161 /SN13 201 VSS 02 VDD 42 VSS
82 PS4 122 VDD 162 VSS 202 SS4 03 VDD 43 VSS 83 /PS4 123 VDD 163
VSS 203 /SS4 04 VSS 44 RFU* 84 VSS 124 VSS 164 RFU* 204 VSS 05 VDD
45 RFU* 85 VSS 125 VDD 165 RFU* 205 VSS 06 VDD 46 VSS 86 RFU* 126
VDD 166 VSS 206 RFU* 07 VDD 47 VSS 87 RFU* 127 VDD 167 VSS 207 RFU*
08 VSS 48 PN12 88 VSS 128 VSS 168 SN12 208 VSS 09 VCC 49 /PN12 89
VSS 129 VCC 169 /SN12 209 VSS 10 VCC 50 VSS 90 PS9 130 VCC 170 VSS
210 SS9 11 VSS 51 PN6 91 /PS9 131 VSS 171 SN6 211 /SS9 12 VCC 52
/PN6 92 VSS 132 VCC 172 /SN6 212 VSS 13 VCC 53 VSS 93 PS5 133 VCC
173 VSS 213 SS5 14 VSS 54 PN7 94 /PS5 134 VSS 174 SN7 214 /SS5 15
VTT 55 /PN7 95 VSS 135 VTT 175 /SN7 215 VSS 16 VID1 56 VSS 96 PS6
136 VID0 176 VSS 216 SS6 17 /RESET 57 PN8 97 /PS6 137 DNU/M_ Test
177 SN8 217 /SS6 18 VSS 58 /PN8 98 VSS 138 VSS 178 /SN8 218 VSS 19
RFU** 59 VSS 99 PS7 139 RFU** 179 VSS 219 SS7 20 RFU** 60 PN9 100
/PS7 140 RF** 180 SN9 220 /SS7 21 VSS 61 /PN9 101 VSS 141 VSS 181
/SN9 221 VSS 22 PN0 62 VSS 102 PS8 142 SN0 182 VSS 222 SS8 23 /PN0
63 PN10 103 /PS8 143 /SN0 183 SN10 223 /SS8 24 VSS 64 /PN10 104 VSS
144 VSS 184 /SN10 224 VSS 25 PN1 65 VSS 105 RFU** 145 SN1 185 VSS
225 RFU** 26 /PN1 66 PN11 106 RFU** 146 /SN1 186 SN11 226 RFU** 27
VSS 67 /PN11 107 VSS 147 VSS 187 /SN11 227 VSS 28 PN2 68 VSS 108
VDD 148 SN2 188 VSS 228 SCK 29 /PN2 69 VSS 109 VDD 149 /SN2 189 VSS
229 /SCK 30 VSS 70 PS0 110 VSS 150 VSS 190 SS0 230 VSS 31 PN3 71
/PS0 111 VDD 151 SN3 191 /SS0 231 VDD 32 /PN3 72 VSS 112 VDD 152
/SN3 192 VSS 232 VDD 33 VSS 73 PS1 113 VDD 153 VSS 193 SS1 233 VDD
34 PN4 74 /PS1 114 VSS 154 SN4 194 /SS1 234 VSS 35 /PN4 75 VSS 115
VDD 155 /SN4 195 VSS 235 VDD 36 VSS 76 PS2 116 VDD 156 VSS 196 SS2
236 VDD 37 PN5 77 /PS2 117 VTT 157 SN5 197 /SS2 237 VTT 38 /PN5 78
VSS 118 SA2 158 /SN5 198 VSS 238 VDDSPD 39 VSS 79 PS3 119 SDA 159
VSS 199 SS3 239 SA0 40 PN13 80 /PS3 120 SCL 160 SN13 200 /SS3 240
SA1
RFU = Reserved Future Use * These pin position are reserved for
forwarded clocks to be used in future module implementations **
These pin positions are reserved for future architecture
flexibility
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 4
Block Diagram
D M /C S D Q S /D Q S
U 0I/O 0I/O 1I/O 2I/O 3
D Q 0D Q 1D Q 2D Q 3
D Q S 0/D Q S 0
/S 1/S 0
N o te :1 . D Q -to I/O w ir in g m a y b e c h a n g e d w ith
in a b y te.2 . T h e re a re tw o p h y s ic a l c o p ie s o f e
a c h a d d re s s/c o m m a n d /c o n tro l/c lo c k .3 . T h e
re a re fo u r p h y s ic a l c o p ie s o f e a c h c lo c k.
S D AS C L
S A 0 S A 1 S A 2
E E P R O M
W P
/D Q S 0 ~ /D Q S 8S C LS D A
S A 1 ~ S A 2
/R E S E T
P N 0 ~ P N 1 3/P N 0 ~ /P N 1 3
P S 0 ~ P S 9/P S 0 ~ /P S 9D Q 0 ~ D Q 6 3
C B 0 ~ C B 7D Q S 0 ~ D Q S 1 7
AMB
S C K //S C K
S N 0 ~ S N 1 3/S N 0 ~ /S N 1 3S S 0 ~ S S 9/S S 0 ~ /S S 9S 0
-> /C S (U 0 ~ U 1 7 )C K E 0 -> C K E (U 0 ~ U 1 7 )S 1
-> /C S (U 1 8 ~ U 3 5 )
O D T -> O D T (a ll S D R A M s)B A 0 ~ B A 2 (a ll S D R A
M s)A 0 ~ A 1 5 (a ll S D R A M s)/R A S (a ll S D R A M s)/C A S
(a ll S D R A M s)/W E (a ll S D R A M s)C K //C K (a ll S D R A M
s)
V S S
U 1 8I/O 0I/O 1I/O 2I/O 3
U 1I/O 0I/O 1I/O 2I/O 3
D Q 8D Q 9D Q 1 0D Q 1 1
U 1 9I/O 0I/O 1I/O 2I/O 3
U 2I/O 0I/O 1I/O 2I/O 3
D Q 1 6D Q 1 7D Q 1 8D Q 1 9
U 2 0I/O 0I/O 1I/O 2I/O 3
U 3I/O 0I/O 1I/O 2I/O 3
D Q 2 4D Q 2 5D Q 2 6D Q 2 7
U 2 1I/O 0I/O 1I/O 2I/O 3
U 4I/O 0I/O 1I/O 2I/O 3
D Q 3 2D Q 3 3D Q 3 4D Q 3 5
U 2 2I/O 0I/O 1I/O 2I/O 3
U 5I/O 0I/O 1I/O 2I/O 3
D Q 4 0D Q 4 1D Q 4 2D Q 4 3
U 2 3I/O 0I/O 1I/O 2I/O 3
U 6I/O 0I/O 1I/O 2I/O 3
D Q 4 8D Q 4 9D Q 5 0D Q 5 1
U 2 4I/O 0I/O 1I/O 2I/O 3
U 7I/O 0I/O 1I/O 2I/O 3
D Q 5 6D Q 5 7D Q 5 8D Q 5 9
U 2 5I/O 0I/O 1I/O 2I/O 3
U 8I/O 0I/O 1I/O 2I/O 3
C B 0C B 1C B 2C B 3
U 2 6I/O 0I/O 1I/O 2I/O 3
U 9I/O 0I/O 1I/O 2I/O 3
/D Q S 9
D Q 4D Q 5D Q 6D Q 7
D Q S 9
U 2 7I/O 0I/O 1I/O 2I/O 3
U 1 0I/O 0I/O 1I/O 2I/O 3
/D Q S 1 0
D Q 1 2D Q 1 3D Q 1 4D Q 1 5
D Q S 1 0
U 2 8I/O 0I/O 1I/O 2I/O 3
U 1 1I/O 0I/O 1I/O 2I/O 3
/D Q S 1 1
D Q 2 0D Q 2 1D Q 2 2D Q 2 3
D Q S 1 1
U 2 9I/O 0I/O 1I/O 2I/O 3
U 1 2I/O 0I/O 1I/O 2I/O 3
/D Q S 1 2
D Q 2 8D Q 2 9D Q 3 0D Q 3 1
D Q S 1 2
U 3 0I/O 0I/O 1I/O 2I/O 3
U 1 3I/O 0I/O 1I/O 2I/O 3
/D Q S 1 3
D Q 3 6D Q 3 7D Q 3 8D Q 3 9
D Q S 1 3
U 3 1I/O 0I/O 1I/O 2I/O 3
U 1 4I/O 0I/O 1I/O 2I/O 3
/D Q S 1 4
D Q 4 4D Q 4 5D Q 4 6D Q 4 7
D Q S 1 4
U 3 2I/O 0I/O 1I/O 2I/O 3
U 1 5I/O 0I/O 1I/O 2I/O 3
/D Q S 1 5
D Q 5 2D Q 5 3D Q 5 4D Q 5 5
D Q S 1 5
U 3 3I/O 0I/O 1I/O 2I/O 3
U 1 6I/O 0I/O 1I/O 2I/O 3
/D Q S 1 6
D Q 6 0D Q 6 1D Q 6 2D Q 6 3
D Q S 1 6
U 3 4I/O 0I/O 1I/O 2I/O 3
U 1 7I/O 0I/O 1I/O 2I/O 3
/D Q S 1 7
C B 4C B 5C B 6C B 7
D Q S 1 7
U 3 5I/O 0I/O 1I/O 2I/O 3
V T TA ll a d d re s s /c o m m a n d /c o n tro l/c lo c k
V D D S P D
V D D
V R E F
V S S
S P D , A M B
U 0 ~ U 3 5 , A M B
U 0 ~ U 3 5
U 0 ~ U 3 5 , S P D , A M B
V T T T e rm in a to rs
V C C A M B
C K E 1 -> C K E (U 1 8 ~ U 3 5 )
S A 0
D Q S 1/D Q S 1
D Q S 2/D Q S 2
D Q S 3/D Q S 3
D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D M /C S D Q S /D Q S D M /C S D Q S /D Q S
D Q S 4/D Q S 4
D Q S 5/D Q S 5
D Q S 6/D Q S 6
D Q S 7/D Q S 7
D Q S 8/D Q S 8
This technical information is based on industry standard data
and tests believed to be reliable. However, Transcend makes no
warranties, either expressed or implied, as to its accuracy and
assume no liability in connection with the use of this product.
Transcend reserves the right to make changes in specifications at
any time without prior notice.
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 5
Absolute Maximum Ratings Parameter Symbol Value Unit Notes
Voltage on any pin relative to Vss Vin, Vout -0.3~1.75 V 1
Voltage on Vcc pin relative to Vss Vcc -0.3~1.75 V 1 Voltage on VDD
relative to Vss VDD -0.5~2.3 V 1 Voltage on VTT pin relative to Vss
VTT -0.5 ~ 2.3 V 1 Storage temperature TSTG -55~+100 °C 1 DDR2
SDRAM device operation temperature (Ambient) Tcase 0~85 °C 1,2 AMB
device operation temperature (Ambient) Tj 0~110 °C 1,2
1. Stress greater than those listed may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may adversely affect reliability.
Note:
2. DDR2 SDRAM of FBDIMM should require this specification.
Input DC Operation Condition Parameter Symbol MIN Nom MAX Unit
Notes
AMB supply voltage Vcc 1.46 1.50 1.54 V DDR2 SDRAM supply
voltage VDD 1.7 1.8 1.9 V Termination voltage VTT 0.48xVDD 0.50xVDD
0.52xVDD V EEPROM supply voltage VDDSPD 3.0 3.3 3.6 V SPD Input
HIGH (logic 1) voltage VIH(DC) 2.1 - VDDSPD V 1 SPD Input LOW
(logic 0) voltage VIL(DC) - 0.8 V 1 RESET Input HIGH (logic 1)
voltage VIH(DC) 1.0 - V 2 RESET Input LOW (logic 0) voltage VIL(DC)
- 0.5 V 1 Leakage Current (RESET) IL -90 - 90 uA 2 Leakage Current
(link) IL -5 - 5 uA 3
1.Applies for SMB and SPD bus signals. 2.Applies for AMB CMOS
signal RESET #.
Note:
3.For all other AMB related DC parameter. Please refer to the
high-speed differential link specification.
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 6
Timing Parameters Parameter Symbol MIN Nom MAX Unit Note
EI Assertion Pass-Thru Timing tEI Propagate t 4 clks -
EI Deassertion Pass-Thru Timing tEID Bitlock clks 2
EI Assertion Duration tEI 100 clks 1,2
FBD Cmd to DDR Clk out that latches Cmd 8.1 ns 3
FBD Cmd to DDR Write TBD ns
DDR Read to FBD (last DIMM) 5.0 ns 4
Resample Pass-Thru time 1.075 ns
ResynchPass-Thru time 2.075 ns
Bit Lock Interval tBitLock 119 frames 1
Frame Lock Interval tFrameLock 154 frames 1 1. Defined in
FB-DIMM Architecture and Protocol Spec 2. Clocks defined as core
clocks = 2x SCK input
Note:
3. @DDR2-667 - measured from beginning of frame at southbound
input to DDR clock output that latches the first command of a frame
to the DRAMs
4. @ DDR2-667 - measured from latest DQS input AMB TO start of
matching data frame at northbound FB-DIMM outputs.
VTT Currents Description Symbol Typ MAX Units
Idle current, DDR2 SDRAM device power down ITT1 500 700 mA
Active power, 50% DDR2 SDRAM BW ITT2 500 700 mA
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 7
Power specification parameter and test condition Symbol
Condition Power Supply Units
Icc_Idle_0 1.5V MA Icc_Idle_0
Idle Current, single or last DIMM L0 state, idle (0 BW) Primary
channel enabled, Secondary Channel Disabled CKE high. Command and
address lines stable. DRAM clock active.
1.8V mA
Idd_Idle_0 Total Power W Icc_Idle_1 1.5V mA Icc_Idle_1
Idle Current, first DIMM L0 state, idle (0 BW) Primary and
Secondary channels enabled CKE high. Command and address lines
stable. DRAM clock active.
1.8V mA
Idd_Idle_1 Total Power W Icc_Idle_2 1.5V mA Icc_Idle_2
Idle Current, DRAM power down L0 state, idle (0 BW) Primary and
Secondary channels enabled CKE low. Command and address lines
floated. DRAM clock active, ODT and CKE driven low.
1.8V mA
Idd_Idle_2 Total Power W Icc_Active_1 1.5V mA Idd_Active_1
Active Power L0 state. 50% DRAM BW, 67% read, 33% write. Primary
and Secondary channels enabled. DRAM clock active, CKE high.
1.8V mA
Idd_Active_1 Total Power W Icc_Active_2 1.5V mA Idd_Active_2
Active Power, data pass through L0 state. 50% DRAM BW to
downstream DIMM, 67% read, 33% write. Primary and Secondary
channels enabled CKE high. Command and address lines stable. DRAM
clock active.
1.8V mA
Idd_Active_2 Total Power W Icc_L0s 1.5V mA Idd_L0s
Channel Standby Average power over 42 frames where the channel
enters and exits L0s. DRAMs Idle (0 BW). CKE low. Command and
address lines floated DRAM clock active, ODE and CKE driven
low.
1.8V mA
Idd_L0s Total Power W Idd Traning
(for AMB spec, Not in SPD)
1.5V mA
Training Primary and Secondary channels enabled. 100% toggle on
all channel lanes DRAMs idle. 0 BW. CKE high, Command and address
lines stable. DRAM clock active.
1.8V mA
Idd_Training Total Power W
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 8
Power specification (Vdd Max = 1.900V , Vcc Max = 1.575V) 4GB
Notes Unit
Icc_Idle_0 TBD 1.5V mA Idd_Idle_0 TBD 1.8V mA P_idle_0 TBD W
Icc_Idle_1 TBD 1.5V mA Idd_Idle_1 TBD 1.8V mA P_idle_1 TBD W
Icc_active_1 TBD 1.5V mA Idd_active_1 TBD 1.8V mA P_active_1 TBD
W
Icc_active_2 TBD 1.5V mA Idd_active_2 TBD 1.8V mA P_active_2 TBD
W Icc_training TBD 1.5V mA Idd_training TBD 1.8V mA P_training TBD
W
Reference Clock Input Specification
Values Parameter Symbol MIN MAX
Units Note
Reference clock frequency @3.2 Gb/s (nominal 133.33 MHz)
FRefclk-3.2 126.67 133.40 MHz 1,2
Reference clock frequency @4.0 Gb/s (nominal 166.67 MHz)
FRefclk-4.0 158.33 166.75 MHz 1,2
Rise time, fall time TSCK-RISE, TSCK-FULL 175 700 ps 3 Voltage
high VSCK-HIGH 660 850 mV Voltage low VSCK-LOW -150 mV Absolute
crossing point VCROSS-ABS 250 550 mV 4 Relative crossing VCROSS-REL
calculated calculated 4,5 Percent mismatch between rise and fall
times
VSCK-RISE-FALL-MATCH - 10 %
Duty cycle of reference clock VSCK-DUTYCYCLE 40 60 % Clock
leakage current II-CK -10 10 uA 6,7 Clock input capacitance CI-CK
0.5 2 pF 7 Clock input capacitance delta CI_CK(D) -0.25 0.25 pF 8
Transport delay T1 5 ns 9,10 Phase jitter sample size NSAMPLE 1016
Periods 11 Reference clock jitter, filtered TREF-JITTER 40 ps 12,13
Reference clock deterministic jitter TREF-DJ TBD ps
1.133MHz for PC2-4200 and 166MHz for PC2-5300. 2. Measured with
SSC disabled. 3. Measured differentially through the range of
0.175V to 0.525V. 4. The crossing point must meet the absolute and
relative crossing point specification simultaneously. 5.
VCROSS_REL_(MIN) and VCROSS_REL(MAX) are derived using the
following calculation : Min =
0.5(Vhavg-0.710)+0.250;and Max=0.5(Vhavg-0.710)+0.550, where
Vhavg is the average of VSCK-HIGHM.
Note:
6. Measured with a single-ended input voltage of 1V.
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
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4GB With 256Mx4 CL5
Transcend Information Inc. 9
7. Applies to reference clocks SCK and SCK. 8. Difference
between SCK and SCK input. 9. T1 = [Tdatapath-Tclockpath](excluding
PLL loop delays). This parameter is not a direct clock output
parameter
but in indirectly determines the clock output parameter
TREF-JITTER. 10. The net transport delay is the difference in time
of flight between associated data and clock paths. The data
path is defined from the reference clock source, through the TX,
to data arrival at the data dampling point in the RX. The clock
path is defined from the reference clock source to clock arrival at
the same sampling point. The path delays are caused by copper trace
routes, on-chip routing, on-chip buffering, etc. They include the
time-of flight of interpolators or other clock adjustment
mechanisms. They do not include the phase delays caused by finite
PLL loop bandwidth because these delays are modeled by the PLL
transfer functions.
11. Direct measurement of phase jitter records over 1016 periods
is impractical. It is expected that the jitter will be measured
over a smaller, yet statistically significant, sample size and the
total jitter at 1016 samples extrapolated from an estimate of the
sigma of the random jitter components.
12. Measured with SSC enabled on reference clock generator.
13. As measured after the phase jitter filter. This number is
separate from the receiver jitter budget that is defined by the
TRXTotal – MIN parameters
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TTTSSS777QQQFFFTTT222666222222000---666SSS 240PIN DDR2 667 Fully
Buffered DIMM
4GB With 256Mx4 CL5
Transcend Information Inc. 10
Differential Transmitter Output Specification Parameter Symbol
Min Max Units Comments
Differential peak-to-peak output voltage for large voltage
swing
VTX-DIFFp-p_L 900 1300 mV EQ1,Note1
Differential peak-to -peak output voltage for reqular voltage
swing
VTX-DIFFp-p_R 800 - mV EQ1,Note1
Differential peak-to-peak output voltage for small votage
swing
VTX-DIFFp-p_S 520 - mV EQ1,Note1
DC common code output voltage for large voltage swing
VTX-CM_L - 375 mV EQ2,Note1
DC common code output voltage for small voltage swing
VTX-CM_S 135 280 mV EQ2,Note1,2
De-emphasized differential output voltage ratio for -3.5 dB
de-emphasis
VTX-DE-3.5-Ratio -3.0 -4.0 dB 1,3,4
De-emphasized differential output voltage ratio for -6.0 dB
de-emphasis
VTX-DE-6.0-Ratio -5.0 -7.0 dB 1,2,3
AC peak-to-peak common mode output voltage for large swing
VTX-CM-Acp-p-L - 90 mV EQ7,Note1,5
AC peak-to-peak common mode output voltage for regular swing
VTX-CM-Acp-p-R - 80 mV EQ7,Note1,5
AC peak-to-peak common mode output voltage for small swing
VTX-CM-Acp-p-S - 70 mV EQ7,Note1,5
Maximum single-ended voltage in EI condition DC+AC
VTX-IDLE-SE - 50 mV 6
Maximum single-ended voltage in EI condition DC+AC
VTX-IDLE-SE-DC - 20 mV 6
Maximum peak-to-peak differential voltage in EI condition
VTX-IDLE-DIFF-p-p - 40 mV
Single-ended voltage (w.r.t. VSS) on D+/D- VTX-SE -75 750 mV 1,7
Mimimum TX eye width, 3.2 and 4.0 Gb/s VTX-Eye-MIN 0.7 - UI 1,8
Mimimum TX eye width 4.8 Gb/s VTX-Eye-MIN4.8 TBD - UI 1,8 Maximum
TX deterministic jitter, 3.2 and 4.8Gb/s
VTX-DJ-DD - 02 UI 1,8,9
Maximum TX deterministic jitter, 4.8 Gb/s VTX-DJ-DD-4.8 - TBD UI
1,8,9 Insantaneous pulse width VTX-PULSE 0.85 - UI 10 Differential
TX output rise/fall time VTX-RISE TTX-FALL 30 90 ps 20~80% voltage,
Note1Mismatch between rise and fall times VTX-RF-MISMATCH - 20 ps
Differential return loss RLTTX-DIFF 8 - dB 1~2.4GHz, Note11 Common
mode return loss RLTTX-CM 6 - dB 1~2.4GHz, Note11 Transmitter
termination impender RTX 41 55 12
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D+/D-TX Impedance difference RTX-MATCH-DC - 4 % EQ 4, Boundaries
are applied separately to high and low output voltage states
Lane-to lane skew at TX LTX-SKEW1 - 100+3UI ps 13,15 Lane-to
lane skew at TX LTX-SKEW2 - 100+2UI ps 14,15
Differential Receiver Input Specification
Parameter Symbol Min Max Unit Comments Differential peak-to-peak
input voltage for large voltage swing VRX-DIFFp-p
170 TBD mV EQ5, Note1
Maximum single-ended voltage in El condition VRX-IDEL-SE - 75 mV
2,3 Maximum single-ended voltage in Ei condition (DC only)
VRX-IDEL-SE-DC - 50 mV 2,3
Maximum peak-to-peak differential voltage in El condition
VRX-IDEL-DIFFp-p - 65 mV 3
Single-ended voltage (w.r.t. VSS) on D+/D- VRX-SE -300 900 mV
4
Single-pulse peak differential input voltage VRX-DIFF-PULSE 85 -
mV 4,5
Amplitude ratio between adjacent symbols VRX-DIFF-ADJ-RATIO -
TBD 4,6 Maximum RX inherent timing error, 3.2 and 4.0 Gb/x
TRX-TJ-MAX - 0.4 UI 4,7,8
Maximum RX inherent deterministic timing error, 3.2 and 4.8 Gb/s
TRX-TJ-MAX4.8 - TBD UI 4,7,8
Single-pulse width as zero-voltage crossing VRX-DJ-DD - 0.3 UI
4,7,8,9
Skingle-pulse width at minimum-level crossing VRX-DJ-DD-4.8 -
TBD UI 4,7,8,9
Differential RX input rise/fall time VRX-PW-ZC 0.55 - UI 4,5
common mode fo the input voltage VRX-PW-ML 0.2 - UI 4,5
Differential RX output rise/fall time TRX-RISE TRX-FALL 50 - ps
20~80% voltage
Common mode of input voltage VRX-CM 120 400 mV EQ6, Note1,10 AC
peak-to-peak common mode of input voltage VRX-CM-Acp-p - 270 mV
EQ7, Note1
Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp-p VRX-CM-EH-RATOP -
45 % 11
Differential return loss RLRX-DIFF 9 - dB 1~2.4GHz, Note12
Common mode return loss RLRX-CM 6 - dB 1~2.4GHz, Note12
RX termination impedance RRX 41 55 Ω 13 D+/D- RX Impedance
difference RRX-MATCH-DC - 4 % EQ8
Lane-to lane PCB skew at RX LRX-PCB-SKEW - 6 UI
Lane-to-lane skew at the receiver that must be tolerated. Note
14
Minimum RX drift tolerance TRX-DRIFT 400 - ps 15
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Minim data tracking 3dB bandwidth FTRK 0.2 - MHz 16
Electrical idle entry detect time TEI-ENTRY-DETECT - 60 ns
17
Electrical idle exit detect time TEI-EXIT-DETECT - 30 ns
Bit Error Ratio BER - 10-12 18 1. Specified at the package pins
into a timing and voltage compliant test setup. Note that signal
levels at the pad
will be lower than at the pin. 2. Single-ended voltages below
that value that are simultaneously detected on D+ and D-are
interpreted as the
Electrical Idle condition. Worst-case margins are determined for
the case with transmitter using small voltage swing.
3. Multiple lanes need to detect the El condition before the
device can act upon the El detection. 4. Specified at the package
pins into a timing and voltage compliance test setup. 5. The
single-pulse mask provides suffcient symbol energy for reliable RX
reception. Each symbol must comply
with both the single-pulse mask and the cumulative eyemask. 6.
The relative amplitude ratio limit between adjacent symbols
prevents excessive intersymbol interference in the
RX. Each symbol must comply with the peak amplitude ratio with
regard to both the preceding and subsequent symbols.
7. This number does not include the effects of SSC or reference
clock jitter. 8. This number includes setup and hold of the RX
sampling flop. 9. Defined as the dual-dirac deterministic timing
error. 10. Allows for 15 mV DC offset between transmit and receive
devices. 11. The received differential signal must satisfy both
this ratio as well as the absolute maximum AC peaktopeak
common mode specification. For example, if VRX-DIFFp-p is 200
mV, the maximum AC peak-to peak common mode is the lesser of (200
mV*0.45=90mV)and VRX-CM-AC-p-p.
12. One of the components that contribute to the deterioration
of the return loss is the ESD structure which needs to be carefully
designed.
13. The termination small signal resistance; tolerance across
voltage from 100 mV to 400 mV shall not exceed +/-5 W with regard
to the average of the values measured at 100 mV and at 400 mV for
that pin.
14. This number represents the lane-to-lane skew between TX and
RX pins and does not include the transmitter output skew from the
component of the end-to-end channel skew in the AMB
specification.
15. Measured from the reference clock edge to the center of the
input eye. This specification must be met across specified voltage
and temperature ranges for a single component. Drift rate of change
is significantly below the tracking capability of the receiver.
16. This bandwidth number assume the specified minimum data
transition density. Maximum jitter at 0.2 MHz is 0.05 UI,
17. The specified time includes the time required to forward the
El entry condition.
Note:
18. BER per differential lane.
VRX-DIFFp-p = 2x[VRX-D+-VRX-D-] (EQ5)
(VRX-CM = DC(avg) of [VRX-D+ + VRX-D-] /2) (EQ 6)
VRX-CM-AC=((Max[VRX-D+ + VRX-D]/2]((Min [VRX-D+ + VRX-D-]/2] (EQ
7) RRX-MATCH-DC = 2x((RRX-D+-RRX-D-)/(RRX-D+ + RRX-D-) (EQ 8)
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SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect
Byte No. Function Described Standard Specification Vendor
Part
0 Number of Serial PD Bytes Written / SPD Device Size / CRC
Coverage
CRC coverage 0~116Byte, SPD Byte Total :256Byte, SPD Byte Use :
176Byte
92h
1 SPD Revision Revision 1.1 11h 2 Key Byte / DRAM Device Type
DDR2 SDRAM FB-DIMM 09h 3 Voltage Levels of this Assembly Channel
1.8V /DRAM 1.5V 12h
4 SDRAM Addressing
Number of Row Address : 14, Number of Col Address : 11, Number
of Bank Address : 8
49h
5 Module Physical Attributes Thickness : Under 8.2mm, Height :
30.35mm 24h
6 Module Type / Thickness FBDIMM(width 133.35mm) 07h 7 Module
Organization 2Rank/x4 10h 8 Fine Timebase Dividend and Divisor 5 ps
51h 9 Medium Timebase Dividend 1 01h 10 Medium Timebase Divisor 4
04h 11 SDRAM Minimum Cycle Time (tCKmin) 3ns 0Ch 12 SDRAM Maximum
Cycle Time (tCKmax) 8ns 20h 13 SDRAM CAS Latencies Supported CL 3,
4, 5 33h 14 SDRAM Minimum CAS Latency Time (tAA) 15ns 3Ch 15 SDRAM
Write Recovery Times Supported 2,3 clk 22h 16 SDRAM Write Recovery
Time (tWR) 15ns 3Ch 17 SDRAM Write Latencies Supported 2,3,4,5 clk
42h 18 SDRAM Additive Latencies Supported 0,1,2,3 clk 40h 19 SDRAM
Minimum RAS to CAS Delay (tRCD) 15ns 3Ch
20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 7.5ns
1Eh
21 SDRAM Minimum Row Precharge Time (tRP) 15ns 3Ch 22 SDRAM
Upper Nibbles for tRAS and tRC - 00h 23 SDRAM Minimum Active to
Precharge Time (tRAS) 45ns B4h
24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC)
55ns DCh
25 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command
Period (tRFC)
127.5ns FEh
26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command
Period (tRFC)
127.5ns 01h
27 SDRAM Internal Write to Read Command Delay (tWTR) 7.5ns
1Eh
28 SDRAM Internal Read to Precharge Command Delay (tRTP) 7.5ns
1Eh
29 SDRAM Burst Lengths Supported BL 4,8 03h 30 SDRAM
Terminations Supported 50, 75, 150 ohm 07h 31 SDRAM Drivers
Supported Weak Drivers 01h
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32 SDRAM Average Refresh Interval (tREFI) / Double Refresh mode
bit / High Temperature self-refresh rate support indication
7.8us 02h
33 Bits 7:4: Tcasemax Delta 3:0: DT4R4W Delta 85°C/ 0.40°C 01h
34 Thermal resistance of SDRAM 24.5 31h 35 DT0 0.3°C 04h
36 DT2N/DT2Q 1.5°C 0Fh
37 DT2P 0.15°C 0AH
38 DT3N 1.65°C 0Bh
39 DT4R/Mode Bit: Bits 7:1: Case temperature rise from ambient
due to IDD4R/page open 9.6°C, DT4W is greater
than DT4R 18h
40 DT5B: Case temperature rise from ambient due to IDD5B/burst
refresh operation 9°C 12h
41 DT7: Case temperature rise from ambient due to IDD7/bank
interleave read mode operation 10.5°C 15h
42~78 Reserved Reserved 00h
79 ODT definition Rank0(150ohm), Rank1(75ohm) 12h
80 Reserved Reserved 00h
81 FB-DIMM Channel Protocols Supported Least Significant Byte -
02h
82 FB-DIMM Channel Protocols Supported Most Significant Byte -
00h
83 b2b access turnaround bubble (assumes at tCK) - 00h 84
CMD2DATA (800) - 36h 85 CMD2DATA (667) - 34h 86 CMD2DATA (533) -
32h 87 TR AMB (free air JEDEC) - 2Ah 88 AMB DT Idle_0 - 5Eh 89 AMB
DT Idle_1 - 73h 90 AMB DT Idle_2 - 5Ch 91 AMB DT Active_1 - 9Bh 92
AMB DT Active_2 - 80h 93 AMB DT L0s - 00h 94 reserved (TR dram) -
00h 95 reserved (TR AMB) - 00h 96 reserved (TR DRAM2AMB) - 00h 97
reserved (TR AMB2DRAM) - 00h 98 AMB Junction Temperature Maximum(Tj
max) 125°C 1Fh 99 Air Flow Impedance,DRAM type, HS Type
Type3,Planar,FDHS 0Ah
100 reserved - 00h 101 AMB Personality Bytes: Pre-initialization
- 40h 102 AMB Personality Bytes: Pre-initialization - C0h 103 AMB
Personality Bytes: Pre-initialization - 02h 104 AMB Personality
Bytes: Pre-initialization - 44h
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105 AMB Personality Bytes: Pre-initialization - 9Ch 106 AMB
Personality Bytes: Pre-initialization - 30h 107 AMB Personality
Bytes: Post-initialization - 60h 108 AMB Personality Bytes:
Post-initialization - 33h 109 AMB Personality Bytes:
Post-initialization - 60h 110 AMB Personality Bytes:
Post-initialization - 1Bh 111 AMB Personality Bytes:
Post-initialization - 60h 112 AMB Personality Bytes:
Post-initialization - 1Bh 113 AMB Personality Bytes:
Post-initialization - 60h 114 AMB Personality Bytes:
Post-initialization - 1Bh 115 AMB Manufacturer’ s JEDEC ID Code IDT
80h
116 AMB Manufacturer’ s JEDEC ID Code IDT B3h
117~118 Module ID: Module Manufacturer’ s JEDEC ID Code
Transcend 01h, 4Fh
119 Module ID: Module Manufacturing Location T 54 120~125 Module
ID: Module Manufacturing Date - 00h 126~127 Cyclical Redundancy
Code - B5h, 1Fh
54 53 35 31 32 4D
46 42 37 32 56 36128~145 Manufacturers Part Number
TS7QFT26220-6S
54 2D 54 20 20 20146~147 Module Revision Code - 30h,20h 148~149
SDRAM Manufacturer's JEDEC ID Code Micron 80h, 2Ch 150~175
Manufacturer's Specific Data - 00h 176~255 Open for customer use -
00h
TS7QFT26220-6S.pdfDescription Input DC Operation Condition
Timing Parameters MAX
Power specification parameter and test condition
ParameterSymbolUnitsComments