gital Integrated Circuits 2nd Sequential Circuit Cascading Dynamic Gates Cascading Dynamic Gates Dynamic gates rely on temporary capacitive storage, while static gates have DC restoration. Except the above design issues, there is one major catch that complicates the design of dynamic circuits: straight- forward cascading of dynamic gates to create multi-level logic does NOT work.
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Cascading Dynamic GatesCascading Dynamic Gates Dynamic gates rely on temporary capacitive storage, while static gates have DC restoration.
Except the above design issues, there is one major catch that complicates the design of dynamic circuits: straight-forward cascading of dynamic gates to create multi-level logic does NOT work.
1) The arises because the outputs of each gate – thus the inputs of the next gate – are all precharged to 1, which may cause inadvertent discharge in the beginning of evaluation cycle.2) Setting all inputs (to next gates) to 0 during precharge address that concern. So, only 0 1 transitions allowed at inputs !
1) Without evaluation devices, when the first gate goes to precharge, the second gate has to wait for In2 to get to 0 since it fights against the precharge, which takes two inverter delays. More delay for later gates.
2) This also causes short circuit power consumption
np-CMOSnp-CMOS One dis-advantage is that P-blocks are slower than N-blocks due to low current driving strengths of PMOS (equalizing the delay imply more area)
May cause larger power consumption due to differential logic
Summary of logic stylesSummary of logic styles We have discussed Static complementary, Ratioed, Pass transistor and Dynamic logic styles
Which one to use strongly depends on the following factors: ease of design, robustness, area, power and speed.
No single style optimize all these metrics
Current trend is towards an increased use of complementary static CMOS logic style (somewhat due to the use of design automation tools at logic design level which requires that the logic be robust and complexity problem). Also, static CMOS is more amenable to voltage scaling.
Future trendsFuture trends To use multiple threshold transistors, low threshold for performance critical circuits and high-threshold for leakage control.
To dynamically adjust the threshold of transistor by adaptively controlling the body effect.
Voltage islands: different voltage at different blocks.
Layout preferenceLayout preference For layout density, it is desirable to realize NMOS and PMOS transistors as an unbroken row of devices with abutting source-drain connections and with gate connections of NMOS and PMOS aligned.
For this, it requires only a single strip of diffusion in both wells.
To achieve the goal, a careful ordering of input terminals is necessary.
Layout planning using Euler PathLayout planning using Euler Path A systematic approach has been developed to derive the permutation of input terminals so that complex functions can be realized by un-interrupted diffusion strips that minimize the area.
The approach has two steps, construction of logic graph and identification of Euler paths.
The logic graph of a logic function is a graph of which the vertices are the signals of the network and the edges are the transistors.
An Euler path is defined as a path through all nodes in the graph such that each edge is only visited once.
The Euler paths for PDN and PUN must be the same in order to use a single poly for each input signal
NotesNotes The above layout technique is for single finger transistors.
When it comes to one strip of diffusion but with each transistor having multiple fingers, layout further complicate and you may still be able to do so.
Also another constraint: tcd,reg + tcd,logic > =thold
tcd: contamination delay = minimum delayThis constraint ensures the input data of the sequential circuits is held long enough after the clock edge and not modified too soon by the new coming-in data
tc2q + tp,comb + tsetup <= T
Clock period T must accommodate the longest possible delay
Gain should be larger than 1 in the transition region
A
C
d
B
Vi2
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Vi1 5Vo2
A
C
d
B
Vi2
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Vi1 5Vo2
Hence, cross coupling of two inverters results in a bistable circuit, that is a circuit with two stable states. The circuit serves as a memory, storing either a 1 or 0 (A or B)
Bistable circuitBistable circuit In absence of triggering, a bistable circuit remains in a single state (static memory as long as power is on). Another common name for a bistable circuit is flip-flop
A FF is only useful when there is a mean to bring it from one state to the other one.
Two approaches can achieve that:
cutting the feedback loop, once the feedback loop is open, a new value can be written. This is called multiplexer based.
Overpowering the feedback loop, by applying a trigger signal at the input of the FF, a new value is forced into the circuit by overpowering the previous stored value.