반도체 용어 사전 완본

AABIOS(Advanced Basic I/O System)PC BIOS , ABIOS .

Abrasive PKG .

Absorption Constant () .

Absorption Dichroism ( ) .

Accel Mode ( 32-200KeV.)

AC CharacteristicDevice Timimg .

Acceptable Quality Level. Sampling, Lot Batch (variant unit) . (variant unit) () .

Acceptance Sampling . Sampling , Sampling , .

Acceptance Tests () .

Acceptor3 (hole;) 3 Acceptor .

Acceptor Level(Acceptor )

Hole P Level Acceptor Level .

ACI (After Cleaning Inspection) , , , CD(Critical Dimension : ) .

Active Matrix Drive ( ) contrast response . .

AccumulationMOSGate Bias silicon surface Gate Majority Carrier(, substrate Carrier) Density .

Accuracy, .

Active Element () . .

ADART (Automatic Distribution Analysis in Real Time) Program, .

A/D Converter (Analog to Digital Converter) "1" "0" . ADC .

Additive Process ( ; ) .

Address Pre-DecoderRow/Column Address Decoding Address Buffer internal Address AN, / AN Decoding .

Addressing Technology ( ) LCD -Addressing .

Adhesion WF WF . ( )

ADI(After Development Inspection) , Pattern , CD .

Agitation() WF

AGV(Automatic Guided Vehicle, ) Intra-bay cassette 6 . LCD lot .

AH (Absolute Humidity) .

AHU (Air Handling Unit) , , Particle .

Air Gun , .

Air ShowerFAB Line , box .

Alignment WF mask . Ali gner() .

Alignment Mark Align Align .

AlloySi AI .

ALPG (Algorithmic Pattern Generator) Device Data , instruction Coding

Alpha-particle He() U Th trace contamination IC , sillicon hole-electron pairs Soft error .

Al-TargetWafer Al() Al.

Ambient Carrier Gas (N2, O2, H2)

AMLCD (Active Matrix Liquid Crystal Display) .

Amorphous Silicon .

Amplification( ) .

Analog .

Analog IC IC .

Analog Memory

Analysis of Variance (ANOVA) .

Analyzer Wafer .

Anelva

(Al, Cu, Ti ) , .

Angstrom () 1 =110-8 cm H+ = 0.059210-8

AniconLTO(Low Temperature Oxide) deposition

Anisotropic Etching , () Isotropic Etching ( )

Annealing , Si N2 Ar gas Oxide quality bulk silicon defect damage cure .

Annular Ring ( ) .

Anode . .

ANSI (American National Standard Institute) .

AntimonyWafer , N Sb.

Anti ReflectPolycide silicon 11.0 photo pattern . SiO2 TiN silicide pattern TiN ARC .

Antistatic

AOQ (Average Outgoing Quality) lot lot . (AOQ)= LOT LOT >

AOQL (Average Outgoing Quality) : AOQ

Application Test() , .

APCVDAtmospheric Dressure CVD(Chemical Vapor Deposit-ion). (Vapor) , Gas Chamber .

APD (Avlanche Photo Diode) PN Photo Diod e.

AQL (Acceptable Quality Level) Sampling lot , lot .

ArArgon Gas

Arc Chamberlon .

Arc CurrentPlasma Bean Arc Chamber

ARL (Acceptable Reliability Level) .

Array Device .

Array LogicFILP-FLOP, NAND, NOR, Diode Logic Circuit Array () Device.

Artwork Master Film 1:1

As (Arsenic)

Ashing/ (Dry Strip) .

ASIC (Application Specific IC) (), () IC , IC .

ASIC Memory Memory. Computer Multi-port Video RAM(VRAM), data cache memory , dark memory . Frame memory Line memory . Dual-port memory FIFO(First In First Out) .

ASIC miconUser 1chip micon. microprocessor microcontroller CPU(CPU core ), CPU, ROM, RAM, Random Logic User system 1 chip . User , , , .

Aspect RatioStep Coverage .

Assembly .

ASRP (Autoexec Spreading Resistance Probe)Silicon Wafer .

Assignable Cause .

ASSP (Application Specific Standard Product) IC. user IC, , IC , Printer controller .

ATE (Automatic Test Equipment) Test .

Au-Bond (gold ball Bond) Bonding

Auto-Doping .

Auto Loader (FAB, TEST, ASS'Y) .

Automatic Loading SystemCarrier Wafer .

Auto TransferWafer Boat Loading Unloading .

Auto Transport System ( ) computer system System.

Av Voltage Gain,

AV TFT-LCD(AUDIO-VIDEO, TFT-LCD), TFT-LCD 1.1 inch 12 .

Avalanche breakdownPin Diode (reverse bias) breakdown Zener breakdow n mechanism doping Junction transition region Field electron electron-hole pairs impact ionization mechanism carrier Breakdown .

Avalanche Injection Diode P+ N+ Diode

Avalanche Transistor TR TR OFF Avalanche Breakdown ON .

Average Outgoing Quality Level (AOQL). sampling , (AOQ) .

A.W.W (Acid Waste Water) .

Axial Fan Fan Clean Room , .

BBackward CurrentPN .(Reverse Current )

Back Flow Effect ( ) .

Back Grind ( ) Wafer , Fab.

Back Plane .

Back PanelFab. Line Bay Room PVC Back Panel . , Particle Room .

Back Seal Oxide , Wafer Outdoping Wafer .

Back Side Grind. Wafer Wafer Get tering .

Back Seal MarkingDevice Marking lot Fab. Site lot# Device Marking.

Back-Annotation layout layout ( ) simulation .

Back-Up System , Gas .

BaffleGas control .

BakeWafer Pre-Bake, Hard-Bake, Soft-Bake . 1) Pre-bake : Wafer Resist Wafer 15010 Oven Wafer 2) Hard-bake : Etch Wafer Resist 3) Soft-bake : PhotoResist

Base ArrayASIC Process Gate (2 Input Nand gate or 2 Input Nor gate) userable gat e array LSI .

Base Line Spec process flow .

Base Line FAB

Base Material ()

Basic Dimension () .

Batonnet .

B/B Ratio (Book to Bill Ratio) 3 3 WSTS( ) Da ta . , B/B Ratio .

BC (Buried Contact)POLY1 N+ Active contact POC 13 doping .

BCD TechnologyBipolar, CMOS, DMOS , Bipolar , CMOS digital logic DMOS . (BCD system reliability .)

BCG Approach(Boston Consulting Group Approach) , (SBU) 2 , . .

BCR (Bar Cod Reader)Bar Code .

Bean LineSource lon Beam .

Beam Mask Beam , Wafer .

Beam Spectrum , .

Behavioral DescriptionSystem input output computer language . VHDL(very high speed hardware descri-ption language), HDL .

Bench Test Test Pattern Die DC Probing Electric al Paramet-er

Bent Lead () 45 .

Bias. () System error.

BiasTR 0 0 Bias .

Bidirectional Buffer signal voltage level , sense AMP data ext-ernal load driv e Buffer.

Bipolar(electron) (hole) ( Transistor )

Bipolar TR TR NPN Type PNP Type 2 . Emitter, Base, Collector 3 , Base Emitter Collector . Transistor Bipolar IC .

BI-MOS MOS Chip .

BiCMOS (Bipolar-CMOS)Bipolar Transistor CMOS Transistor Chip IC. Bipolar Transistor , CMOS .

Binary Number System (2) 0 1 .

B/I (Burn-in)

( 83, 63 ) .

Bin . ) Bin 1-, Bin13-, Bin 15-Parameter .

Bin 1 CheckTest .

Bin Grade DownTest Step Good Device speed power .

Bit LineMemory data data data .

Bit MapMemory CheckMemory Data Cell ( Cell )

Bit Mapper , Fail Point Address Fail F/A Tool.

Bit Fail Device Test Random Address Cell Fail .

Black & White SPOT , pinhole seak .

Black Hole F/A Contact Contact Pattern Poly or Metal Pattern Misalign Over Etch Contact Overap Contact Edge Chemical Contact Defect.

Black Stripe SM

BladeWafer .

Bleeding () . .

Blister .

Block FactorsBlock. Block Block Block .

Blow Hole (Solder).

BN WaferBoron Wafer Boron Wafer Wafer.

BN BN Wafer Tube 375 N2 .

Boat Wafer SiC Wafer .

Boat HolderBoat Poly-Si .

Bonding wire bonding Chip PAD .

Bond Diode

Bonding Layor ()

Bonding Pad

Chip wire bonding .

Bond Strength () .

Bottom Up Design Primitive Cell Circuit Level, Logic Level, Architechure L evel IC .

BoulderFAB Diffusion .

Bow () Wafer Wafer film

BPSGBoron Phosphorus Silicate Glass flow (850 Vis-cosity ) . Oxide Film B,P .

BPT (Bond Pull Test) bondability GRAM weight gauge ball stitch bond .

Bread BoardIC IC IC

Break-DownPN Breakdown . , avalanche br eakdown zener breakdown .

Breakdown VoltageP-N Diode Breakd own .

Break-UpHalf Cutting Wafer Full Cutting .

Bridging .

Broken () Wafer Quartzware .

BT Stress (Bias & Temperature Stress) Bias() Stress .

BT Test (Bias and Temperature Test)TR, Diode Bias .

Bubbler (D-I Water) Wafer .

Bubbler Memory, .

Buffer .

Buried LayerTransistorCollector Collector .

Buried Via Hole

Burr. Trim Lead .

Burn in (85 ~ 125) Device Stress Test , IC (Reliability) , Pa rameter Over Stress Test.

Burner .

BurntBurn-in Device Stress High Current Device Device .

BVcob (Collector-Base Breakdown Voltage with Emitter Open) Open - , Collector Base Breakdown .

BVcer (Collector-Base Breakdown Voltage with Specified Resistance) - .

BVces (Collector-Emitter Breakdown Voltage with Emitter Short-Circuited to base)- Short - .

BVcev (Collector-Emitter Voltage with Specified Reverse Voltage Between Emitter And base)- - .

BVebo (Emitter-Base Breakdown Voltage with Collector Open)Collector open -

CCache DRAMCache ( data buffer ) SRAM Regist DRAM , DRAM SRAM . Main Memory CPU .

CAD(Computer Aided Design) ( ). IC, LSI LSI computer , Simulation, , Device , , , Mask Pattern, Test Pattern Step CAD . .

CAD Software CAD Program .

CAE(computer aided engineering)CAD System ( (Simulation) Tools). CAD , CAD Computer CAE simulation , CAE CADCAM En gineering .

CAM(Computer Aided Manufacturing) , CAD system NC(Numerical Control: ) . Computer LSI LSI , CAM . CAD Master data test data Process data . CAD CAM Computer s ystem CAD/CAM .

Capacitance .

Capatiance Voltage CharacterisMOS . , , , MOS , silicon , , .

Capacitor ()

CapillaryWire Bonding Chip Lead Frame Load Wire .

Capture Center .

Carrier (, )

CarrierWafer 25 . (Blue Carrier), (Black Carrier), (White Carrier), (Metal Carrier) . 1) Blue Carrier : Poly Propylene , 2) White Carrier : Teflon , .

Carrier Generation carrier . Valence Electron Conduction Band Electron Hole Carrier Generation.

Carrier HandlerWafer .

CartWafer strage box .

Cascade3 (DIW) Wafer .

CAT(Category)Bin .

Cavity PKG PKG .

Cavitation pump , , .

CBIC (Cell Based IC)MASK CAD S/W Library .

CBR (CAS Before RAS)RAS Low CAS Low Refresh .

CC (LIM Central Controller)STC stocker cassette .

C&C (Computer and Communications) .

CCD (Charge Coupled Device)(). .

( ) 2 . ( ) .

CCM(Cell Control Manager)Factory Automation System Host Level program() .

CCST (Constant Current Stress Time)Dielectric Film Life Time TDDB(Time Dependent Dielectric Breakdown) . CCST 100 Plate Poly Dielectric Film Breakdown .

CD (Critical Dimension) . 1) ADI(After Develop Inspection) : Wafer . 2) ACI(After Clean Inspection) : Wafer Strip .

CD-ROM (Compact Disk Read Only Memory)CD() Disk.

CDI (Collector Diffusion Isolation) IC .

CellRAM ROM IC Transistor, Capacitor, Resistor 1Bit .

Cell Boundaries. . data .

Cell Deviations(d) , , A data . A Xm . . Xm=A d=0. A "+", A "-" .

Cell GAPLCD , .

Cell IMPMask ROM Bit Implant . P-Well Boron TR compe nsate .

Cell Interval(i) (). .

Cell Library function primitive cellNAND, NOR, XOR Cell Logic sy-mbol, Electrical dat a Layout .

Cell Midpoint(Xm) , . .

Ceramic .

Cer-DIP(Ceramic Dual In-Line Package) Ceramic Lead PKG.

Certification .

Centeral Line. .

Chance Cause(Random Causes), , , .

Chance Variation (Random Variation) .

ChannelMOS Transistor Gate . P-Channel, N-Channel .

Characterization Testing , . Test Time Data .

Charge

Charge Coupled Device(CCD) .

Chip ( 0.5~ 10mm) (Die ). , , .

Chip Select LSI LSI .

Chip-SetSystem component(TTL, Contro-ller, PLL) Chip . chipset system solution software .

Chiral .

Chiral Nematic Phase . cholestric .

Chiral Pitch . .

Chokralsky MethodChokralsky .

Chromaticity() , , 3 , .

Chrome MaskMask chrome() Mask.

Chuck , Wafer Test Wafer Prober .

Chuck Table Wafer .( )

CIM(Computer Integrated Manufacturing) , , . , , , Computer .

Clad (Base Material) .

Clamp Pressure , .

Clean Class () Particle . 1M DRAM 0.1 m Particle . 0.5 m Particle .

CleaningWafer Carrier (D.I Water) .

Clean Paper .

Clean Room() , Particle .

Clearance Hole Hole.

Clinched Lead .

Clock Pulse 1 AND Clock Pulse .

Cluster .

.

C-MOS(Complementary Metal Oxide Semiconductor) N Channel, P Channel MOS Transistor Noise Margin .

CMOS Logic TTL CMOS Logic IC Family, Family NAND NOR Gate, Filp -Flop , Bipolar Logic IC CMOS Logic .

MOSClocked CMOS, CMOS.

C-MOS LOT .

CMS(Central Monitoring System) .

Coating, Wafer ().

COB(Chip on Board)PCB Board Die .

Cob(Collector Capacitance) Collector-Base PN .

BubblerWafer .

Co-ProcessorMain processor instruction . Main processor , floating-p oint math-co-processor, graphic graphic coprocessor .

CODEC (Coder and Decodr)ADC DAC one chip IC.

COG (Chip On Glass) , , .

Cold Solder Joint .

Cold Test (-18 )

Collector Transistor .

ColletChip Lead Fram Expanding Tape Chip Lead Frame .

Column , .

Column Fail Device Test Y Address, X Address Cell Fail .

Combinational Circuit () NAND, NOR Digital

Common .(Ground)

Comparator , TTL Logic IC .

Complementary Circuit ( ) TR .

Compound .

Compound Semiconductor .

Component () . .

Component Density ( ) .

Component Pin ) .

Component Side () .

Compound Device. 2 .

Compressor .

Computer Network . 1 .

Condenser() 2 .

Conductance . Y Y-G-jB G . .

Conduction Band () , .

Conductivity ( ) .

Conductor () ( 10E 6 ~ 4cm )

Conductor Side () .

Conductor Spacing () .

Contact (TEST) Continuity Test , tester interface device . Test IC pin protection diode .

Contact Potentia () .

Contrast Ratio . .

Concuctor Width () .

Conformal Coating .

Confounding, block () .

Connector Area () .

Console () .

Contact ResistenceMetal Wafer .

Contact Spacing () .

Contact SpikingAI P/N Alloy Junction Junction Spike Alloy .

Contamination.

Control Chart .

Control Chart-Standard given .

Control Gate2 Polysilicon Stacked Structure Non-Valatile Momory Gate , Electrode Bias Program Erase .

Control Limit. data

Continuous Sampling Plan Sampling. , sampling sampling .

Conventional MemoryDOS Memory 640KB Base Memory . Expan ded Memory Extended Memory .

Converter . .

Cooker Test TR, Diode, IC .

Coplanar Structure .

CoreEmbedded IC Micro-Operation ALU CPU Block (Peripherals) Core .

Correlation .

Corrosion() AL Etchant Gas Al2O2 Metal

Cosmetic Appearance() A Instrum ent panel , E (car -audio), B Game .

Convalent Bond() . .

Cooling Wafer (CW)

CPO (Customer Product Operation) Device Test Customer Special Spec .

CPU (Central Processing Unit)Computer , .

CPU CoreLSI Microprocessmicrocon- troller, standard cell SOG Gate Array

library , user system ASIC Micon 1chip

Crack. , stress Chip, PKG .

CradleChip Mount , .

Crazing .

Critical EnergyIon Beam Energy mask Implant Energy .

Cross Section() Layer Pattern Layer .

Cross Talk .

Cross-overIC .

Crow FeetWafer .

Crystal Osillator .

CTN(Complementary TN) LCD

CUM Graph(Cumulative Graph) data data data . Water die data Die (element) Data (Wafer) .

Cumulative Frequency Distribution . .

Cure, PKG .

Custom IC. IC.

Customer LayerASIC process gate array base array process user gate process .

CUT-OFF Frequency .

Cut Stroke .

CV(Cleaning Vacuum) .

CV(Count Variance).

CVD (Chemical Vaper Desposition)APCVD, LPCVD Wafer Poly Nitride, PSG, BPSG, LTO .

C-V Plot (Capacitance Versus Voltage Plot)Wafer , (, , , ) .

CVST (Constant Voltage Stress Time) .

CycleFunction Test Device .

Cycle Time

.

CRT(Cathode-Ray Tube) .

Cryo-Pump Gas .

CQ(Conditional Qualification) .

CTE(Coefficient of Thermal Expansion) .

CTM(Clean Tunnel Module) Hepa Filter Clean Room A Class . 0.3m/s 700/h. Granting Down Flow Clean , Hepa Box .

CTS(Computerized Typesetting System) , .

CU(Control Unit)Timing. .

Culvert, .

DD(Demerit)Quality score . D-A (Digital to Analog Converter) Analog .

DA(Die Attach)

Die Lead Frame

DAC(Digitaaal to Analog Converter)Digital Analog . Hi-Fi CD player 16bit D/A convertor .

D.C CharacteristicDeviceStatus Current , Device Status .

DAD(Digital Audio Disk) Disk .

DAE(Dynamics Asian Economies), , , .

Daisy Chain LSI

DambarPKG Lead Bar.

Dark Current() .

D.A.T.A Derivation And Tabulation Associates Inc. .

Data Line on-off .

Data Retention Mode (DRAM/SRAM) power-off battery back-up circuit

DC(direct Current) .

DC CharacteristicDevice Status current , DeviceStatus .

DC Parametic TestingSteady state test OHM . / / . DC test (ICC), (leakage test), (VIL,VIH), (VOL,VOH) .

DC PDP (Direct Current Plasma Display Panel) (lonized Neon-Argon Gas , .

DCW (Dry Cooling Water)FAB Cooling Coal .

DD (Double Die) Die.

Debug, . Debugging, Screening, BURN-IN .

DebuggingTest Plan .

Decay Time 100% 10% .

Decel Mode lon ( 0-33kev)

Decoder2 (Decode) (10 ) 2-10 Decoder . Encoder

Defect () product service . defect . 1) Class 1 : . 2) Class 2 : . 3) Class 3 : . 4) Class 4 : .

Deflash

Compound .

Defocus ( ) (P/R) .

Delamiantion () .

Delay TimeTR Switching () 10% .

Demo Wafer .

Demutiplexer data () control .

Dent .

Depletion DeviceMOS FET Gate Channel .

Depletion Layer() PN P HoleN . .

Depletion Mode TR Bias .

Depletion TypeChanneldeplete . channel .

Deposition CVD , Si Film() (Oxide, Nitride) .

Deprocess strip back defect site .

Descum (scum) .

Design KitElectrical/Physical ASIC modeling layout database Electricla Design Kit . (: Mentor Design Kit, Verilog Design Kit)

Design Rule .

DevelopMask Align expose Pattern .

Development. Pattern .

Device()()

Dextrotatory () .

Dewetting .

DF (Die Fabrication)Wafer mount dicing saw .

Dichronmated Gelatin Dichomated gelatin .

Dicing Wafer ( )

Dicing SawWafer Die (Chip) diamond wheel.

Die Attach Die Lead Frame .

Die BusinessProbe Test package Good Die wafer wafer Good Die .

Die Bonder (chip) , IC .

Die BondingIC Chip . , .

Die CoatingDie .

Die ColletDie Die . .

Die Pocket Die . .

Die SawingWafer chip .

Dielectric Constant() .

Dieletric Isolation

IC Electrical . (), Poly -Si, Ce -ramic .

Diffused Resistor diffusion .

Diffusion (Wafer) B (boron;) P(Phosporous;) .

Diffusion CapacitanceDiffusion Junction Capacitor .

Diffusion Current E-filed/ Current Carrier .

Diffusion Furnace

Diffusion LengthCarrier Carrier Carrier . Life Time Carrier diffusion length .

Diffusion Pump gas .

Diffusivity .

Digital(DIC)Analog "1" "0" (Digital IC)

Digital IC "1" "0" digital IC, MOS IC Bipolar digital I C , logic IC Memory IC . ,, .

DigitizingMask .

Dimenrization() .

Dimension

DIMM(Dual In-Line Memory Module)PC Memory module PCB pin .

DimpleWafer .

Dimentional Stability( ) , , , .

Dimentioned Hole () .

DINDeionized Water .

Diodedi-electrode 2 . 2 , , .

Diode Array .

Diode Ring Structure .

DIP(Dual Inline Package) IC , (Chip) .

DiscolorWafer FAB Pad .

Discrete(IC) . TR, Diode, , Discrete .

Discretional Array MethodLSI 10 100 (Cell Unit Cell ) Cell .

Discrete Device , Transistor , Diode .

Discrete Product Diode, Transistor, (Rectifier), (Thyristor) , .

Discretion Wiring-ApproachWafer , Wafer Patt ern LSI .

Display Device, .

DIW (Deionized Wafer) , Wet .

D-I Water (De Ionized Water Semiconductor grede Water) , Wafer .

DLM2 Metal Layer . 1 power routing line 2 rounting line .

D-MOS(Double DiffusionMetal Oxide Semiconductor) channel length , MO S .

DMA (Direct Memory Access) CPU data

DMAC(8237A) DM A data .

Domain cell .

Donor N-type P, As, Sb .

Donor level N donor . (Forebidden band) level Donor Level .

Dope (, ION IMP-LANTATION ) .

DopantDope .

Doping (Wafer) P-type N-type .

Dope OxideDoping layer Oxide.

Dosage .

Doselon lmplantation dose , .

Dot-Clock Signal .

DPLL(Dull Phase Locked Loop)PLL 2 PLL PLL DPLL , Digital PLL .

DRAM(Dynamic Random Access Memory)Capacitor Cell device CAP Charge Refresh Cycl e . Refresh RAM (capacitor) , Memory leak , Refresh . DRAM SRAM memory cell memory .

Drain TR(FET) , . TR, TR .

DRC/ERC/LVS DVP-Circuit Layout Design Rule, . 1) DRC(Design Rule Check) ; Layout Data (Metal , ) Check 2) ERC(Electrical Rule Check) ; Check. 3) LVS(Layout vs Schematic) ; Layout Data Circuit .

DressingWafer (Blade) Dressing .

Drift "0" .

Drift Current Extrinsic Semiconductor E-Filed Current Carrier Drift Velocity v= E ( :M oblity, E:Electric Filed) .

Drive-InDeposition B() P()DMF wafer (Furnace) .

DriverDevice , .

Driving Fregurncy .

Driving Voitage

.

DRO(Destructive Read-Out). .

Dross() .

DRT(Device Reliability Test)" " (Quality Approval Test) .

Dry Etch , Gas(Plasma) .

Dry Process TR, IC beam .

DST(Die Share Test)Die Die Attach Die Frame pad .

DT(Down Time) .

Dummy WaferTube Uniformity Wafer Wafer Wafer Wafer

Dumping-ZIG Carrier wafer carrier .

DUT(Device Under Test) . test , DUT Board .

Duty Cycle refresh rate 60Hz .

Duty Ratio .

Dyed Polyimides (polyimide) .

Dynamic Shift RegisterMOS Shif Register .

Dynamic RAM(Dynamic Random Access Memory; DRAM) "1" "0" .

Dynamic Scatting Mode ( ) . . .

DynascopeWafer 0.1mm . ( ) , , .

DW(Diffused Wafer)

EE/Post SimulationSimulation layout esti-mated wire capacitance Pre Simulation la yout actual wire capacitance Post Simu-lation .

EA (Exhaust Air) GAS , , , , , .

EAROM (Electrically Alterable ROM)EPROM .

EBE (Electron-Beam Evaporation)

Beam Wafer() .

EBR (Edge Bead Removal)Wafer particle .

ECC (Error Check & Correction)ROM device repair column row program RAM Redency . logic column row fail column row . MASK ROM DRAM Module .

ECC(Error Correction Code)(Error Checking Code) , .

ECC Mode (Error Catch & Correction Mode)Memory Module Parity Bit 2Bit Error Memory Module .

ECL (Emitter Coupled Logic)CML(Current Moded Logic) . Bipolar Transistor ( ) . Transistor Emitter Emitter Coupled Logic .

Edge Board Connector .

Edge Board Connector .

Edge Definition () film .

E/D MOS (Enhancement-Depletion MOS)Enhancement MOS Depletion MOS .

ED (Electronic Data Interchange) EditingCAD System CRT Layout

.

EDO (Extened Data Output)DRAM data access fast page mode /CAS signal inactive high valid data /CAS signal low active data . fast PAGE MODE TPC(fast page mode cycle) speed . .

EDS Wafer .

EDS TestWafer (chip) .

EDS YieldEDS test : (Good Die / Net Die)100

EECA(European Electronic Component Manufactures Association) .

E-E PROM(Electrically-Erasable PROM) off data . Parallel data Intel Type Seria l data NEC Type . Tunneling Erase Programming In-System 2 Transistor 1 cell EPROM .

Elght Nines9 8 . 99.999999% .

Effective Channel LengthMOS Source Drain cha-nnel Gate length . EL ()(ELECTRO-LUMINECENCE) . 1936 DESTRIAU 2 .

ELD (Electro Luminescent Display)PDP COLOR .

ELD .

Electroless Deposition ( ) .

Electrical TestProcess Wafer Passivation Test Pattern Test Test (, wafer mapping)

Electron Beam Exposure System Beam mask pattern system, mask pattern pattern pattern generator , , . LSI pattern data algorithm , EBMT( tape) Beam on/off, aperture pattern . ASIC sample needs . mask wafer Beam .

Element () .

EllipsometerThin Film (Polarization) .

Electron Beam Exposure ( ) ( ) photolithography .

EM (Electromigration) Metal Quality .

EmitterNPN,PNP Transistor .

EMM(Emission Microscope Multilayer Inspection) Electron Hole recombination photon leakage current FA .

Emulsion MaskMask , Emulsion() Mask.

EncoderDecoder . (10 2 )

End Point DetectionEtch Wafer plasma Etch stop reference .

End SealLCD

End Stationlon wafer .

Endurancedata program erase .

Energy Band Energy .

Energy Gap energy gapdlfkrh .

Energy Level . . .

Enhancement DeviceGate Channel MOSFET.

Enhancement Mode TR (FET) Gate bias .

Entity () .

EOH (Ending on Hand) ( ).

EOP (End Of Point) plasma .

EOTC(European Organization on Testing and Certification)

EPD (Etch Pit Density) Etch Pit . End Point Detect Etch Etch Etch .

Epi (Epitaxial Layer) . Bipolar Transistor Epitaxial Layer .

EpitaxialEPI-TAXIAL " " . Substrate Substrate .

Epitaxial-Growth () Substrate .

EPM (Electric Parameter Monitor) test pattern , .

EPM Standard Sub Program EPM .

EpoxyChip lead frame .

Epoxy Dispenser Epoxy

EPROM(Erasable Programmable Read Only Memory) ROM . programm- able ROM, Program IC Package glass . bit .

EPS(Experimental Plan Sheet)S/N RUN SPLIT

Equip(Equipment).

EraseEPROM EEPRO Floating Gate Tunneling Bit . EPROM Floating Gata discharge EEPROM Floating Gate .

Erase GateErase Gate 3Polysilicon Split Gate Flash E(E)PROM Erase Gate Electrode.

ERC(Electrical Rule Check) check .

ERC(Electrical Rule Check)Layout , .

ESD(Electro Static Discharge)

ET Part(Extended Temperature Part) Memory Device 0 ~ 70 Device 40 ~ 85 .

Etch Back , .

Etch BiasPhoto etch pattern .

Etching. Silicon wafer chemical gas .

Etching Selectivity( ) SX

(plasma) .

Etch Factor .

Etch Rate. A/min .

E-Test (Electrical Test)Process Wafer Passivation Test Pattern Test Test.

EvaporationWafer AI, Au() .

Evaporatorbeam wafer .

EventEvtity Start, End, Maintenance .

Evolutionary Operation(EVOP). .

EWS(Engineering Work Station) CAD Design Tool system system.

Excess Electron () .

Excite () . pumping .

Exclusive Effect 2 . . , .

Exclusive or Circuit "1"', "0" "1" .

Exoending TapeWafer 360 tape.

Expose() P/R wafer pattern aligner .

External Visual Inspection .

Exposure, WF mask . mask p attern .

Extraction VoltageLon Source lon Beam .

Extrinsic Semiconductor(lntrinsic Semiconductor) (3, 5 )

Eylet .

FFAB (Fablication)Wafer .

FAB Process Wafer diffusion, thin film, photo, etch .

Factor, .

Fail Memory Device Function Test Device Device

Falg . . tag .

Fail Time() TR off collector on 90% 10% .

Fan coil unitcoil .

Fan Out CapabilityDevice data current drive .

Fan-In .

Fan-Out .

Farad . 1F 1 volt/sec 1A .

Fault CoverageSimulation simulation vector % access output simulation vector .

FCU (Fan Coil Unit), .

FDM (function data module) (function data) module.

Fermi Energy

energy energy . energy - . 1/2 F .

FET ( Transistor:Field Effect Transistor) carrier ( ) Transistor. carrier Bipolar Unipola() Transistor .

FFU () Fan Filter Unit

. fan filter filter fan clean

Field oxideactive active .

FIL (Filament) .

Fill Factor

Filter ()

Final test (/Class Test) .

Finder CoatWafer .

Fire Damper (F.D) Duct damper 70 fuse damper.

Film Ware software ROM .

First Acticle ()

.

First MinimumGooch & Terry 0 .

Fixture .

Fixed Oxide Charge (Qf)Oxidation , , Cooling silicon Oxide charge.

Flat PackIC .

Flat-Zone Alignercarrier loading wafer(flat-zone) .

Flash EEPROM EPROM EEPROM EPROM EEPROM , EPROM, EPROM . Memory Device block . flash memory NOR, NAND NOR EEPROM Hot Electron , NAND . . Memory har d disk .

Flat Zone ( ) Wafer cut .

FLC . . .

Flexible Strength,

Flip-Flop2 (on off) .

Flicker

.

Floating GataMOS TR Floating Gate .

Floor plan chip layout block layout layout block .

Flux .

Forbidden Band () . .

Forming DieForming I.C. ead frame lead frame .

Forming Gas1) Die Attach wire bonding H2 N2 Gas. 2) FAB(, ) Gas.

Forward () PN P +, N .

Forward Current ( ) PN .

Forward Voltage ( ) PN PN .

Four Layer Diode (4 Diode) PNPN 4 Diode.

Four-Point Probe sheet .

FOX (Fast Oxidation)(0~25) Hipox . (High Pressure oxida tion)

FPGA (Filed Programmable Gate Array) program chip CAD .

FPO (Finish Process Order) lot lot 1 lot flow , lot FPO lot . .

FQ (Full Qualification)Customer .

FR (Failure Rate)" " .

FRAM (Ferroelectric RAM) . , memory cell RAM SRAM DRAM data . EEPROM data .

FrameReticle/mask Alignment PatternProcess item Sawing Scribe line Alig nment . Scibe li ne Align key Process inspection Pattern .

Frame RingWafer tape .

Free Election ()

Freon

.

Freedericks () . Hc .

From/To chatInter-bay intra-bay simulation chart.

FSTN(Film Super Twist Nematic)DSTN . FSTN DSTN .

FTA (Fixed To Attempt Ratio) Wafer repairable fuse cutting .

Full-Auto host AGV CST LOAD/UNLOAD .

Full Custom Tool Chip IC. MOS tran -sistor level . Simulation, opti -mization Chip Area layout .

Full Cutting, (tape cutting) Wafer (95~100%) .

Function Test.Device Formater Device .

F.W.W(Flouric Waste Water) .

G

GaAs(Gallium Arsenide) , silicon . III-V Si 5~6 , device . UHF SHF GaAs FET, micro anlog IC, Diode, laser, .

Gas Scrubber gas .

Gate transistor , 2 MOS transistor bipolar transistor base .

Gate Array NOT-Gate, AND-Gate, OR-Gate, NOR-Gate, NAND-Gate Transistor logic . semi-custom digital IC. cell master wafer user Timing Chart Data CAD . Gate Type Chip Gate Gate SOG(Sea o f Gate) G/A .

Gate oxideTR 2 , insulator , MOS TRGate

Gel .

Gettering , , Si-SiO2 .

GIDL (Gate Induced Drain Leakage) Gate oxide breakdown voltage drain substrate leakage current gate drain field drain deep depletion band , ba nd tunneling drain junction inpact ionization EHP drain hole substra te leakage current .

Glass Substrate . .

Gm (Transconduction)Gate Source Drain . = Bipolar TR ()

GN2 (General N2) N2. Purge .

GO/NO GO TEST (pass) (fail) (GO), (NO-GO) . Wafer Die Package Device / Test . Test Program Program.

GOI (Gate Oxide Integrity)Gate Oxide . (BV,) . GOI System In-Line Diffusion Oxidation Tube, Recipe, W/S Electrical Stress Test .

Grade JunctionPN P N . P N P N .

GratingClean Down Flow Lamimar Unit floor . Ac cess Floor . . Aluminum . .

Grain () .

Ground Gate ( ) TR(FET) 3 Gate (Common Gate) . .

Guard RingPNPTR P N , P

. P . BAND GUARD .

Guard RingsCMOS Latch-up Pattern Ring .

Guest-Host Effect . . , .

HH.A.L(Host Solder Air Leveling)P.C.B .

HandlerPackage Ttest Test system(Tester) .

Half CuttingWafer 70 ~ 80 % .

Halide 2 . .

Hard Fail defect .

HCT (High Speed C-MOS TTL) C-MOS TTL LSTTL ( ) Com-puter computer CPU, Menory, IC .

Heat Sink Plane () .

HEMT (High Electron Mobility Transistor) Transistor , GaAs , FET GaAs undoped GaAs, N AIGaAs , AIGaAs Channel .

Hepa BoxClean Room Hepa Filter Box.

HEPA Filter (High Efficiency Particulate Air Filter)Clean Room Filter . (0.1 m - 99.9995 %)

Hetero Junction P N PN Junction . P N . 2 HETERO Juction .

High Power InspectionWafer Die

Hfe(DC Current Gain)Emitter .

HierarchyLSI Design Design .

High Pressure Cleaner Wafer CO2 D-I Water .

Hillock .

HMDS(Hexa Methyl Di Silazane ) Wafer Wafer Primer( ) .

H-MOS(High-performance MOS) MOS IC N-NOS MOS.

Hold Time data tCAH(Column Address Hold Time) tRAH(Row Addres s Hold Time), tDH (Data Hold Tome) .

Hole. .

HOPL(High Temperature Operating Life Test)" " 125 Oven 7.5(V) Bias, 1000 " " .

Hot DI water DI water(85), Wafer .

Hot RunRUN(lot) RUN . Normal RUN RUN.

Hot Test Test .

Hot Electron . ( ) . . Hot Electron .

HP4145Wafer level DC Graphic Bench Test T ool.

H/S (Heat Sink). PKG .

HTO (High Temperature Oxidation). . (900) Si Wafer , Si Wafer SIO2 .

HTRB (High Temperature Reverse Biase)

" Bias" Device Bias Oven .

HTS (High Temperature Storage)" " (125) Oven Device .

HVAC (Heating Ventilation and Air Conditioning) , () .

Hybrid-Circuit , , .

Hybrid I.C (THIN FILM) (THICK FILM) I.C , I.C . IC ,, , .

II-line stepper 365 nm

IC (Integrated Circuit) 2 , , .

IC Memory TR MOS F-F Memory(cell) IC.

IC Tester ( ) IC . ATE (Automatic Test Equipment) .

IdsMOS TR Source Drain .

Ie (Emitter Current)

IEC (Integrated Equipment Computer)

. (Integrated Injection Logic) Bipolar Transistor PNP Tr-ansistor NPN Transistor . Bipolar Logic IC . PNP Transistor NPN Transistor N P . Gate . Analog. Digital Bipolar IC Digital . (Isoplanar Integrated Injection Logic) .

ILT (Infant Life Test) () 48. Burn-In .

Image Sticking() ghost .

Impact Ionization Electric Field Electron Atom Electronhole Pair .

Implanter( ) wafer , , 3 .

Implanting () wafer B() P() Implanter .

Impurity , P N . P: B, AI, Ga, In N: P, As, Sb

Index Feeding Lead Frame .

Index Register Address Register.

Induced Cholesteric Phase . .

Induced Smectic Phase , .

Indum arsenideInAs, III-V .

Initial OxideSi Nitride Tensite Stress(1109 Dyne/cm2) , Buffered Oxide . , Oxide Bird's Beak .

Injection() PN .

Ink .

InkerWafer Ink .

InkingPackage Package Wafer Inking .

Inorganic Filter .

Input Buffer Signal voltage level .

Input LevelDevice De-vice (High, Low) .

Insulator .

Inter-bayBay Bay Clean Way (AGV, Track) .

InterfaceAmp Computer . Inter Metallic Compound( ) .

Intra-bayBay AGV Track .

IntrinsicP N , P N .

InversionMOS FET Gate PN Type NP Type .

Inversion Wall() . , .

Inverted Staggered() source .

InverterDigital Circuit 10 01 .

Ion Beam Lithography Optic, X-ray, electron beam Lithography . Ion Implantation .

Ion InjectionSilicon lon .

Ion Shell () .

IPA (Iso Propy Alcohol) .

IPO (Inter Poly Oxide) Poly Si Poly Si Oxide.

ISO-PlanarPlanar .

Isolation Chip TR, Diode Isolation .

Isolation Diffusion N Epi P Sub-strate . Epi .

Isotropic Etching . () .

Isotrophic Phase () . ..

Isolation in IC .

Isotropic

ITO(Indium Tin Oxide)

. (In2O3, SnO2) .

JJ-FET(Junction FET)Depletion Mode Source-Drain lon Gate Gate Drain FET(Filed Effect Transistor) .

Jig .

Junction . Junction Depth (Xj) Silicon Diffused layer background .

Junction DiodePN Diode

Junction Transistor ( TR) 3 ( PNP NPN) TR.

Junction SpikingMetal-Silicon contact Metal Silicon

Jungle-Box Gas Gas Flow Meter(MFC) GAS .

KKerf(). Blade .

Keying Slot .

LLabelling() Wafer RUN Tube Diamond pen .

Laminar Flow Station Filter .

Laser Diode PN . PN .

Laser Interference MethodEtch Wafer Laser .

Laser Repair Data ( ) laser data( ) .

Laser Scriber Wafer Die .

Laser TestYield Fuse Laser

Lasera .

Latch

Latch UpCMOS , ionizing redation Turn on .

Layer IC Si-Wafer (Insulator, Conductor) Photo/Etch Pattern .

Layout PlotLayout Hard Copy C-MOS LSI THYRISTOR TRANSISTOR IC .

L/B (Loadboard)Test System Jig.

LC (Liquid Crystal) . . " ".

LCD(Liquid Crystal Display) .

LDD(Lightly Doped Drain)Doping , Device .

LDMOS(Lateral Diffused MOS) MOSFET Source Drain .

Lead Finshing Lead (Tin), .

Lead FrameTR, Diode, IC Sawing Die Attach . Alloy42 , Copper, Kovar, Steel IDF TTT .

Leak Pin Pin .

Leak Current .

Leakage Input tristated output open circuit high impedence . leakage voltage input triasted output current input leakage triasted leakage .

LED(Light Emission Diode) Diode. (PN )

Legend() .

LF(Lead Frame)Chip .

LibraryGate array Standard cell .

LIM(Linear Induction Motor) 1 , 2 Motor.

Linear IC IC , , .

LIPAS(Line Item Performance Against Schedule) .

Liquid Crystal () .

Liquid Phase Epitaxy () . Ga, Sn .

LN2(Liquified N2) N2 GAS, .

LoaderStocker Station Cassette Unit.

Load CircuitTest Device Application , Cpacitance Circui t.

LoadingWafer Boat Tweezer .

Loading Effect() Pattern Pattern .

Loading fixtureLead Frame .

Local Oxidization of Silicon. silicon silicon silicon silicon .

Logic Circuit() 2 , , , .

Logic SimulationIC Functionality Logic Value .

Logic SynthesisHDL Netlist Logic Level Schemetic . VHDL Logic .

LotSampling .

LotWafer .

Low Power Part Power Device Portable .

LP(Lens Paper)Lens .

LPCVD(Low Pressure CVD) Wafer Deposition Gas .

LRR (Lot Reject Rate)Gate Lot Reject.

LSB (Least Significant Bit) .

LSI (Large Scale Integration) Transistor100 .

LTO (Low Temperature Deposition of Oxide, ) LPCVD 400~450 .

LTS(Low Temperature Storage)" " (-40) Oven Device . Luminerous Effciency .

Luminescence .

LVS (Layout Versus Schematic)Layout .

Lyotropic Nematic , .

MMacro Cell Library Core Macrocell Interface Input/Output Macrocell .

Macro FunctionMacrocell Macrocell Library CAD software Library Library.

Macro Loading EffectWafer etch .

MagazineLead Frame Strip Carrier .

Magneto Diode ( Diode) Diode.

Main Frame . . , , .

Magnetic Ink (, ) Ink, TR IC Wafer .

Majority Carrier ( ) . .

Manual StationHandler Tester .

Mask

. Mask Epitaxial Method Mask .

Mask Layout Mask , , , ,, , , mask .

Mask Tooling InformationReticle/Mask Information PG Data, FramePIE Scrbe Line Align Key Information Vendor .

Master Drawing , , , .

MBE(Molecular Beam Epitaxy) .

MCC(Motor Channel Center)Motor , Panel.

Mcdonnell Switch . Boiler , Gas Boiler .

MCM (Multi Chip Module) . MCM , , .

MDS (Microcontroller Development System)MICOM Program Tool.

Measling .

Mechanical Pump

Gas .

Mega CellRAM,ROM Memory PC 82 Series Logic Macrocell Library.

Mega functionMegacell Library Macrofuntion CAD Library Megafunction Library Disk .

Memory CellMemory IC Data . RAM SRAM, DRAM, SRAM Cell Latch , DRAM Condenser . SRAM , Access . DRAM Condenser Bit ,. . Leak Data Rewrite (Refresh) . Memory Effect .

Memory module Memory Memory .

Mesogen .

Metal Gate (AI ) TR MOS FET MOS FET IC .

Metallization .

MFC(Mass Flow Controller) .

Micro BridgePattern Pattern Bridge Scope Current leve l Scope .

Micro IC

.

Micromulsion () .

Mil 1/1,000 Inch. 25.4 m.

Minority Carrier( ) .

Mis-Align (mask) Wafer .

MLM(Multi-Layer Metal)IC Metal 1 Layer . 2, 3 .

MMIC(Monolithic Microwave Integrated circuit) Wafer IC Inductor, Capacitor,, Transistor .

MO Tape(MASK ORIGINAL TAPE) Mask Data .

Mobility, , , , 10/m . .

MOCVD(Metal-Organic Chemical Vaper Deposition) MOVPE Epi . Source 5 .

Mode. . , , Operation .

Model ParameterSimulation

.

Module .

Module .

Molding () . Wire Bonding () package .

Molding CompoundWire Bonding .

Molding Die .

Monitoring .

Monolithic IC1 .

MOP(Metal Oxide Passivation) .

MOS(Metal Orcide Semiconductor)Silicon Device.

MOS FET(MOS Field Effect Transistor)Source, Drain Gate3 Gate Source Drain Channel .

MOS ICMOS FET IC.

Movement Run .

MPR(Micro Peripheral) LSI Micro Computer Microprocessor LSI .

M-Pyrol , , .

MRB(Material Review Board) Criteria , Stock Shut-down 24 Corrective action .

MSI(Medium Scale Integration)100 10 Transistor .

MTO(Medium Temperature Deposition of Oxide)LPCVD 800 .

Multi-Processing .

Multiple Diode 2 Diode .

Multiplexer () Control .

Myelin FigureA 2 .N

Nail Heading .

Nano Line Intensity .

Nano SpecWafer .

National Reference Standard 2 .

Navigation TFT-LCDLCD , .

N-ChannelP FET , .

Neat Phase , , lame lla .

NeckingInterconnect line .

Negative LCDNormally black .

Negative Resistance .

Nematic IC .

Net DieWafer Total Die.

Netlist Simulation Layout , , , Signal Name File.

Neural Processing Chip Neuron Neuron IC.

N-CH Filed Implant

Filed Region VT Ce Cell Filed Oxide ll ICON .

N MOS(N-channel MOS) P Source Drain N MOS device.

Nodule , Si Si .

Noise Margin( ) 1 0 level "1" "0 " .

Non-Volatile( ) Memory.

Notch/Void () . Notch , Hole Void .

NotchingPhoto line .

Notebook TFT-LCD 3.5Kg PC 10 Laptop Pitch 0.21, 0. 33mm.

NPN TRN ,P, N , , TR.

N-Type Silicon(Negative Type Silicon)Major Carrier Electron .

NVD(Non Visual Defect)Deprocess Fail Defect Non Visual Defect .

OOA(Outside Air)AHU .

OAHU(Out Air Handing Unit) .

Oalemce Election , .

OCD(Optically Coupled Device) .

Octal TestProbe Test touch 8Die Probeinng 8 Die test .

OEIC(Organized design for line & Crew System)System Layout Method Line .

One Chip CPU 1 Chip LSI .

ONO Capacitor Dielectric Material Oxide/ Nitride/ Oxide 3 Pinhole Breakdown , Nitride Dielect ric Constant Oxide Capacitance .

Open .

Open RepairTFT Arrey Panel Data Lline Gate Line line short .

Optic Emission MethodPlasma etch Optic signal

.

Optical Axis (No:ordinary) (Ne:extra ordinary) .

Orientation- Film() . Oscilator( ) .

O/S(Open Short) .

OTP(One Time Programmable) EPROM Device Plastic Package Erase Package Device .

Output BufferSence AMP Data External Load Device Buffer.

Output LevelDevice Data (High, Low) .

OutgassingSource Gas Gas Lon Beam .

OvenWafer .

Over Coat(ITO) Alksli Barrir Coa t .

Over Coating(Polyimide Coating) , .

Over EtchingEnd Ppint Detection Etch .

Oerlay VernierWafer Wafer Pattern .

Over- flow .

Oxidation , (650 ~ 1200 ) Wafer .

Oxide(SiO2)

Oxide BreakdownOxide voltage .

Oxide Film() .

PP-ChannelN P FET , .

P & R(Placement & Rounting)Design Automation Chip Layout Macro-Block Standard-Cell .

P/A(Process Area) Wafer Area.

P-Type Silicon(Positive Type Silicon)Major Carrier Hole Si .

PA(Process Air)Air Comp Dryer Filter Air .

PackageTR, Diode, IC Package Mold() Type, Ceranic type, Cam() type . Type Pin Type .

Package Density .

Panel Plating() .

Parasitic Effect() IC .

Passivation , , Damage Plas ma CVD Oxide Nitride , PN , .

Pattern .

PBH (Planer Buried Heterostructure) (LD) , epi .

PCB (Printed Circuit Board: ) , , , , TR, IC, LSI, .

PCD (Plasma Coupled Device)CCD Device.

PCM DataRUN Data Test pattern Data.

PCM TestProcess control monitor , .

PCT(Pressure Cooker Test)" " 15PSI, =100%, =1212 Pressure Cooker .

PCW(Process Cooling Wafer) .

PD(Photo Detector) PIN-PD, APD .

PDP(Percent Defect Panel) .

PDIP (Plastic Dual In-Line Package)Plastic Package Type Package Lead Socker .

PECVD(Plasma Enhanced Chemical Vapor Deposition) Plasma . TFT-LCD Insulato r a-Si .

Pellet Wafer .

Pelletizecompound .

Performance BoardTest System Test System Probe PCB Coaxial Cable Wiring Interface board.

Peripheral LSITest system CPU LSI.

PG(Pattern Generator)CAD System Digitizing Mask Pattern Reticle .

PG(Pattern Generation) Pattern Layout Reticle/Mask Data

.

PG Tape Layout Data Reticle/Mask E-Beam Machine Format Data PG data Tape .

PGA(Pin Grid Array)LeadPackage .

Phase() 1 .

Photo Conductive Effect() .

Photo Diode PN PN .

Photo Etching( ) .

Photo-Resist Positive Negativ e 2 .

Photo-Resist or Resist Positive Negative .

Photo Volatic Effect( ) PN PN .

PI(Process Integration) Photo, Etch, Diffusion, Thin Film, Ion Implantation Process Flow .

Piezo Electric Effect() .

Pin Hole Mask WF Pattern . .

Pit .

Pixel() "Picture Element" R,G,B 3 1 .

Pixel DefectLCD .

PLA(Programmable Logic Array) Program .

Planner. FAB Silicon .

Planar TransistorFAB Silicon Chip .

Plasma .

Plasma Display .

Plasma Etching Gas Energy , , , , , .

Plating.

PLCC(Plastic Leaded Chip Carrier)Package lead 4 .

Plenum .

PLL(Phase Locked Loop) .

P-MOS Channel MOS Transistor.

P-N JunctionP-N Junction P N . Junction (rectifier) Diode .

PNPN DiodePNPN 4 Diode.

PNP Type TransistorPNP P, N, P , , TR .

Polarizer , 2 PVA TAC(Tri Acetyl Cellul ose) .

Poly-Crystal() . Poly-Crystal Silicon( ) . .

Poly-Si , . .

Polyimide

Rubbing .

Polymer. (Monomer) .

Positive LCDLCD Normally White .

Post Burn-inBurn-in .

Post Laser Repair TestLaser Repair Wafer Chip Pass/Fail Laser Repair .

Pot .

Power RegulatorBipolar IC IC Linear IC .

PR(Photo Resist) Pattern . Pattern . Pre Burn-in Burn-in .

Predipitate ( ), FAB .

Preform Feeder Preform Lead Frame .

Pretilt Angle .

Probe CardWafer Chip Probe Tip .

ProberTest Wafer X, Y, Z ROOM/HOT Wafer Point Test .

Probing PAD Probe Tip Contact .

Process Minispec. base line FAB SPEC ,, .

Profile .

Proximity EffectPattern Etch .

PRT(Production Realiability Test) .

PSG(Phospho-Silicate-Glass) . Phosphorous Reflow .

P/S(Prober Station)Wafer

PSRAM(pseudo SRAM)DRAM SRAM Refresh DRAM SRAM .

P-TypeN-Type 3 .

P type semiconductor .

Punch-Through Breakdown

Source/Drain Junction depletion region Breakdown Substrate , Short Channel Junction Depletion Source -Dain .

PV(Process Vacuum) Pump . .

PVD(Physical Vapour Deposition)CVD , .

PW(Polished Wafer) .

PWL(Pulsed Word Line)ICC Reading Word Line Signal Pulse Control Circuit .

QQDR(Quick Drain Rinse)DI Rinse Cycle Sho-wer Drain Cleaning .

QFP(Quad Flat Package)Lead Package Lead .

Quartz BoatWafer , .

Quartzware() Furnace N/C Chamber .

Q-tip. Cleaning .

QTL(Q8K Test Language)Q8K Test System PGM language.

Qual(qualification) Test .

Quantum Electrnics Elec tronics .

QV (Quality Validation) Test QA , ,Test .

RR/A(Return Air) .

Rack. .

Ram Height .

Rambus DRAMRambus DRAM. Data 500MHz data bus .

RAMDACPixel Address RAM DAC R.G.B Analog Chip.

RasterCRT .

Recipe Material Process Rule Control data .

Rectifier Diode .

Recombination , .

.

Rectifying Action() .

Redundancy Cell Chip .

Redundancy Chip Cell Defect Cell Cell .

Reference Check Device System Check .

Reflectance() Film .

Reflective DisplayBacklight Display.

RefreshDRAM MOS FET WRITE-IN REFRESH .

Reject Wafer Mask .

Reliability .

RepairableMemory Chip Fall Bit Redundancy Fail Cell Spare Cell Repairable . Wafer Test Row Column Cell Row Column .

Repeating Defect() Wafer .

Resin Recession .

Resisstor Retilcle Mask Chip 10 Mask Master Mask .

Resistration .

Response time .

RetestSystem Align Test Wafer Test .

ReticleMask .(Stepper Mask) Wafer Pattern ( ) () Wafer .

Reverse Tilt .

Reverse Twist , .

RF(Radio Frequency) , Gas , .

RIE(Reactive lon Etching) . Plasma etching Ion .

Ring OscillatorLibrary .

Rinse(DI Water) Wafer .

Rise Time() TR Collector ( ) 10% 90% .

Room Temperature Test .

ROR(Ras Only Refresh)RAS Low Refresh .

Round CutWafer Wafer .

RoutingPCB . PCB Drill PCB .

Row Fail Device Test X address, Y address cell fail .

R.S(Resistivity) .

RTI(read time inspection)FQA Sampling .

RTV(Room Temperature Vulanizing) . 25, 60% .

Rubbing .

Run SplitRun , Run Wafer , .

RZ(Return to Zero) Pattern Data "1" "0" Palse .

SS/A(Service Area) Mainternance Area 1M-DRAM CALSS 100. Salt Spray " " =35, 5% Device Lead Frame Check .

SawingWafer 1/1000 Wafer X,Y .

S/C(Solder Coating)I.C lead lead .

ScannerBeam line lon Beam Beam .

Scanning Trigger Circuit Feedbac k .

Schematic . Simulator Text Netlist .

Schottky Barrier .

Schottky Diode , P-N Diode.

Schottky gate fetFET Gate , Schottky FET.

SCP

Gate PNPN .

ScrambleDevice Pin Test .

Scratch, .

ScreeningDEBUG, BURN-IN LOT .

Scibe Wafer Chip .

Scibe lineDie Sawing .

Scribing , Wafer ( , )

ScrubberWafer .

Scum Wafer .

SDA(Statistical Dafect Analysis)Process Wafer Fail(Row, Column, Bit fail) Feedback Data.

SDRAM(Synchronous DRAM) System Clock Data 10ns Access Time DRAM.

Seal Bonding Wire .

Seal PrintLCD Seal .

Search LevelDie Lead .

Second Bond Lead Frame Bond.

SECSDEVLoopback Test Simulator .

SECSIM(SECS Simulator)SECS Test PC Simulator.

SECSTESTLoopback Test Simulator HOST .

SECCPECSECS Protocol Specification Vendor .

SegmentNIXIE TUBE , , , . , .

Segment ON/OFF "8" .

SEG(Selective Epitaxial Growing) Epi Silicon Oxide .

Selective Diffusion() .

Selective Oxidation Process() .

Self Align Mask .

Self bias( ) .

Self RefreshDRAM Refresh Refresh Mode DRAM , Self Refresh DRAM Refresh T ime Refresh .

Self-AlignmentMOD Gate AL Melting Poing AL DEP. Themal Caycle . AL DEP Source Drain Drive-in . S/D Drive-In Gate Define Alignment Tolerrance Overlap Regio n S/D Parasitic Overlap Capac-itance Minimum size .

SEM(Semiconductor Equipment and Material Institute) , .

Semi-Auto Host CST LOAD/UNLOAD Opertor .

Semi-Custom Masker Cell Mask User IC/LSI IC.

Semiconductor. ( ) ( ) .

Sensor .

Sense AMPCell Data Data line voltage swing Data line Signal Am plifier.

Sequential Circuit()

GateNAND, NOR , Flip -Flop, Shift Register, Counter, Memory .

SER(Soft Error Rate)Memory Particle FIT .

SET(Summary of Electrical Test) TEST Information Sheet.

Set-up() . Set-up Mode Arc Energy lon Beam .

SF(Stacking Fault) .

SF(Spiral Flow) .

Sheath() .

Shelf() Stocker Cassett .

Shift RegisterRegister (Shift ) .

Shoe BoxCarrier 2 , carrier .

ShoomDevice graphic , 2 , Device pass/fail dotting Device .

Short Circuiting

.

Short Repair .

Shrink Chip .

SiC(Silicon Carbide) , Wafer Tube , .

Side Ball Bonding Wire .

Side Etch () .

Silicon 4 .

Silicon CompilerSystem master pattern IC .

Silicon GateGate , MOS .

Si Gate MOSMOS FET Gate (Poly) silicon MOS Device.

Silicon Nitride .

SIMM(Single In Line Memory Module)Edge connector .

Simulation Vector simulation input pin input netillist cycle

.

Single Crystal .

Single end lead .

Single In Line.Lead .

SIP(Single Inline Pkg)Memory Module Memory Modual, Pin Type Memory Module . Inserting .

SiteWafer .

SkewPin Timing.

SliceWafer . Silicon .

Slicer level , limitter level slicer . Slot() Carrier boat Wafer .

Sludge .

Smart Power IC Control IC .

Smock() Line .

SN(Spit Notice)RUN Spit Split .

SOA(Safe Operating Areas) .

Socket BoardJig (TEST PKG )

SOG(Sea of Gate)ASIC Unit Gate Array Channel . Metal D ie Unit Gate .

SOG(Spin On Glass)VLSI , , . SOG SOG 400 ~500 .

SOIC(Silicon outline Integrated Circuit) IC.

SOJ(Small Outline J-form Package)Device "J" LEAD PKG PCB .

Solder Ball .

Solder Coating , Frame Coating .

Soldering () PCB I.C , .

Soldering OilWafer Soldering Machine

.

Soler PreformDie Lead Frame .

Solder ResistPCB , Solder .

Soler Side() .

SortingWafer .

SOT(Small Outline Transistor) Transistor.

Space Charge .

SpacerLCD , .

SPARC(Scalable Processor Architecture)SUN MICRO 32 Bit RISC Processor.

Speed-Up CapacitorTR Inverter Speed-Up .

Spider bondingWireless Pattern Wafer .

SpikeSilicon Contact .

Spindle MotorBlade Wafer , . Air Bearing 30, 000RPM .

SPLC(Stocker PLC)Stocker Stocker Program .

SplitNormal RUN .

Split Word lineSRAM Cell Layout Design Asymmetry Word Line .

Sputtering Argon Gas Target Wafer .

Square OutWafer , Wafer .

S-RAM(Static RAM)Dynamic RAM . .

SSI(Small Scale Integration)10 Gate .

Stack . FAB Silicon .

Standard CellStandard Cell Cell , Chip semi-custom LSI Gate Array custom .

Standby .

Standby Current Drain .

Static Hold 2V Data Data Retention .

Static memoryMOS FET .

STC(Stocker Controller)Bay Cassette , Bay Cassette Bay Cassette Bay .

STD(Standard)

Stem TR , Header .

Stepper WF 1 Chip Chip . WF 1 .

STN(Super-Twisted Nematic) WF PC .

Storage Time () TR ON .

StressWafer .

Stringer Film Etch Residue .

StripWafer P.R , .

StrobeDevice Device Latch Timing.

Sub-Mask Mask Master Mask Mask

mask.

Substrate () , Wafer .

Substrate-ConcentrationWafer , Bulk .

Subtrative Process, , etching .

Supported Hole() .

Surface Agent .

Surface Concentration. Wafer .

Surface Passivation( ) PN . (ACTIVE) PN (PASSIVE) .

Surface Potential . Wafer .

Surge Current .

Synchronization() Timing .

SWMI(Side Wall Masked Isolation)LOCOS Isolation Oxide En-croachment , bird's Beak .

TTAB(Tape Automated Bonding)Tap Die .

TABTR IC 1mm TAB .

TapingWafer Tape ( ).

TCA Oxidation TCA .

TCP(Tape Carrier Package)IC Chip Tape Film TAB(Tape automated bonding) Package.

TEG(Test Element Group) Bread Board TR, Diode, .

Tenting Resist .

TEOS(Tetra Ethyl Ortho Silicate) Si Source .

Terminallon Source Cover .

Test HeadTester Handler Prober Station .

Test Mode Device Test Test Access Device , Test Test Time Test multi-bit test .

Test Pattern / Wafer Pattern.

Tester Computer .

Test OptionComputer .

Test Plan , , , Limit .

Test Program Wafer Program SPEC Program Software.

Test Schematic(Test Circuit)Jig .

Test System .

Test Vector Test Simulation Test Signal Set.

Test vehicle Mask.

Test Test Program Pass/Fail .

TestabilityChip Level Block Sub Block Test .

TF-EL Display (Thin-Film Electrolumines- cent Displays) , .

TFIC(Thin Film Integrated Circuit) 5 . .

TFT(Thin Film Transistor) FET.

TFT ArrayMatrix TFT .

Thermal Addressing .

Thermo-Optic Effect( ) . .

Thermotropic LC .

Thermal Relief() .

Thermal Shock Test() TR, Diode, IC .

Thermo Electric Effect() , , .

Thick Film IC( ) 5 .

Thin FilmThick Film ( 5 micro) .

3D Circuit Device LSI , DEVICE LSI Silicon LSI . 3 .

Threshold LevelInput Device .

Thyristor () PN 3 ON/OFF 2 OFF ON .

Tie barPKG Lead Bar.

Tilt , . .

Tilt Angle .

TimingDevice Comtrol Clock, Address, Data .

Tin PlatingSn Frame .

Tip Chip .

TiSiX (Titanium Silicide)Titanium silicon contact .

Tj(junction Temperature).

TN LCD (Twisted Nematic Liquid Crystal Display)90 LCD.

TN-FE LCD (Twisted Nematic Filed Effect LCD) 90 Twist LCD.

TNI. Clearing Point .

Tooling Hole .

Topology () Wafer .

TQFP(Thin Quad Flat Package) 1.0 mm 1.4mm QFP.

TR(Transformer) .

TransferLCD , Carrier Boat Wafer Carrier Boat .

Transfer CollectTape Die .

Transfer PrintNi-beads .

Transfer System. RUN SHOE BOX Wafer .

Transition timeDevice level level A.C .

TransistorEmiter Collector base base carrier .

Transition .

Trapcarrier .

Trench . FAB , Silicon .

Triangular Voltage Sweep MethodGate mobile ion oxide current gattte bias oxide check .

Triger .

Trim/FormPackage lead 90 I.C .

Tristate output Level High Low High Impedance .

TSOP(Thin Small Outline Package)Package 1.0mm SOP(SOIC) P-DIP PACKAGE SYSTEM .

TS(Tensile Strength) .

TTL(Transistor Transistor Logic) . .

TTV(Total Thickness Variation) (wafer)

TunnelingBisas PN, Oxide Energy Band Gap Electron Hole .

TV RUNTest Vehicle Wafer.

TweezerWafer ( Vacumn Tweezer )

Twist angle Cell .

UUART(Universal Asynchrnous Receiver & Transmiter) LSI Interface .

UJT(Unjunction TR)Junction 1 Base 2 TR.

Ultra Filter2 Particle Filter.

Ultrasonic Cleaner () .

Under CoatingLCD SiO2 . SiO2 . MASK LAYER .

Undershoot Noise 0V NOISE, 0V NS Pulse Negative Latch-up .

Uni-Biopolar IC - TR .

Unipolar Transistor FET .

Unloader Frame Magazine Frame .

UnloadingLoading Wafer Tweezer Transfer Arm CARRIER BOAT .

UPS(Uninteruptable Power Supply) .

UV(Ultra Violet,) Energy .

VVacumn TubeTransistor , , , , Transistor IC .

Vacuumn TweezerChip Carrier .

Valence Band () .

Valence Electron() .

Vane DamperFan .

Varistor .

Vcc (Supply Voltage) . Device Device Device .

Vector Simulation Input Pin Input Netilist Cycle .

Vector AddressPattern Memory Pattern Address.

Verical TR( ) ( ) . .

VFD(Vacumn Fluorescent Display) . .

VIA Metal lnsulating filed Contact.

VIA not OPEN METAL LAYER PROCESS VIA CONTACT UNDER ETCH Metal Layer Contact SPEC .

Via holePCB .

Viewing Angle . LCD.

Virtual Cieaing Point( ) .

Viscosity , . .

Visual inspection Chip Device .

VoidRTN (). FAB SPACE .

VssDevice Device Vcc Clock Device Signal .

VTD Depletion TR VTH.

VTH(Threshold Voltage).

VTNNatural TR VTH.

VTPC(Vertical Probe Card)Wafer Test Device PAD Needle Probe Card Probe Card Needle .

WWafer (Si) .

Wafer CarrierWafer , .

Wafer IDRUN Wafer Wafer .

Wafer SortWafer Level GO/NO-GO Test , Test Wafer Probe Prober Card Test .

Wafer Storage Box (Wafer) Wafer Carrier Box.

Wave Form Wafer lon Beam .

Wave Soldering .

Wedge Bonding .

WellCMOS Technology N-Channel Transistor P-Channel Transistor Si-Substrate N P-Channel Transistor substrate.

Wet Etch. .

Wet SinkWafer .

Wetting .

WI(Wire Inspection)Bond .

Wide Bit8bit I/O Byte Word Dar Device .

WIP(Work In Process)()

Wire BonderTR IC Wire Bonding Wire Bonder .

Wireless Bonding .

Work Function .

Work HolderLead Frame Loader Magazine Die Unloading Magazine .

Work stationWF .

Worm(1 : Write once Read many) .

WriteEPROM EEPROM Floating Gate Bit .

WSI(Wafer Scale Integration)Wafer Chip Wafer .

WSTS(World Semicondiuctor Trade Statistics) . .

XXylne or Way Coat (resist) .

YYield

Wafer Wafer 1 Wafer Chip Wafer Test Chip .

ZZenor breakdownPN Diode 0 . .

Zenor . PN Diode , . . , . .

Zero ohm resistorSIMM PD Pin Chip Connector ZERO OHM RESISTOR .

ZIP(Zigzag In-line Package)Package Type Package Lead Zigzag Device .

Zone AHU(Zone Air Handing Unit) FAB Return FAB Air .