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Use two shadow page tables for each guest page table
• Privileged/User shadow PTs
• Switch on privilege mode switches
Guest AP Priv. Shadow AP User Shadow AP
PNA-UNA P**-UNA P**-UNA
PRW-UNA P**-URW P**-UNA
PRW-URO P**-URW P**-URO
PRW-URW P**-URW P**-URW
PRO-UNA P**-URO P**-UNA
PRO-URO P**-URO P**-URO
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{User, Priv} Shadows
Guest page table
Shadow User page table
Shadow Priv. page table
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Comparison of ARM vs. x86 Virtualizability
Sensitive Instructions
[3] John Scott Robin and Cynthia Irvine, Analysis of the Intel Pentium’s Ability to Support a Secure Virtual Machine Monitor, USENIX Security Symposium, 2000.
Type of Sensitive Instructions
Violating Goldberg’s
Requirement #
X86 [3] ARM
Sensitive Register Access
3B SGDT, SIDT, SLDT, SMSW, PUSHF/POPF
-
Protection System References
3C LAR, LSL, VERR, VERW, PUSH/POP, CALL, JMP, INT n, RET, STR, MOVE
LDM/STM (user regs), LDRT/STRT (“As User”)
Both 3B & 3C - MRS, MSR, CPS, SRS, RFE, DPSPC,
LDM (exc. return)
Copyright ® VMware, Inc. All Rights Reserved.
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Comparison of ARM vs. x86 Virtualizability
Ring compression – protection mechanisms
• x86: Segmentation + Paging
• ARM: Paging (+ domains?)
Instruction execution vs. Data Read/Write protection
• x86: CS for instruction fetch vs. DS/other for data access
• ARM: No explicit distinction b/w execute and read protection
Cache architecture
• x86: Largely transparent; PIPT across all versions
• ARM: Exposes a lot of the cache architecture; VIVT/VIPT/PIPT