© 2004 Xilinx, Inc. All Rights Reserved Adding a Processor System to an FPGA Design.

© 2004 Xilinx, Inc. All Rights Reserved

Adding a Processor System to an FPGA Design

Adding Processor System to an FPGA Design - 4 - 2 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only

Objectives

After completing this module, you will be able to:• Utilize the integration between ISE and XPS to enhance the design flow• Utilize the Xflow in XPS• Describe the steps involved in creating a submodule by using XPS and

integrating the submodule into a bigger system by using ISE• List some of the advantages of UltraController


Outline

• ISE: Project Navigator Integration– Top Level– Submodule

• UltraController Case Study• XPS: Xflow Integration


EDK: ISE

Processor IPMPD Files

system.ucf

system.bit

MHS Filesystem.mhs

PlatGen

ISE

Hardware

Data2MEM

download.bit

Compile

Link

Object Files

Executable

Libraries

Source Code

LibGen

MSS Filesystem.mss

EDIF IP Netlists

bram_init.bmm

bram_init_bd.bmm

ISE

Source Code

Synthesis


ISEProject Navigator Integration

• XPS provides integration on two levels:– The processor system is the top-level design– The processor system is a submodule

• What XPS does– Creates the ISE Project Navigator Project File (NPL)– Adds the BMM file to the project– Adds the HDL file to the project

• Top-level wrapper• Submodule wrapper

– Sets macro search path to <project>\implementation directory• The peripheral files (NGC) created by PlatGen


ISEProject Navigator Integration

• Benefits– Allows you to add additional logic to the FPGA design– Allows you to synthesize the design by utilizing ISE supported synthesis

tools– Allows you to control the FPGA implementation flow by using ISE

• Timing and constraints entry• Implementation tool flow control• Point tool control

– FPGA Editor tool– Constraints Editor tool– ChipScope Pro tool


Project OptionsHierarchy and Flow Tab

• Design Hierarchy– Toplevel– Sub-module

• Top Instance• Must use ISE flow

• Synthesis Tool– ISE XST– None, if third party tools are to be

used• Implementation Tool Flow

– XPS– ISE (ProjNav)

• Provide directory and file name in the NPL File box


Outline

• ISE: Project Navigator Integration– Top Level– Sub-module



ISE: Top Level

• The project is created with the partand synthesis tool selected in XPS

• The processor system netlist will be hierarchical

• The following files are added– system.vhd: instantiates the

processor system created in XPS– bram_init.bmm: BMM file

used by Data2MEM– User IP creates a VHDL library

and adds the IP sources to thatlibrary


Outline




ISE: Sub-module

• The project is created with the part and the synthesis tool selected in XPS

• The following files are added– system_stub.vhd: instantiates the

processor system created in XPS– system_stub.bmm: BMM file used

by Data2MEM


Outline




UltraController

• UltraController key features– Completely self-contained

PowerPC system• No external FPGA pins required

– 32 general-purpose inputs and outputs– Ultra low power— 0.9 mW / MHz

• Easy to use– Code in “C” — Multiple reference

designs available– No CPU buses, no RTOS required– Integrates with standard ISE design flow– Full debug support

32

32

gpio_insys_clk gpio_out

sys_rstjtag_cntlr UltraController


Inside the UltraController

• General-purpose controller based on the PowerPC– Growing family of solutions– Uses 8 or 16 BRAMs + 49 logic cells

• 8-kB instruction, 8-kB data

• 16-kB instruction, 16-kB data

– JTAG debug support

UltraController

ROM8kB PowerPC

405

gpio_in <0:31>

gpio_out <0:31>

sys_clksys_rstjtag_cntl

I/ORAM8kB


UltraController Benefits

• UltraController provides flexibility for the following– Complex user interfaces (GUI or LCD display)– Sophisticated data and math manipulations– System monitoring and statistics gathering– Complex algorithms

• Maximizes logic efficiency by using the PowerPC processor, because logic frees fabric for more functionality, performance, and intelligence

• Reduces cost by downsizing to smaller device

Original Device New Device Cost Saving*

XC2VP7 XC2VP4 40%

XC2VP20 XC2VP7 50%

XC2VP30 XC2VP20 54%


UltraController Design Flow

Place & Route

Simulation

HDL

PPC405PLB /

Arbiter

PLBEMC

OPBGPIO

OPBUART

PLB2OPBBridge

OPB2PLBBridge

BRAMBlock

OPB /Arbiter

JTAGCNTL

PLBBRAM

I/F

ISE

DownloadBitstream

ChipScope ProHardware

Verification

EDKC Code

GDBSoftware

Debug

Software Steps

UltraControllerHDL Module


Prepackaged Design

UltraController Instantiated in EDK

UltraController Instantiated in EDK


UltraControllerImplementation Steps

Add UltraController to HDL Design in ISE

Add UltraController to HDL Design in ISE

1

Create Code in the Platform Studio- Leveraging Reference Examples- Simulate System

Create Code in the Platform Studio- Leveraging Reference Examples- Simulate System

2

Download Design - Debug

Download Design - Debug

3


Step 1:Add UC to the HDL in ISE


Step 2: Create the Code in EDK

Write to LEDWrite to LED

Write to SoundWrite to Sound

Click to Compile SWClick to Compile SW


System SimulateBehavioral and Structural Levels


Step 3:Download Using iMPACT


Outline


• UltraController Case Study

• XPS: Xflow Integration


EDK: Xflow

Processor IPMPD Files

system.ucf

system.bit

MHS Filesystem.mhs

PlatGen

Xflow

Hardware

Data2MEM

download.bit

Compile

Link

Object Files

Executable

Libraries

Source Code

LibGen

MSS Filesystem.mss

EDIF IP Netlists

bram_init.bmm

bram_init_bd.bmm

Source Code

Synthesis


Xflow

• Benefits to the user– Allows independent design of the processor system– Allows the designer to use one GUI to perform all design work

• Limitations– No direct control of synthesis and implementation options– No point-tool support


Xflow

• code directory– <application>.c

• data directory– <system>.ucf

• etc directory– bitgen.opt– bitgen.ut– download.cmd– fast_runtime.opt– BSDL files

• pcores directory– User IP– Customized BRAM controllers

project_directory

code directory

data directory

etc directory

pcores

Required XPS Directory Structure

synthesis

TestApp [optional]


Controlling Xflow

• In the etc directory, there is a file called fast_runtime• This is what it looks like:

# Options for Translator# Type "ngdbuild -h" for a detailed list of ngdbuild command line optionsProgram ngdbuild -p <partname>; # Partname to use — picked from xflow commandline-nt timestamp; # NGO File generation. Regenerate only when # source netlist is newer than existing NGO file (default)-bm <design>.bmm; # Block RAM memory map file<userdesign>; # User design — pick from xflow command line<design>.ngd; # Name of NGD file. Filebase same as design filebaseEnd Program ngdbuild


Review Questions

• What are some of the advantages of using the ISE and XPS integration?

• What are some of the advantages of using the Xflow and XPS integration?

• How can UltraController be beneficial?


Answers

• What are some of the advantages of using the ISE and XPS integration?– Allows you to add additional logic to the FPGA design– Allows you to synthesize the design by utilizing ISE supported synthesis

tools– Allows you to control the FPGA Implementation flow by using ISE

• What are some of the advantages of using the Xflow and XPS integration?

– Allows you to use one GUI to perform all design work• How can UltraController be beneficial?

– Increases product functionality– Implementing the finite state machine in the PowerPC improves logic

efficiency– Reduces cost by downsizing


Where Can I Learn More?

• Tool documentation– Embedded System Tools Guide Xilinx Platform Studio

• Support website– UltraController Home Page — www.support.xilinx.com/ultracontroller– EDK Home Page: support.xilinx.com/edk

© 2004 Xilinx, Inc. All Rights Reserved Adding a Processor System to an FPGA Design.

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