– 1 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Switched-Capacitor Circuits.

– 1 –

Data Converters Switched-Capacitor CircuitsProfessor Y. Chiu

EECT 7327Fall 2012

Switched-Capacitor Circuits

Continuous-Time Integrator

– 2 –


EECT 7327Fall 2012

Goal:

C2

Vi Vo

R1

C2

Vi VoSC

1 2

1 2

1

1 1

t

o in

o

i

v t v dR C

VH s s

V R C s

Approach: emulating resistors with switched capacitors

1 2R C

Concept of Switched Capacitor

– 3 –


EECT 7327Fall 2012

BA VVT

C

T

qi

BA VVR

i 1

Ф2

Ф1

C

TReq

• A switched capacitor is a discrete-time “resistor”

• RC time constant set by capacitor ratio C2/C1 (match considerably better than R and C) and clock period T (flexibility)

RVA VB

i

C Ф2Ф2

Ф1Ф1

VA VB

<i>

so,1

22

121, C

CTC

C

TCReq

Non-overlappingtwo-phase clock

Switched Capacitors

– 4 –


EECT 7327Fall 2012

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

• Shunt- and series-type SCs are simple and cheap to implement

• Stray-insensitive SC requires 2 more switches, what’s the advantage besides being more flexible (i.e., w/ or w/o the T/2 delay)?

2-phase clock

Ф2Ф1

VA VB

CФ1

VA VB

C Ф2

Series-typeShunt-type

C Ф2Ф2(Ф1)

Ф1Ф1(Ф2)

VA VB Stray-insensitive

Discrete-Time Integrator (DTI)

– 5 –


EECT 7327Fall 2012

2-phase clock

C2

Vi Vo

Ф2Ф1

C1


Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

What are the VTFs (z-domain) of these DTIs, assuming no parasitic capacitance is present?

C2

Vi Vo

C1Ф1

Ф2

Shunt-Type DTI

– 6 –


EECT 7327Fall 2012

Ф1(sample)

Charge conservation law (ideal):

Total charge on C1 and C2 during Ф1→ Ф2 transition must remain unchanged!

C2

Vi Vo

C1

C2

Vo

C1

Vi

Ф2(update)

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

T

vi(t)

0 t

vo(t)

0 t

(n-1)(n)

(n+1)

(n-1)

(n)(n+1)

Shunt-Type DTI

– 7 –


EECT 7327Fall 2012

Ф1(sample)

Ф2(update)C2

Vi Vo

C1

C2

Vo

C1

Vi

211 CnVCnVQ oi 212 10 CnVCQ o

212121 10 CnVCCnVCnVQQ ooi

221 CzVzCzVCzV ooi

1 1/21 1

1 12 2

1 1

o

i

V z C Cz zH z or

V z C z C z

Series-Type DTI

– 8 –


EECT 7327Fall 2012

Ф1(sample/update)

Ф2(reset C1)

C2

Vi Vo

C1Ф1

Ф2

1

2

1

1

1

zC

C

zV

zVzH

i

oVTF:

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

T

vi(t)

0 t

vo(t)

0 t

(n-1)(n)

(n+1)

(n-1)(n)

(n+1)

Stray Capacitance

– 9 –


EECT 7327Fall 2012


Cu

Cu Cu

Cu Cu

C1 C2

• Strays derive from D/S diodes and wiring capacitance

• VTF is modified due to strays

• Strays at the summing node is of no significance (virtual ground)

41

2 C

C

C2

Vi Vo

C1

Ф1 Ф2

A

C2

Vi Vo

C1

Ф1

Ф2

A

Stray-Insensitive SC Integrator

– 10 –


EECT 7327Fall 2012

1

2

1

1

1

zC

CzHVTF:

1

1

2

1

1

z

z

C

CzH

• Capacitors can be significantly sized down to save power/area

• Sizes are eventually limited by kT/C noise, mismatch, etc.

C1 Ф2Ф2(Ф1)

Ф1Ф1(Ф2)

C2

Vi Vo

A B

“Inverting” “Non-inverting”

VTF:

SC Amplifier

– 11 –


EECT 7327Fall 2012

11

2

CH z z

C

• Non-integrating, memoryless (less the delay)

• Used in many applications of parametric amplification

VTF:Vi

C2

C1Ф1

Ф2

Ф1

Vo

– 12 –


EECT 7327Fall 2012

SC Applications

CT Filter

– 13 –


EECT 7327Fall 2012

R

CVi Vo

L

R1

CA

R

R

R3

R4

CB

R2

Vi Vo

RLC prototype

Active-RC Tow-Thomas

CT biquad

SC DT Filter

– 14 –


EECT 7327Fall 2012

SC DTbiquad

CA CB

Vi Vo

C1 Ф2Ф2

Ф1Ф1

C2

C4 Ф2

Ф1

C3 Ф2Ф1

Ф1Ф2

Ф2

R1

CA

R

R

R3

R4

CB

R2

Vi Vo

Active-RC Tow-Thomas

CT biquad

Sigma-Delta (ΣΔ) Modulator

– 15 –


EECT 7327Fall 2012

CI

Ф2Ф1

Ф1Ф2

Vi

Do

+VR 1-b DAC-VR

CS

DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC

Pipelined ADC

– 16 –


EECT 7327Fall 2012

SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC

Vo

Vi

0-VR

VR

1.5-bDAC

Φ1 C1

Φ1 C2

Φ2

Φ1

Φ2

-VR/4

VR/4

SC Common-Mode Feedback

– 17 –


EECT 7327Fall 2012

Vo+

Vo-

R

AR

VBias Vcm

Vcmc

Vo+

Vo-

R

AR

Vcmc

Vcm-VBias

CM sense amp can be replaced by a floating voltage source since the gain through the main op-amp is high enough.

SC Common-Mode Feedback

– 18 –


EECT 7327Fall 2012

Vo+

Vo-

A

Vcmc

C

C

0.2C

0.2C

Ф2

Ф2

Ф2

Ф1

Ф1

Ф1

Vcm

Vcm

VBias

Vo+

Vo-

A

Vcmc

Vcm-VBias

Vcm-VBias

Ф2

Ф1

– 19 –


EECT 7327Fall 2012

Noise in SC Circuits

Noise of CT Integrator

– 20 –


EECT 7327Fall 2012

Noise in CT circuits can be simulated with SPICE (.noise)

R

C

Vi Vo

R

C

Vo

VN12

VN22

H1(f)

H2(f)

2 2

2 22 1 21 2

N NoN

V VV f H f df f H f df

f f

Noise of SC Integrator

– 21 –


EECT 7327Fall 2012

SC circuits are NOT noise-free! Switches and op-amps introduce noise.

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

C2

C1 Ф2Ф1

Ф1Ф2

Vi Vo

Sampling (Ф1) Ideal Voltage Source

– 22 –


EECT 7327Fall 2012

• Noise is indistinguishable from signal after sampling• The noise acquired by C1 will be amplified in Ф2 just like signal

2 222 1 2

10

2

1 201 2

1

14 4

1 2

N NN

V VV f f H f df

f f

kTR kTR dfj f R R C

kT

C

C1

Vi

R1

R2

VN12 VN2

2

Integration (Ф2)

– 23 –


EECT 7327Fall 2012

No simulator can directly simulate the aggregated output noise!

2 2 2

2 22 3 4 534 52 N N N

N

V V VV f f H f df f H f df

f f f

21 22

2

2

12 NNoN VVC

CV

Vo

VN32

VN52

H34(f)

H5(f)

C1

C2

R4VN42

R3

Sampling (Ф1) Noise – Cascaded Stages

– 24 –


EECT 7327Fall 2012

C1'R1

R2

VN32

VN52

VN12 VN2

2C1

C2

R4VN42

R3

• Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise (noise filtering).

• But parasitic loop delay may introduce peaking in freq. response, resulting in more integrated noise (noise peaking).

C2 C2'

Vi Vo

C1 Ф1Ф2

Ф2Ф1

C1' Ф2Ф1

Ф1Ф2

Ф2

Sampled Noise Spectrum

– 25 –


EECT 7327Fall 2012

• Total integrated noise power remains constant

• SNR remains constant

CT

DT

PSD

fs/2 fs 3/2fs0

PSD

fs 2fs0

Alias

– 26 –


EECT 7327Fall 2012

Nonideal Effects inSC Circuits

Nonideal Effects in SC Circuits

– 27 –


EECT 7327Fall 2012

• Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap, accumulation-mode gate cap, etc.)– PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage

coefficients negligible for most applications)– Gate caps are typically good for up to 8-10 bits

• Switches (MOS transistors)– Nonzero on-resistance (voltage dependent)– (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb)– Switch-induced sampling errors (charge injection, clock feedthrough,

junction leakage, drain-source leakage, and gate leakage)

• Operational amplifiers– Offset– Finite-gain effects (voltage dependent)– Finite bandwidth and slew rate (measured by settling speed)

– 28 –


EECT 7327Fall 2012

Nonideal Effects ofSwitches

Nonzero On-Resistance

– 29 –


EECT 7327Fall 2012

• FET channel resistance (thus tracking bandwidth) depends on signal level

• Usually (RonCS)-1 ≥ (3-5)·ω-3dB of closed-loop op-amp for settling purpose

VGS

Vout

C

…Ф

CS

Ф

Ф

CS

…

Ron

0 VDDVout

VTnVTp

PMOS

NMOS

CMOS

outthDDoxon VVVL

WCR 1

Clock Bootstrapping

– 30 –


EECT 7327Fall 2012

• Small on-resistance leads to large switches → large parasitic caps and large clock buffers

• Clock bootstrapping keeps VGS of the switch constant → constant on-resistance (body effect?) and less parasitics w/o the PMOS

Ф

Ф

CS

…

OutInM1

VDD

Ф1 Ф2

CMOS Bootstrapped NMOS

Simplified Clock Bootstrapper

– 31 –


EECT 7327Fall 2012

Pros• Linearity• Bandwidth

Cons• Device reliability• Complexity

Out

C

In

M2

M1

VDD

VSS

OutInM1

VDD

Ф1 Ф2

Ф1Ф1

Ф2

Ф2

Ф2

Ф2

Switch-Induced Errors

– 32 –


EECT 7327Fall 2012

Channel charge injection and clock feedthrough (on drain side) result in charge trapped on CS after switch is turned off.

Vout

Ф

CS

Zi

Vin

CgdCgs

Qch

• Clock feedthrough

• Charge injection

Clock Feedthrough and Charge Injection

– 33 –


EECT 7327Fall 2012

• Both phenomena sensitive to Zi, CS, and clock rise/fall time

• Offset, gain error, and nonlinearity introduced to the sampling

• Clock feedthrough can be simulated by SPICE, but charge injection cannot be simulated with lumped transistor models

Ф

VDD

0

Vin+Vth

Switch on Switch off

Vout

Ф

CS

Zi

Vin

CgdCgs

Qch

Clock Rise/Fall-Time Dependence

– 34 –


EECT 7327Fall 2012

Ф

VDD

0

Vin+Vth

Switch on Switch off

Vout

Ф

CS

Zi

Vin

CgdCgs

Qch

Clock feedthrough Charge injection

Fast turn-off

Slow turn-off

DDSgs

gs VCC

CV

Sgs

inthDDox

CC

VVVWLCV

2

thinSgs

gs VVCC

CV

0V

Dummy Switch

– 35 –


EECT 7327Fall 2012

• Difficult to achieve precise cancellation due to the nonlinear dependence of ΔV on Zi, CS, and clock rise/fall time

• Sensitive to the phase alignment between Ф and Ф_

Vout

Ф

WL CS

W2L

Ф

Vin

CMOS Switch

– 36 –


EECT 7327Fall 2012

• Very sensitive to phase alignment between Ф and Ф_

• Subject to threshold mismatch between PMOS and NMOS

• Exact cancellation occurs only for one specific Vin (which one?)

Vout

CS

Vin

Ф

Ф

Same size for

P and N FETs

Differential Signaling

– 37 –


EECT 7327Fall 2012

• Signal-independent errors (offset) and even-order distortions cancelled

• Gain error and odd-order nonlinearities remain

Balanced diff. input

Vop

CSp

Vip

M1

Von

CSn

Vin

M2

Ф

Ф

Switch Performance

– 38 –


EECT 7327Fall 2012

ch

2

ithDDox

2

ithDDox

on μQ

L

VVVWLμC

L

VVVLW

μC

1R

S

ch

C

Q

2

1ΔV Charge injection:

Bandwidth:S

2ch

Son CL

μQ

CR

1BW

2 2

ch S

S ch

Q L CΔV 1 L≈ =

BW 2 C μQ 2μPerformance FoM:

Technology scaling improves switch performance!

On-resistance:

Leakage in SC Circuits

– 39 –


EECT 7327Fall 2012

• I1 – diode leakage (existing in the old days too)• I2 – sub-threshold drain-source leakage of summing-node switch• I3 – gate leakage (FN tunneling) of amplifier input transistors• Leakage currents are highly temperature- and process-dependent; the

lower limit of clock frequency is often determined by leakage

Vo(t)

0 t

Ф1 Ф1Ф2 Ф2

Φ1 = “high”, Φ2 = “low”

Vi Vo

C2

C1

A0

Vx

Ф2 Ф2

Ф1 Ф1

VB

I2 I1I3

DS Leakage

– 40 –


EECT 7327Fall 2012

M1+

Vi+ Vo

+

Vo-Vi

-

CS+

CS-

VDD

M1-

VDD

Ф1 Ф1e

Ф1 Ф1e

Ф2

Ф2

CS+

CS-

Ф2e

Ф2e

• 0.13-μm CMOS• A0 = Gm·Ro = 90dB

• Ro ≈ 2MΩ

• Rleak ≈ 0.6V/3μA

≈ 0.2MΩ• A0 = Gm·(Rleak//Ro)

≈ 70dB

OutInM1

VDD

Φ Φ

ΦOut

Φ

Φ

ΦΦ

Φ

Φ

Φ

In

M3 M4

M2

M1

Ileak

VDD = 1.2V

VSS = 0V

Gate Leakage

– 41 –


EECT 7327Fall 2012

• Direct tunneling through the thin gate oxide

• Short-channel MOSFET behaves increasingly like BJT’s

• Violates the high-impedance assumption of the summing node

GSoxGS VtWLI expexp

Switch Size Optimization

– 42 –


EECT 7327Fall 2012

• To minimize switch-induced error voltages, small transistor size,slow turn-off, low source impedance should be used.

• For fast settling (high-speed design), large W/L should be used, and errors will be inevitably large as well.

Guidelines

• Always use minimum channel length for switches as long as leakage allows.

• For a given speed, switch sizes can be optimized w/ simulation.

• Be aware of the limitations of simulators (SPICE etc.) usinglumped device models.

– 43 –


EECT 7327Fall 2012

Nonideal Effects ofOp-Amps

Nonideal Effects of Op-Amps

– 44 –


EECT 7327Fall 2012

• Offset

• Finite-gain effects (voltage dependent)

• Finite bandwidth and slew rate (measured by settling speed)

Offset Voltage

– 45 –


EECT 7327Fall 2012

211 CVnVCnVQ osoi

212 1 CVnVCVQ osoos

1

11

2 1o i

C zV z V z

C z

Vi Vo

C2

C1Ф1

Ф2

Ф2

Ф1 Vos

Vo(t)

0 t

Ф1 Ф1Ф2 Ф2

Vi = 0

1

2

0 1i o o os

CV V n V n V

C

Autozeroing

– 46 –


EECT 7327Fall 2012

211 CVCVnVQ ososi

212 CVnVCVQ osoos

2

1

C

C

zV

zVzH

i

o

Vi Vo

C2

C1Ф1

Ф2

Ф2

Ф1

Vos

Ф1

• Also eliminates low-frequency noise, e.g., 1/f noise

• A.k.a. correlated double sampling (CDS)

Chopper Stabilization

– 47 –


EECT 7327Fall 2012

Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise chopper-stabilized differential switched-capacitor filtering technique,” IEEE Journal of Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981.

Vi VoA1

Vn2

A2

fC1

-1

A B

Chopper Stabilization

– 48 –


EECT 7327Fall 2012

Also eliminates DC offset

voltage of A1

Vi VoA1

Vn2

A2

fC1

-1

A B

|Vi|2

f0

SN(f)

f0

f0

|VA|2

|VB|2

f0

fC

fC

fC

fC

Chopper-Stabilized Differential Op-Amp

– 49 –


EECT 7327Fall 2012

Vi+

Vi-

Vo-

Vo+

Ф

Ф

Ф

Ф

Ф

Ф

Ф

Ф

• Integrators/amplifiers can be built using these op-amps

• Some oversampling is useful to facilitate the implementation

Ideal SC Amplifier

– 50 –


EECT 7327Fall 2012

1

2CL

CA

C

• Closed-loop gain is determined by the capacitor ratio by design

• But this is assuming X is an ideal summing node (the op-amp is ideal)

Vi ∞

C2

C1Ф1

Ф2

Ф1

VoX

Finite-Gain Effect in SC Amplifier

– 51 –


EECT 7327Fall 2012

1 1 1 2

1 22 2 2

2

11

1

oCL

i

V C C C CA

C CV C C C AC A

Vi A

C2

C1Ф1

Ф2

Ф1

VoX

1 1 1 1 2

1 1 1

0i x

x o x

Q V V C C

V V V A

1 2 1 1 2i x o xQ Q V C V C V V C

2 2 1 2 2 2

2 2

x o x

o x

Q V C V V C

V V A

o xV V A

– 52 –


EECT 7327Fall 2012

Practical Issues

Analog vs. Digital Supply Lines

– 53 –


EECT 7327Fall 2012

Sharing sensitive analog supplies with digital ones is a very bad idea.

Analogcircuits

Digitalcircuits

Pad

Pad

VDD CBP

id=dt

diLV d

L RiV dR RLDDA VVVV

Analog vs. Digital Supply Lines

– 54 –


EECT 7327Fall 2012

• Dedicated pads for analog and digital supplies

• On-chip bypass capacitors help (watch ringing)

• Off-chip chokes (large inductors) can stop noise propagation at board level

Analogcircuits

Digitalcircuits

Pad

Pad

VDD CBP

Pad

Pad

id=

“Supply” Capacitance

– 55 –


EECT 7327Fall 2012

• Any summing-node stray capacitance can be a potential coupling path.

• VDD, VSS, substrate, clock line, and digital noises, body effect, etc.

• Fully differential circuits help to reject common-mode noise and coupling.

Cp

…VDD

VSS

M2

M5

M3 M4

M7

M6

Vo

CC

Vi

C2

C1Ф1

Ф2

Ф2

Ф1

M1

S

Y

X

Cgs

Cgd

2C

CVV stray

o

“Supply” Capacitance

– 56 –


EECT 7327Fall 2012

• Avoid connecting bottom-plate parasitics to the summing node

• Avoid crossing other signal lines with the summing node

• Shielding can mitigate substrate noise coupling

n substrate

p+p well

Cbot

C2

Clock Generation

– 57 –


EECT 7327Fall 2012

• Clock-gated ring structure

• Non-overlapping time determined by inverter delays, sensitive to process, voltage, and temperature (PVT) variations

• DLL is an alternative, often used in high-speed designs

CLK Ф2

Ф1

Ф2

Ф1

– 1 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Switched-Capacitor Circuits.

Documents

chiu eect

noise slide

update slide

signal slide

capacitor ratio c

concept of switched

noise of sc integrator

pipelined adc slide