Unit 9 Multiplexers, Decoders, and Programmable Logic Devices Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science.
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Unit 9Unit 9Multiplexers, Decoders, and Multiplexers, Decoders, and
Programmable Logic DevicesProgrammable Logic Devices
Ku-Yaw ChangKu-Yaw Changcanseco@mail.dyu.edu.twcanseco@mail.dyu.edu.tw
Assistant Professor, Department of Assistant Professor, Department of Computer Science and Information EngineeringComputer Science and Information Engineering
Da-Yeh UniversityDa-Yeh University
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ContentsContents
9.19.1 Introduction Introduction9.29.2 Multiplexers Multiplexers9.39.3 Three-State Buffers Three-State Buffers9.49.4 Decoders and Encoders Decoders and Encoders9.59.5 Read-Only Memories Read-Only Memories9.6 Programmable Logic Devices9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.7 Complex Programmable Logic Devices9.89.8 Field Programmable Gate Arrays Field Programmable Gate Arrays
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Programmable Logic DevicesProgrammable Logic Devices
A general name for a digital integrated A general name for a digital integrated circuit capable of being programmed to circuit capable of being programmed to provide a variety of different logic functionsprovide a variety of different logic functions
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Programmable Logic ArraysProgrammable Logic Arrays
Performs the same basic function as a Performs the same basic function as a ROMROM n inputs and m outputsn inputs and m outputs
m functions of n variablesm functions of n variables
Differences in internal organizationDifferences in internal organization The decoder is replaced with an AND arrayThe decoder is replaced with an AND array OR arrayOR array
PLA : a sum-of-product expressionPLA : a sum-of-product expression
ROM : truth tableROM : truth table
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PLA StructurePLA Structure
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PLA with Three Inputs, Five PLA with Three Inputs, Five Product Terms, and Four OutputsProduct Terms, and Four Outputs
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AND-OR ArrayAND-OR Array
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PLA RealizationPLA Realization
ff11 = a’bd + abd + ab’c’ + b’c = a’bd + abd + ab’c’ + b’c
ff22 = c + a’bd = c + a’bd
ff33 = bc + ab’c’ + abd = bc + ab’c’ + abd
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PLA StructurePLA Structure
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PLA Table v.s. Truth TablePLA Table v.s. Truth Table
PLA TablePLA Table Each row represents a general product term.Each row represents a general product term. 0, 1, or more rows may be selected.0, 1, or more rows may be selected.
ROM Truth TableROM Truth Table Each row represents a minterm.Each row represents a minterm. Exactly one row will be selected.Exactly one row will be selected.
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PLAsPLAs
Mask-programmable PLAsMask-programmable PLAs Programmed at the time of manufactureProgrammed at the time of manufacture Similar to mask-programmable ROMSimilar to mask-programmable ROM
Field-programmable PLAs (FPLAs)Field-programmable PLAs (FPLAs) Use electronic charges to store a pattern in Use electronic charges to store a pattern in
the AND and OR arraysthe AND and OR arrays An FPLA with 16 inputs, 48 product terms and An FPLA with 16 inputs, 48 product terms and
8 outputs8 outputs8 functions of 16 variables8 functions of 16 variablesTotal number of product terms does not exceed 48Total number of product terms does not exceed 48
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Programmable Array LogicProgrammable Array Logic
PALPAL a special case of PLAa special case of PLA
AND array is programmableAND array is programmable
OR array is fixedOR array is fixed Less expensiveLess expensive Easier to programEasier to program
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PALPAL
A buffer is usedA buffer is used To drive many AND gate inputsTo drive many AND gate inputs
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PALPAL
Connections to the AND gate inputs are Connections to the AND gate inputs are represented by X’srepresented by X’s
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PAL segmentPAL segment
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Full AdderFull Adder
The logic equations for the full adder areThe logic equations for the full adder are
Sum = X’Y’CSum = X’Y’Cinin + X’YC’ + X’YC’inin + XY’C’ + XY’C’inin + XYC + XYCinin
CCoutout = XC = XCinin + YC + YCinin + XY + XY
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Full AdderFull Adder
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ContentsContents
9.19.1 Introduction Introduction
9.29.2 Multiplexers Multiplexers
9.39.3 Three-State Buffers Three-State Buffers
9.49.4 Decoders and Encoders Decoders and Encoders
9.59.5 Read-Only Memories Read-Only Memories
9.6 Programmable Logic Devices9.6 Programmable Logic Devices
9.7 Complex Programmable Logic Devices9.7 Complex Programmable Logic Devices
9.89.8 Field Programmable Gate Arrays Field Programmable Gate Arrays
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CPLDsCPLDs
As integrated circuit technology continues As integrated circuit technology continues to improve, more and more gates can be to improve, more and more gates can be placed on a single chip.placed on a single chip. Complex Programmable Logic Devices Complex Programmable Logic Devices
(CPLDs)(CPLDs)
When storage elements such as flip-flops When storage elements such as flip-flops are also included on the same IC, a small are also included on the same IC, a small digital system can be implemented with a digital system can be implemented with a single CPLD.single CPLD.
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ContentsContents
9.19.1 Introduction Introduction9.29.2 Multiplexers Multiplexers9.39.3 Three-State Buffers Three-State Buffers9.49.4 Decoders and Encoders Decoders and Encoders9.59.5 Read-Only Memories Read-Only Memories9.6 Programmable Logic Devices9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.7 Complex Programmable Logic Devices9.89.8 Field Programmable Gate Arrays Field Programmable Gate Arrays
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Field Programmable Gate ArraysField Programmable Gate Arrays
FPGAFPGA An IC contains an array of identical logic cells An IC contains an array of identical logic cells
with programmable interconnectionswith programmable interconnections
The user can programThe user can program Functions realized by each logic cellFunctions realized by each logic cell Connections between the cellsConnections between the cells
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Configurable Logic BlockConfigurable Logic Block
CLBCLB Two function generatorsTwo function generators
Four inputsFour inputs
Can implement any function of up to four variablesCan implement any function of up to four variables
Implemented as lookup tables (LUTs)Implemented as lookup tables (LUTs) Two flip-flopsTwo flip-flops Various multiplexers for routing signals within Various multiplexers for routing signals within
the CLBthe CLB
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Simplified CLBSimplified CLB
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Implementation of a LUTImplementation of a LUT
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Decomposition of Decomposition of Switching FunctionsSwitching Functions
To implement a switching function of more To implement a switching function of more than four variables using 4-variable than four variables using 4-variable function generatorfunction generator The function must be decomposed into The function must be decomposed into
subfunctionssubfunctions Each subfunction requires only four variablesEach subfunction requires only four variables
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Shannon’s Expansion TheoremShannon’s Expansion Theorem
Expand a function of the variables Expand a function of the variables aa,,bb,,cc, , and and dd about the variable about the variable aa : :
ff((aa,,bb,,cc,,dd) = ) = aa’ ’ ff(0,(0,bb,,cc,,dd) + ) + aa ff(1,(1,bb,,cc,,dd))
= = aa’ ’ ff00 + + aa ff11
ff00 = f = f(0,(0,bb,,cc,,dd): replace ): replace aa with 0 in with 0 in ff((aa,,bb,,cc,,dd) )
ff11 = f = f(1,(1,bb,,cc,,dd): replace ): replace aa with 1 in with 1 in ff((aa,,bb,,cc,,dd) )
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Expansion ExampleExpansion Example
ff((aa,,bb,,cc,,dd))
= = c’d’c’d’ + + a’b’ca’b’c + + bcdbcd + + ac’ac’
= = a’a’ ( (c’d’c’d’ + + b’cb’c + + bcdbcd) + ) + aa ( (c’d’c’d’ + + bcdbcd + + c’c’))
= = a’a’ ( (c’d’c’d’ + + b’cb’c + + cdcd) + ) + aa ( (c’c’ + + bdbd))
= = aa’ ’ ff00 + + aa ff11
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Expansion ExampleExpansion Example
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Shannon’s Expansion TheoremShannon’s Expansion Theorem
General form : expanding an n-variable General form : expanding an n-variable function about the variables function about the variables xxii : :
ff((xx1 1 , , xx2 2 ,…, ,…, xxi-1 i-1 , , xxi i ,, xxi+1 i+1 ,…, x,…, xnn))
= = xxi i ’ ’ ff((xx1 1 , , xx2 2 ,…, ,…, xxi-1 i-1 , 0, 0 ,, xxi+1 i+1 ,…, x,…, xnn) + ) +
xxi i ff((xx1 1 , , xx2 2 ,…, ,…, xxi-1 i-1 , 1, 1 ,, xxi+1 i+1 ,…, x,…, xnn))
= = xxi i ’ ’ ff00 + + xxi i ff11
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5-variable function5-variable function
ff((aa, , bb, , cc, , d, ed, e))
= = aa’ ’ ff((00, , bb, , cc, , d, ed, e) + ) + aa ff((11, , bb, , cc, , d, ed, e))
= = aa’ ’ ff00 + + aa ff11
Any 5-variable function can be realized Any 5-variable function can be realized using two 4-variable function generators using two 4-variable function generators and a 2-to-1 MUX.and a 2-to-1 MUX.
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5- and 6-variable functions5- and 6-variable functions
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SupplementSupplement
SIPSIP Single In-line PackageSingle In-line Package
DIPDIP Dual In-line PackageDual In-line Package
PGAPGA Pin Grid ArrayPin Grid Array
SIMMSIMM Single In-line Memory Single In-line Memory
ModuleModule
DIMMDIMM Dual In-line Memory Dual In-line Memory
ModuleModule
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SupplementSupplement
IEEE Standard 1164 defines a std_logic type IEEE Standard 1164 defines a std_logic type that has nine values:that has nine values:
U : UninitializedU : Uninitialized X : UnknownX : Unknown 0 : Logic 0 (driven)0 : Logic 0 (driven) 1 : Logic 1 (driven)1 : Logic 1 (driven) Z : High impedanceZ : High impedance
W : Weak 1W : Weak 1 L : Logic 0 (read)L : Logic 0 (read) H : Logic 1 (read)H : Logic 1 (read) - : Don’t care- : Don’t care
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