Unit 1 8086 Architecture

Microprocessor and Interfacing Techniques

Prof. Rajendra KhopeDepartment of ComputerMIT College of Engineering, Pune, India

Syllabus210249: Microprocessor and Interfacing

Techniques

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Syllabus

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Syllabus

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Syllabus

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Syllabus

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Features of 8086

8086 is a 16 bit microprocessor, It can perform read & write operation on both 8 or 16 bit data..

8086 has 16 bit data bus & 20 bit address bus.

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Features of 8086 ( continued)

20 bit address lines capable of addressing 1MB memory location

16 bit data are stored in 2 consecutive memory locations

8086 can generate 16 bit I/O address , 216 = 65536 I/O ports

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Features of 8086 ( continued)

8086 has fourteen 16 bit registers

8086 has multiplexed address & data bus

8086 operates in 2 modes , minimum( single processor ) & maximum( multi processor) modes

8086 has 6 byte pr-efetch instruction Queue

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Registers Organisation 16-Bit General Purpose Registers

– can access all 16-bits at once– can access just high (H) byte, or low (L) byte

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only the GeneralPurpose registersallow access as8-bit High/Lowsub-registers

Registers Organisation (continued)

Register Set16-Bit Segment Addressing Registers

CS Code SegmentDS Data SegmentSS Stack SegmentES Extra Segment

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Registers Organisation (continued)

16-Bit Offset Addressing RegistersSP Stack PointerBP Base PointerSI Source IndexDI Destination Index

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Registers Organisation (continued)

16-Bit Control/Status Registers- IP Instruction Pointer (Program Counter

for execution control)- FLAGS 16-bit register• It is not a 16-bit value but it is a

collection of 9 bit-flags (six are unused)• Flag is set when it is equal to 1• Flag is clear when it is equal to 0

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Architecture

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Architecture (continued)

The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU).

The BIU fetches instructions, reads and writes data, and computes the 20-bit address

The EU decodes and executes the instructions using the 16-bit ALU.

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Architecture (continued)

The BIU contains the following registers- IP - the Instruction Pointer

- CS - the Code Segment Register- DS - the Data Segment Register- SS - the Stack Segment Register- ES - the Extra Segment Register

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Architecture (continued)

The BIU fetches instructions using the CS and IP, written CS:IP, to construct the 20-bit address.

Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode

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Architecture (continued)

The EU contains the following 16-bit general purpose registers:

» AX - the Accumulator» BX - the Base Register» CX - the Count Register» DX - the Data Register» SP - the Stack Pointer \ defaults to» BP - the Base Pointer / Stack segment» SI - the Source Index Register» DI - the Destination Register

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Architecture (continued)

HIGH BYTE GP REGISTERS LOW BYTE

AHBHCHDH

AXBXCXDX

ALBLCLDL

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8 BIT 16 BIT 8 BIT

Architecture (continued)

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CSSSDSIP

AHBHCHDH

ALBLCLDL

SPBPSIDI

FLAGS

AXBXCXDX

Extra SegmentCode SegmentStack SegmentData SegmentInstruction Pointer

AccumulatorBase RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register

BIU registers

(20 bit adder)

EU registers

16 bit arithmetic

ES

General purpose Registers

AX Accumulator Register Preferred register to use in arithmetic, logic

and data transfer instructions because it generates the shortest Machine Language Code

Must be used in multiplication and division operations

Must also be used in I/O operations

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General purpose Registers (conti..)

BX Base Register Also serves as an address register Used in array operations Used in Table Lookup operations (XLAT )

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General purpose Registers (conti..)

CX Count register Used as a loop counter Used in shift and rotate operations

DX Data register Used in multiplication and division Also used in I/O operations

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Pointer & Index Registers

Contain the offset addresses of memory locations

Can also be used in arithmetic and other operations

SP: Stack pointer Used with SS to access the stack segment

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Pointer & Index Registers (continued)

BP: Base Pointer Primarily used to access data on the stack Can be used to access data in other

segments SI: Source Index register

is required for some string operations When string operations are performed, the SI

register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations.

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Pointer & Index Registers (continued)

DI: Destination Index register is also required for some string operations. When string operations are performed, the DI

register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations.

The SI and the DI registers may also be used to access data stored in arrays

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Segment Registers

Are Address registers Store the memory addresses of instructions

and data Memory Organization

Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 meg of addressable memory

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Segment Registers (continued)

Addresses are expressed as 5 hex digits from 00000 - FFFFF

Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!

Solution: Memory Segment• Block of 64K (65,536) consecutive memory

bytes• A segment number is a 16 bit number

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Segment Registers (continued)

Segment numbers range from 0000 to FFFF

Within a segment, a particular memory location is specified with an offset

An offset also ranges from 0000 to FFFF

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Segment Registers (continued)

If the segment address is for example, 2915, then the addresses in this segment start at 2915:0000 and go up to 2915:FFFF, which is the highest address in this particular segment.

This range expressed in terms of absolute or physical addresses is from 29150 through 3914F. The relationship between a segment and the register which defines it is shown below.

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Segment Registers (continued)

31Memory Model for 20-bit Address Space

Memory Segmentation

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Memory Segmentation

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Memory Address Generation

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Physical Address (20 Bits)

Adder

Segment Register (16 bits) 0 0 0 0

Offset Value (16 bits)

Memory Address Generation

to calculate physical memory address

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Flag Register

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Carry flag

Parity flag

Auxiliary flag

Zero

Overflow

Direction

Interrupt enable

Trap

Sign6 are status flags3 are control flag

Pinout Diagram

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Minimum mode operation

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Ground

Power Supply5V 10%

ClockDuty cycle: 33%

ResetRegisters, seg regs,

flagsCS: FFFFH, IP: 0000H If high for minimum 4

clks

Minimum mode operation ( Conti..)

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Address/Data Bus:Contains address bits A15-A0 when ALE is 1 & data bits D15 – D0 when ALE is 0.

Address Latch Enable:When high, multiplexed address/data bus contains address information.

Minimum mode operation ( Conti..)

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INTERRUPT

Non-maskable interrupt

Interrupt acknowledgeInterrupt request

Minimum mode operation ( Conti..)

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Direct Memory Access

Hold acknowledge

Hold

Minimum mode operation ( Conti..)

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Address/Status BusAddress bits A19 – A16 & Status bits S6 – S3

S6: Logic 0.

S5: Indicates condition of IF flag bits.

S4-S3: Indicate which segment is accessed during current bus cycle:

Minimum mode operation ( Conti..)

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Bus High Enable/S7Enables most significant data bits D15 – D8 during read or write operation.S7: Always 1.

BHE#, A0:0, 0: Whole word (16-bits)

0,1: High byte to/from odd address

1,0: Low byte to/from even address

1,1: No selection

Minimum mode operation ( Conti..)

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Min/Max modeMinimum Mode: +5VMaximum Mode: 0V

Min mode pins

Minimum mode operation ( Conti..)

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Minimum mode operation ( Conti..)

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Minimum mode operation ( Conti..)

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Minimum mode operation ( Conti..)

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Read Signal

Write Signal

Memory or I/0

Data Bus EnableUsed by external data bus buffers

Maximum mode operation

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Maximum mode operation ( Conti..)

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Maximum mode operation ( Conti..)

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Status SignalInputs to 8288 to generate eliminated signals due to max mode.

S2 S1 S0 000: INTA001: read I/O port010: write I/O port011: halt100: code access101: read memory110: write memory111: none -passive

Maximum mode operation ( Conti..)

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DMA Request/Gra

nt

Maximum mode operation ( Conti..)

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Lock Output

Lock OutputUsed to lock peripherals off the systemActivated by using the LOCK: prefix on any instruction

Maximum mode operation ( Conti..)

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Queue StatusUsed by numeric coprocessor (8087)

QS1 QS000: Queue is idle01: First byte of opcode10: Queue is empty11: Subsequent byte of opcode

Address Decoding

I/O: Memory mapped I/O & I/O Mapped I/O

Memory mapped IO Uses the same address bus to address both

memory and I/O devices, and the CPU instructions used to access the memory are also used for accessing devices

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Minimum mode operation ( Conti..)

I/O mapped IO, PORT mapped IO, Peripheral IO Uses a special class of CPU instructions

specifically for performing I/O. Specifically the IN and OUT instructions which can read and write one to four bytes to an I/O device. I/O devices have a separate address space from general memory

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