Tools - Design Entry - Chapter 4 slide 1 FPGA Tools Course Design Entry.
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Tools - Design Entry - Chapter 4 slide 1
FPGA Tools Course
Design Entry
Tools - Design Entry - Chapter 4 slide 2
Objectives
• Understand how to use components to utilize FPGA architectural resources– Describe the contents of the Xilinx Unified Library.
– Explain the naming conventions associated with the Xilinx Unified Library components.
• Learn some basic guidelines for successful design entry– Net naming
– Legal and readable names
– Hierarchical design techniques
Tools - Design Entry - Chapter 4 slide 3
Outline
• Introduction to the Xilinx Unified Library• Guidelines and Hints for successful design entry• Summary
Tools - Design Entry - Chapter 4 slide 4
Xilinx Unified Library
• The Xilinx Unified Library contains functions of SPECIFIC SIZE ONLY
• To get a smaller function, do not connect all of the symbol outputs. The M1 optimizer will remove the unused logic.
• Components are optimized for each device family
• Xilinx library components are fast, small and easy to use– Larger components have an optimized layout
– Components use the best resources available for each function
Tools - Design Entry - Chapter 4 slide 5
Unified Library Contents
• Combinatorial logic functions ( such as AND gates )– AND, INV, NAND, OR, NOR, XNOR, and XOR– Functions range in size from 2 to 9 inputs
• Flip-flops, I/O buffers, tri-state buffers, and other architectural feature symbols
• Large components with fixed sizes and options ( such as counters, adders, accumulators, etc. )
Tools - Design Entry - Chapter 4 slide 6
Architectural Feature Components
• BUFT - internal tri-state buffers
• BUFG - global clock buffer used for high fanout signals
• IBUF/OBUF - input/output buffers used to bypass the IOB registers
• IPAD/OPAD - input/output pads necessary to make pin assignments
• ILD/IFD/OFD - IOB latch and flip-flops
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Large Components• Arithmetic Functions - Full Adders, Accumulators, and Adder/Subtractors
• Comparators - identity and magnitude
• Counters - binary, BCD, Johnson, Ripple, and Carry Logic
• Data Registers and Shift Registers
• Decoders and Multiplexers
• Flip-flops and Latches - D, T, JK, loadable, asynchronous/synchronous controls
Tools - Design Entry - Chapter 4 slide 8
Special Components
• High Speed/Low Skew Clocks - BUFG, BUFGS, etc.
• Boundary Scan Component - BSCAN
• Global Reset - STARTUP allows access to global set/reset network and the global tri-state network
• On-Chip Oscillator - OSC4 allows the use of the internal configuration clock for applications that do not require significant accuracy
Tools - Design Entry - Chapter 4 slide 9
Naming Conventions
• Combinatorial Naming Conventions– <Logic Function><number of inputs> (such as AND2)– An inverter can always be inserted to get the desired logic– Customers frequently use the combinatorial logic elements (AND4, XNOR9, etc.) in their
designs
• Component Naming Conventions– <function><width><control inputs>– CB4CLE = Counter, Binary, 4 bits, Clear, Load, Enable– FD16RE = Flip-flops, D-type, 16 bits, Reset, Enable– Control inputs are referenced by a single letter
* C = asynchronous clear* R = asynchronous reset* listed in order of precedence
Tools - Design Entry - Chapter 4 slide 10
Outline
• Introduction to the Xilinx Unified Library
• Guidelines and Hints for successful design entry
• Summary
Tools - Design Entry - Chapter 4 slide 11
Instance Names (1)• If you do not provide instance names, your design entry tools
will create them for you. Example: $I152. – Reports are more readable if you create effective instance names.
• Instance names are also made by nets connected to flip-flop outputs.– Name the busses and nets connected to flip-flops.
• An IOB is named by the net between the pad and I/O function primitives.
IN1
IOB IN1
D QQ2
CLB Q2
Tools - Design Entry - Chapter 4 slide 12
Instance Names (2)
• Components and nets especially important to name:– Hierarchical blocks
– Flip-Flop controls
* Clocks, clock-enables, resets, etc.
– Flip-Flop outputs
– Both sides of Input and Output buffers
– High fanout signals
Tools - Design Entry - Chapter 4 slide 13
Instantiation of IO Blocks (1)• Most users explicitly define resources to be used in the IOB• I/O components are defined with
– One pad primitive– At least one function primitive
* Buffer, Flip-Flop, or Latch
• Input Examples:
• Recommendation: Keep I/O at the top level of the design.
IPADIN1_PAD
IOB IN1_PAD
IBUFIPADIN2_PAD
IOB IN2_PAD
ILD
Tools - Design Entry - Chapter 4 slide 14
OPADOUT1_PAD
IOB OUT1_PAD
OBUF OPADOUT2_PAD
IOB OUT2_PAD
OFD
Instantiation of IO Blocks (2)
• Output Examples:
IOB B15BI5
IOPAD
IFD
OFDT
• Bi-directional Example: OFDT contains Three-State Buffer which drives net B15
Tools - Design Entry - Chapter 4 slide 15
Use Legal and Readable Names
• Allowable characters– Alphanumeric: A - Z, a - z, 0 - 9, Underline _, Dash -
– Reserved characters
* Angle brackets for buses <>
* Slash / for hierarchy
* Dollar sign $ for instance names
• Names must contain at least one non-digit• Names may be case sensitive
– Depends on design entry tool and/or language
• Avoid using names that correspond to device resources– CLB row/column locations: AA, AB, etc.
– IOB pin locations: P1,P2, etc.
Tools - Design Entry - Chapter 4 slide 16
Hierarchical Design Techniques
• Use of hierarchy...– Adds logical structure to all designs
– Makes debugging with a simulator easier
– Enables re-using of macros
– Enables each macro to be entered by the most efficient design entry technique
– Encourages team design
– Makes timing specifications and incremental design more effective
Tools - Design Entry - Chapter 4 slide 17
Hierarchy Guidelines
• Keep I/O pads on top level• Create macros for common functions
– Do not save user-defined macros in vendor-supplied library
* Future software updates may overwrite the library
• Do not leave macro inputs floating– Check Libraries Guide for information
• Instance names preserve hierarchical references– SUB2/NET5
• There is no direct limit on the number of levels– However, many levels of hierarchy result in long net names
Tools - Design Entry - Chapter 4 slide 18
Constraining a Design
• Timing and layout requirements can be specified– In a text constraints file (design.UCF)
– In source schematics
– May be derived from Synthesis constraints (tool dependent)
• Carry-logic based functions are always Relationally-Placed Macros (RPMs)
• Basic and Advanced Constraints are covered later
Tools - Design Entry - Chapter 4 slide 19
Outline
• Introduction to the Xilinx Unified Library• Guidelines and Hints for successful design entry
• Summary
Tools - Design Entry - Chapter 4 slide 20
• The Xilinx Unified Library contains standard size pre-optimized components, combinatorial logic functions, basic architectural features, and some special components.
• Inserting a component into a project’s schematic or HDL code is the best way to utilize the FPGAs architectural features.
• Refer to the Xilinx Data Book in the DynaText Browser for more information about Xilinx’s device offerings.
• Refer to the Libraries Guide in the DynaText Browser for more information about the members of the Xilinx Unified Library.
Summary
Tools - Design Entry - Chapter 4 slide 21
Questions
• What function does the CB4CLE perform? – What control signals does it have?
– What is the priority of the control signals?
• Name one example of a special component from the Xilinx Unified Library.
• The best way for a synthesis user to control the specific architectural features used in a design is by instantiating a component. (True/False)
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