Text Book: Silicon VLSI Technology Fundamentals, Practice ...zyang/Teaching/20182019... · Silicon VLSI Technology Fundamentals, Practice and Modeling Authors: J. D. Plummer, M. D.
Post on 02-Apr-2020
60 Views
Preview:
Transcript
Oxidation - Chapter 6
Text Book:Silicon VLSI Technology
Fundamentals, Practice and Modelingg
Authors: J. D. Plummer, M. D. Deal, and P. B. Griffina d G
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Oxidation - Chapter 6
THERMAL OXIDATION • SiO2 and the Si/SiO2 interface are the principal reasons for silicon’s
dominance in the IC industry.
SiO2:
1 µm Field Oxides
Thermally Grown OxidesOxide
Thickness
Deposited Oxides
Backend InsulatorsBetween Metal Layers
2• Easily selectively etched using
lithography.• Masks most common impurities
(B P As Sb)
10 nm
0.1 µm Masking Oxides
Pad Oxides
Masking Oxides
(B, P, As, Sb).• Excellent insulator
( ).• High breakdown field ρ > 1016 Ωcm, Eg > 9 eV
1 nm
Gate OxidesTunneling Oxides
Chemical Oxides from CleaningNative Oxides
( )• Excellent junction passivation.• Stable bulk electrical properties.• Stable and reproducible
107 Vcm -1
• Stable and reproducible interface with Si.
• No other known semiconductor/insulator combination has properties that h th Si/SiO i t f
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
2
approach the Si/SiO2 interface.
Oxidation - Chapter 6
SIA NTRS RoadmapYear of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018
Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm
MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm
DRAM Bits/Chip (Sampling) 256M 512M 1G 4G 16G 32G 64G 128G 128G
MPU Transistors/Chip (x106) 550 1100 2200 4400 8800 14,000
Gate Oxide Tox Equivalent (nm)
MPU
1.2 0.9 0.7 0.6 0.5 0.5
Gate Oxide Tox Equivalent (nm)
Low Operating Power
1.5 1.2 0.9 0.8 0.7 0.7
p g
Gate Dielectric Leakage
(nA/µm @ 100˚C) MPU
170 230 330 1000 1670 1670
Thickness Control (% 3σ ) < ±4 < ±4 < ±4 < ±4 < ±4 < ±4
• SiO2 is not the gate dielectric of the future
Min Supply Voltage (volts) 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.8-1.1 0.7-1-0 06-0.9 0.5-0.8 0.5-0.7
dAC ⋅⋅
= 0εκ
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
• High-K dielectrics are now being used to reduce leakage
3
d
Oxidation - Chapter 6
Si and SiO2
• Oxidation occurs at the Si/SiO2interfaceA Si l ill idi t• A pure Si layer will oxidize at room temperature
– Rapid growth to 0.5 to 1 nm (5 10 Angstroms)
Deposited Polysilicon
(5-10 Angstroms)– Final growth of 1-2 nm
• Oxidation involves a volume expansion
SiO2
Original Si SurfaceVolume Expansion
Location of Si3N4 Mask
expansion– SiO2 is 30% larger than Si– Volume expansion 1.33 ~ 2.2
• Induces stress where confined
Si Substrate
• Induces stress where confined, especially in 2D and 3D structures, stress effects play a dominant role.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
dominant role.
4
Oxidation - Chapter 6
Basic Concept
• O2 or H20 diffuse to Si interfaceO2 or H20 diffuse to Si interface
• Oxidation reaction consumes silicon moving the interface down and the SiO2 up as material 2is consumed and the volume increases
SiO2 volume expansion can cause stress on the surface
11
SiO2 volume expansion can cause stress on the surface• 30 % expansion in all directions when unconstrained• Stress induced when volume constrained
1
1
1
1
1.2
1
1
1
1.3
1.3
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
5
1.3Si substrate Si substrate
Oxidation - Chapter 6
SEM of LOCOS
Bird’s Beak Topology lateral growth
Volume Expansion
Deposited Polysiliconp y
Location of Si3N4 M
SiO2
Original Si SurfaceVolume Expansion
Si3N4 Mask
Si SubstrateStress at the
Si/Si3N4 interface
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
6
Oxidation - Chapter 6
Structure of Silica GlassSh t d A h h dShort range order maintained
Amorphous material Non-bridging oxygen in
fused Silica (not present in crystalline SiO2)
hydrogen
Si can be replaced by deposits. B,P,As or Sb = network formers.
Network modifier ----> Qm
• SiO is amorphous even though it grows on a crystalline substrate (Figure 3 15)• SiO2 is amorphous even though it grows on a crystalline substrate (Figure 3-15)– Based on SiO4 tetrahedra shown above. – Bridging oxygen atoms share to form crystal like quartz– Time to form appropriate rotational forms for full crystallization not
available; therefore forms rarely observed in IC
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ7
available; therefore, forms rarely observed in IC– Lattice doesn’t match Si, but there is a short range order
Oxidation - Chapter 6
Si/SiO2 Stresses• Compressive stress due to constrained growth region
– Grow upward– Stress as large as 5 x 109 dyne cm-2
• At high temperature, viscous flow may reduce stress
• There is a large difference in the thermal expansion coefficients– Stress as large as 1-2 x 109 dyne cm-2
• Wafer curvature can be produced from unbalanced stress between the top and bottom of a wafer– Selective etching of one surface will produce curvature
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Selective etching of one surface will produce curvature
8
Oxidation - Chapter 6
Oxide Layer: Intel 90 nm Process
• SiO2 is amorphous even though it grows on a crystalline substrateon a crystalline substrate
– Lattice doesn’t match Si– There is a short range order
I t l SiO f 3 5 t i l• Intel SiO2 of approx. 3-5 atomic layers• http://leitl.org/docs/intel/90nm_press_briefing-technical.pdf
• Deal and Grove (1965) showed that SiO2 growth follows a linear parabolic law.
Wh d l i d t thi id id i i d bi t– Where model inadequate: thin oxides, oxides grown in mixed ambient, oxides grown on 2D and 3D Si surfaces, oxides grown on heavily doped substrates
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
9
Oxidation - Chapter 6
Oxide Growth Charges
+++ -
--
K+
Na+SiO2
Qm
Qot• Four charges are associated with
insulators and insulator/semiconductorinterfaces
++++ + xxxxxxTransition
RegionQf
Qit
interfaces.• Qf - fixed oxide charge• Qit - interface trapped charge• Qm - mobile oxide chargeQit
Silicon • Qot - oxide trapped charge
• Deal defined nomenclature in 1980 for electrical charge defects
• Processing to reduce charges:– High temperature inert anneals in Ar or N2 toward the end of process flow.– Moderate temperature anneal (400 ºC) in H2 or forming gas (N2/H2)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
10
Oxidation - Chapter 6
Wafer Fabrication EquipmentQuartzTube
Wafers
• Oxidation systems are conceptually very simple.– Dry or wet, 600 – 1200 ºC
I ti t d ti l fQuartz Carrier
Resistance Heating
• In practice today, vertical furnaces, RTO systems and fast ramp furnaces all find use.
H2O2 Gate OxidesLOCOSor STI DRAM Dielectrics
• Thermal oxidation canpotentially be used in manyplaces in chip fabrication.In practice, deposited SiO2In practice, deposited SiO2layers are increasingly beingused (lower Dt).
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ11
Oxidation - Chapter 6
Conventional Oxidation SystemWafer loading should use cantilever or elavators (perpendicular) to avoid
Vertical furnaces are also used. Better uniformity, easier automation, cleaner -
3 zones
touching the walls.automation, cleaner no contact with the tub
+ 0.5 ° C
Ramping of T from/to 800 °C ( 10 °C/sec)
Add HCl or TCA for gettering purpose (metals, Na +)
Dry or wet oxidation
At 1000 °C, in wet O2 is approx. 0.1 nm per second. It approx. doubles for every 100 °C rise,
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ12
At 1000 C, in wet O2 is approx. 0.1 nm per second. It approx. doubles for every 100 C rise,
Oxidation - Chapter 6
Rapid Thermal Oxidation• http://www.iue.tuwien.ac.at/phd/hollauer/node13.html
• Reduced time for temperature ramp– 100 ºC per second vs. <10 ºC per second
• Reduced size chamber for smaller number of wafersReduced size chamber for smaller number of wafers– Single wafer vs. multiple boats of 10-50 wafers
• Simple temperature feedback– Pyrometer monitors wafer vs. multiple zones with thermocouple
that are preset at installation (need +/- 0.5 ºC control)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
13
Oxidation - Chapter 6
Measurement Methods
• Physical• Optical• Optical• Electrical Devices (MOS Capacitor gate)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
14
Oxidation - Chapter 6
Physical Step Height Measurement• By etching away part of the SiO2, the resulting step
height between the original Si and new SiO2 height can be made.
Atomic Force Microscope• Atomic Force Microscope– Technique to visual Figure 1-3
• Cross section wafer and use an SEM– As in Figure 6-4 or a TEM in Figure 3-15
SiO2
Deposited Polysilicon
Original Si SurfaceVolume Expansion
Location of Si3N4 Mask
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
15
Si Substrate
Oxidation - Chapter 6
Optical Measurement• Optical (usually non destructive): thick oxides (color chart, ellipsometry, reflectance)
but for thin oxides: ellipsometry
R f tiREFLECTANCE
white or monochromatic light
Refraction indexes
Color chart (xox > 50nm) –> not destructive interference will affect the reflected light –> color correlated with thickness of a dielectric layer (10-20 nm accuracy)
For monochromatic light minima and maxima in the reflected beam
( )
L321atmaxima
cos2 01
=
⋅⋅⋅=
mm
xn βλ
allows to determine xox (fringes, spectrometers with sweeping wavelength λ for fixed φ we can find extrema). [Good for a few tens of nm]
Ellipsometry uses polarized light and detect the change in polarization
L
L
,25,
23,
21atminima
,3,2,1atmaxima
=
=
m
m
( )⎞⎛ i φ
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ16
Ellipsometry uses polarized light and detect the change in polarization of the reflected light due to a film (thickness, index of refraction)
( )⎟⎟⎠
⎞⎜⎜⎝
⎛ ⋅=
1
0 sinarcsinn
n φβ
Oxidation - Chapter 6
Optical MethodsO ti l l tt• Optical color pattern– http://cleanroom.byu.edu/color_chart.phtml– Color Chart description in Table A.7 on p. 790p p
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
17
Oxidation - Chapter 6
Electrical Measurements• Direct electrical measurement of device type
parameters• Oxides are typically used as the dielectric layer in a
capacitorDoped silicon conductor SiO dielectric doped polysilicon or– Doped silicon conductor, SiO2 dielectric, doped polysilicon or metal conductor layers similar to an MOS transistor.
• Typically Capacitance-Voltage or C-V measurements are taken– A DC bias with an AC voltage source to measure changes inA DC bias with an AC voltage source to measure changes in
impedance with frequency– Widely used for MOS devices, gate oxide parameters, and
carrier lifetimes
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
carrier lifetimes
18
Oxidation - Chapter 6
C-V MeasurementsC+ VGDC bi + ll AC Ca)
CO
CO
e-
+ VG
a) Accumulationmajority carrier drawn to surface
• DC bias + small AC high frequency signal applied.
N Silicon Doping = N D
VG+-
ox
oxox x
AC ⋅=
εdVdQC =
C
+ + + +++ +
b)
COCO
CDxD
- VG b) Depletionminority carrier drawn to surfacemajority carriers
Charge Density
xNQQ ==
)
e-
VG+-
majority carriers repelled
DDDG xNQQ ==
D
SiD x
AC ⋅=
ε
C
+ + + ++ +++ +
+++ +
+
c)
COCO
-- VG
QG
QIQD CDMinxDMax
c) Inversionminority carrier
Dx
IDDG QxNQ +=
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
19
+
Holes
e-
VG+- VTH
layer exists
Oxidation - Chapter 6
C-V PlotC
Ideal LF Cox
accumulation
depletionQI follows QG @ Low freq C =COX
Ideal HF
Deep Depletion
CMin
inversionQD follows QG @ High freq C ~ f(COX, CD )
Deep Depletion
DC Gate VoltageVTH
• LF curve - inversion layer carriers can be created and recombine at AC signal frequency so Cinv is just Cox.
• HF curve (100 kHz to 1 MHz) - inversion layer carriers cannot be generated fast enough to follow the AC signal so Cinv is Cox + CD.
• Deep depletion - “DC” voltage is applied fast enough that inversion layer carriers cannot follow it so C must expand to balance the charge on the gatecannot follow it, so CD must expand to balance the charge on the gate.
• C-V measurements can be used to extract quantitative values for:– tox - oxide thickness– N - the substrate doping profile
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
20
– NA - the substrate doping profile– Qf, Qit, Qm, Qot - oxide, interface charges
Oxidation - Chapter 6
MOS C-V Band Diagram
XD= XDmax QD fixed
XD> XDmax
*
Holes generated in the depletion layer and attracted by the gate
th DL h |V | isource the DL when |VG| increases
To avoid deep, WqnJnU
G
igen
G
i =−=ττ
High frequency AC signal changes faster than QI can respond (generation is slow)
ΔQ ΔQ
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ21
To avoid deep depletion*:
sec/1.0 VCWqn
CJ
CJ
dtdV
OXA
i
OX
gengen
GG
≈=≈≤τ
ΔQG = ΔQD
xD = xD max → CD = CD max
Oxidation - Chapter 6
Charges Derived
Qm, Qot have similar effect as Qf (shift characteristics) Due to traps
Traps cannot charge or discharge - do not respond to HF signal
Qi respond to DC voltage – stretch out change in EF (VG), charges at Eit.
Stress of the oxide (ex. charge injection, di ti ) C V d d ti ( ti t
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ11
radiation) C-V degradation ( time to breakdown, charge to breakdown)
Oxidation - Chapter 6
Models and Simulation• Deal-Grove Model Plots
0.7 2
0.5
0.6
1200ÞC 1.5 1100 ÞC
0.3
0.41100ÞC
1000ÞC
1
1000 ÞC
900 ÞC
0
0.1
0.21000ÞC
900ÞC800ÞC
0
0.5
700 ÞC
800 ÞC
00 2 4 6 8 10
Time - hours
00 1 2 3 4 5 6 7 8 9 10
Time - hours
Oxidation rate for (100) silicon in dry O2. Oxidation rate for (100) silicon in wet O2.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
12
Oxidation - Chapter 6
Deal Grove Model
CG
xO0.01 - 1 µm - 500 µm
• The basic model for oxidation was developed in
CO
CS
p1965 by Deal and Grove.
• A linear parabolic model
Si + O2 → SiO 2 (2)
Oxide
CICI
Gas Silicon
F F F
Si + O2 → SiO 2
Si + 2H 2O → SiO 2 + 2H 2
( )
(3)
F1 F2 F3
F1: Transport of Oxygen to oxide surfaceGas phase diffusion through stagnant boundary layerE ilib i t ti i lid (b d ti l )Equilibrium concentration in a solid (based on partial pressures)
F2: Diffusion of oxidant through the oxide F3: Reaction with the Silicon surface
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
13
In steady-state, F1 = F2 = F3 where flux is in molecules cm-2 sec-1
Oxidation - Chapter 6
Deal Grove Model0 01 1 µm 500 µm
CG
CS
xO0.01 - 1 µm - 500 µm
Diffusion of oxidant through the oxide
Oxide
CI
CO
CI
Gas Silicon⎟⎟⎠
⎞⎜⎜⎝
⎛ −=−=
O
IO
xCCD
xCDF
∂∂
2
Fick’s Law - Diffusivity
F1 F2 F3
Transport of Oxygen to oxide surface Ideal Gas Law
The gradient is approx. a constant
( )SGG CChF −=1Reaction with the Silicon surface
Interface reaction rateMass transport coefficient
kTPC
kTPC
SS
GG
=
=
ISCkF =3Surface – Henry’s Law
SO PHC ⋅=
OG
PPCPHC ≈⋅=*
kT
( )OG CCkTH
hF −⋅⋅
=∴ *1
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
14
GS PP ≈∴
Oxidation - Chapter 6
Deal-Grove Model (2)U d t d t t diti F F F• Under steady state conditions, F1 = F2 = F3 so
Dxk
C
Dxk
hk
CCOSOSS
I
+≅
++=
11
**
( )OCChF −⋅= *1
⎞⎛ DDh
*
*
1
1Cxkk
DxkC
COSS
OS
O ≅++
⎟⎠⎞
⎜⎝⎛ +
=
⎟⎟⎠
⎞⎜⎜⎝
⎛ −=
O
IO
xCCDF2
ISCkF =3
h very large and can be neglected
1Dh
OSS ++
• Note that the simplifications are made by neglecting 1/h where h large. This results in is a very good approximation. y g pp
• Combining the above, we have
CkFdx *Fdx
⎟⎠⎞
⎜⎝⎛ ++
==
Dxk
hkN
CkNF
dtdx
OSS
S
111
ISCkF =31N
Fdtdx
=
Oxygen molecules incorporated per unit
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
15
volume of oxide grown
Oxidation - Chapter 6
Deal-Grove Model (3)
⎟⎠⎞
⎜⎝⎛ ++
==
Dxk
hkN
CkNF
dtdx
OSS
S
11
*
1
X
∫∫ ⋅=⋅⎟⎠⎞
⎜⎝⎛ ++⋅
t
S
X
X
OSS dtCkdxDxk
hkN
O
I 0
*1 1
txxxx iOiO =−
+− 22
tABB
=+/
where (parabolic rate constant, F2 dominant)1
*2NDCB =
1
*
1
*
11 NkC
hkN
CAB S
S
≅
⎟⎟⎠
⎞⎜⎜⎝
⎛+
=(linear rate constant , F3 dominant) and
Defining initial conditions of the interface:AB
xBx ii
/
2
+=τ
xx2
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
16
τ+=+ tAB
xBx OO
/
Oxidation - Chapter 6
Deal-Grove Model (4)
• Solving for oxide thickness as a function of time.
xx2
τ+=+ tAB
xBx OO
/
( ) 02 =+⋅−⋅+ τtBxAx OO
( )⎭⎬⎫
⎩⎨⎧
−+
+= 14/
12 2 BA
tAtxOτ
For thin oxide, x small
xxx2
For thick oxide, x large
τ+=⇒+ tAB
xAB
xBx OOO
//
( )τ+⋅= tBAxO
τ+=⇒+ tBx
ABx
Bx OOO
22
/
( )τ+⋅= tBxO2
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
17
Oxidation - Chapter 6
Deal-Grove Model (5)
⎭⎬⎫
⎩⎨⎧
−+
+= 14/
12 2 BA
tAxOτ
xx ii2
+=τ
1
*2NDCB = F2 dominant
ABB /+=τ
1
*
1
*
11 NkC
hkN
CAB S
S
≅
⎟⎟⎠
⎞⎜⎜⎝
⎛+
= F3 dominant
ks x0/D <<1
CI ≈ C*
ks x0/D >>1
For about 50-200 nm.
CI ≈0
k D(T)
Fast reaction -diffusion limits
Diffusion fast compared to chemical reaction for thin oxides.
ks, D(T) oxidation (thick oxides)
A ( )τ+⋅= tBxO2
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ18
( )τ+⋅= tBAxO
( )O
Oxidation - Chapter 6
• The rate constants B and B/A have physical meaning (oxidant diffusion and interface reaction rate respectively).
( )Ambient B B/A ( )kTECB /exp 11 −=
( )kTECAB /exp 22 −=
Ambient B B/A
Dry O2 C1 = 7.72 x 102 µ2 hr-1
E1 = 1.23 eVC2 = 6.23 x 106 µ hr-1
E2 = 2.0 eV
Wet O2 C1 = 2.14 x 102 µ2 hr-1
E 0 71 VC2 = 8.95 x 107 µ hr-1
E 2 05 VE1 = 0.71 eV E2 = 2.05 eV
H2O C1 = 3.86 x 102 µ2 hr-1
E1 = 0.78 eVC2 = 1.63 x 108 µ hr-1
E2 = 2.05 eV
800900100011001200T (ÞC)
• Numbers are for (111) silicon,for (100) divide C2 by 1.68.
10
100 800900100011001200
B/A H2O
0 01
0.1
1
B µ
m2
hr- 1
B/A
µm
hr
- 1
B/A Dry O2
B H2O • Plots of B, B/A using the values in the above Table.
0.0001
0.001
0.01B Dry O2
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
19
0.65 0.7 0.75 0.8 0.85 0.9 0.95 11000/T (Kelvin)
Oxidation - Chapter 6
Deal-Grove Model
0.6
0.7
1 5
2
1100 ÞC
0 3
0.4
0.51200ÞC
1100ÞC1
1.5 1100 ÞC
1000 ÞC
0.1
0.2
0.3
1000ÞC
900ÞC
0.5
900 ÞC
800 ÞC
00 2 4 6 8 10
Time - hours
900ÞC800ÞC
00 1 2 3 4 5 6 7 8 9 10
Time - hours
700 ÞC
800 ÞC
Oxidation rate for (100) silicon in dry O Oxidation rate for (100) silicon in wet O
• Wet O2 rate is significantly higher than dry O2. The oxidant solubility is higher. • Dry O2 used for thin oxides and controlled depths, wet O2 for thicker films.
Oxidation rate for (100) silicon in dry O2. Oxidation rate for (100) silicon in wet O2.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
y 2 p , 2
20
Oxidation - Chapter 6
Example Problem 6.130.7 2
0.5
0.6
1200ÞC 1.5 1100 ÞC
c)
0.3
0.41100ÞC
1000ÞC
1
1000 ÞC
900 ÞCa)
0
0.1
0.21000ÞC
900ÞC800ÞC
0
0.5
700 ÞC
800 ÞC
b)
00 2 4 6 8 10
Time - hours
00 1 2 3 4 5 6 7 8 9 10
Time - hours
Calculated (100) silicon dry O2oxidation rates using Deal Grove.
Calculated (100) silicon H2O oxidation rates using Deal Grove.
Example: Problem 6.13 in the text: a) 3 hrs in O2 @ 1100 ˚C = 0.21 µm + b) 2 hrs in H2O @ 900 ˚C = 0.4 µm
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
21
) 2 @ µ+ c) 2 hrs in O2 @ 1200 ˚C = 0.5 µm total oxide thickness.
Oxidation - Chapter 6Volume Mismatch in Si/SiO2 System; Recessed LOCOSRecessed LOCOS
2 2X volume expansion >
H2O@1000°C; Find time to get planar surface?
Example:
2.2X volume expansion -> 45%yox=ySi so yox=ySi/.45 ySi
Total oxide thickness to be grown: yox=ySi/0.45=ySi+0.5µm
ySi=0.41µmyox=0.91µm
yox ySi ySi µ
For H2O
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ22
Time for dry oxidation would be unrealistically long
Oxidation - Chapter 6
Thin Oxide Growth Models• A major problem with the Deal Grove model was recognized when it was
first proposed - it does not correctly model thin O2 growth kinetics.• Experimentally O2 oxides grow much faster for ≈ 20 nm than Deal Grove
predicts.
• MANY models have been suggested in the literature.
1. Reisman et. al. Model
xO = a t + t i( )b or xO = a t + x i⎛
⎝⎜
⎞
⎠⎟
1b
⎛ ⎜ ⎜
⎞ ⎟ ⎟
b
O i( ) o O a⎝
⎜ ⎠ ⎟
⎝ ⎜ ⎜
⎠ ⎟ ⎟
• Power law “fits the data” for all oxide thicknesses.• a and b are experimentally extracted parameters• a and b are experimentally extracted parameters.
• Physically - interface reaction controlled, volume expansion and viscous flow of SiO2 control growth.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
23
Oxidation - Chapter 6
Thin Oxide Growth Models2. Han and Helms Model
dxO
dt= B1
2xO + A1+ B2
2xO + A2 dt 2xO + A1 2xO + A2
• Second parallel reaction added - “fits the data” ” for all oxide thicknesses.• Three parameters (one of the A values is 0).
• Second process may be outdiffusion of OV and reaction at the gas/SiO2Second process may be outdiffusion of OV and reaction at the gas/SiO2interface.
3. Massoud et. al. Modeldx B x⎛ ⎞
dxO
dt= B
2xO + A+ Cexp −
xO
L⎛
⎝ ⎜
⎞
⎠ ⎟
• Second term added to Deal Grove model - higher dx/dt during initial growth.L ≈ 7 nm second term disappears for thicker oxides• L ≈ 7 nm, second term disappears for thicker oxides.
• Easy to implement along with the DG model, ∴ used in process simulators.• Data agrees with the Reisman, Han and Massoud models. (800˚C dry O2
model comparison below.)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
24
p )
Oxidation - Chapter 6
Thin Oxide Growth Models
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
25
Oxidation - Chapter 6
Additional Growth Considerations• Dependence on Pressure
– If Henry’s Law holds, the growth coefficients are dependent on the oxidant just inside the oxide at the gas/SiO2 interface.
– This is dependent upon gas pressure
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
26
Oxidation - Chapter 6
Additional Growth Considerations• Dependence on Crystal Orientation
– Oxidation rates are faster on (111) silicon as compared to (100) silicon.
– Many current structures uses trench etching and growth.– The effect may be due to differences in the number of y
available bonds at the surface.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
27
Oxidation - Chapter 6
2D SiO2 Growth KineticsE h d Si RiEtched Si Ring
Si Substrate
a) • These effects were investigated in detail experimentally by Kao et. al. about 15 years ago.T i l i t l lt b l
Side Views Top Views
b)
• Typical experimental results below.
Polysilicon
c)
SiO2
Si
c)
d)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
28(Kao et.al)
Oxidation - Chapter 6
2D SiO2 Growth KineticsDifference in volume -> problems when expansion is restricted (SiO2 confined)restricted (SiO2 confined)
Experiments by Kao et al.:• Retardation at sharp corners (2X for 500 nm SiO2)• Retardation larger @ low T (no effect @ 1200 °C)Retardation larger @ low T (no effect @ 1200 C)• Interior (concave) corners oxidize slower than
exterior (convex) but both slower than flat Si
Reasons
Poly-Si for contrast
Reasons• Crystal orientation• Diffusion of oxidant through amorphous SiO2 is the
same -> no dependence on directionS ( l diff ) SiO d l• Stress (volume difference): SiO2 under large compressive stress -> affect both oxidant transport and reaction at the Si surface
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ29
Oxidation - Chapter 6
Stress Effects• Several physical mechanisms seem to be
1.0
1.1
1200 ÞC
• Several physical mechanisms seem to be important:
• Crystal orientation • 2D oxidant diffusion
S
0 7
0.8
0.9
hick
ness
1100 ÞC
1000 ÞC
• Stress due to volume expansion• To model the stress effects, Kao et. al.
suggested modifying the Deal Grove parameters.
.
0.5
0.6
0.7
mal
ized
Oxi
de T
h
900 ÞC
800 ÞC
1100 ÞC
1000 ÞC900 ÞC
parameters.
⎟⎠⎞
⎜⎝⎛−⎟
⎠⎞
⎜⎝⎛−=
kTV
kTVkstressk TtRn
SSσσ expexp)(
( )( )⎞⎛ VP
0.2
0.3
0.4
Nor
m
Convex Radii
Concave Radii
900 ÞC ( )( )⎟⎠⎞
⎜⎝⎛−=
kTVPDstressD Dexp)(
( )( )⎟⎠⎞
⎜⎝⎛−=
VPCstressC Sexp)( **
0 1 2 3 4 5 6 7 8 1/r µm-1
0.11 µm 0.2 µm 0.125 µm
⎟⎠
⎜⎝ kT
p)(
where and are the normal and tangential stresses at the interface.
σ n σ t
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
30
1/r µmVR, VT and VS are reaction volumes andare fitting parameters.
(Kao et.al)
Oxidation - Chapter 6
Simulating StressI dditi th fl ti f th SiO d t b d ib d b t• In addition, the flow properties of the SiO2 need to be described by a stress dependent viscosity
η(stress ) = η(T) σ SVC / 2kT
sinh σ SVC / 2kT( )where is the shear stress in the oxide and VC is again a fitting parameter. σ S
Parameter Value SiOSi3N4
-0.2
-0.4
Parameter ValueVR 0.0125 nm3 VD 0.0065 nm3
VS, VT 0 VC 0.3 nm3 @ 850˚C
Silicon
SiO 2
0
0.2
0 4Mic
rons
VC 0.3 nm @ 850 C0.72 nm3 @ 1050˚C
η(T) - SiO2 3.13 x 1010 exp(2.19 eV/kT) poise η(T) - Si3N4 4.77 x 1010 exp(1.12 eV/kT) poise
0.4
0.6
0.8
M
• These models have been implemented in modern process simulators and allow them to predict shapes and stress levels for VLSI structures (above
Microns0 0.4 0.8-0.4-0.8
Microns0 0.4 0.8-0.4-0.8
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
31
right).• ATHENA simulation: Left - no stress dependent parameters, Right –
including stress dependence.
Oxidation - Chapter 6
Point Defect Based Models• The oxidation models we have considered to this point are macroscopic
models (diffusion coefficients, chemical reactions etc.).
Th i l t i ti i t
*O2
H O
Diffusion
V• There is also an atomistic picture
of oxidation that has emerged in recent years.
• Most of these ideas are driven by
*H2O
II
ythe volume expansion occurring during oxidation and the need for “free volume”.
Oxide Silicon
• In Chapter 3 we described internal oxidation in the following way when discussing SiO2 precipitates as gettering sites (p.141-2):
( ) stressISiOVOSi ISi ++↔+++ γβγ 22221 2
• Surface oxidation can be thought of in the same way.V i d t th f I t titi l t d d i t th
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
32
• Vacancies drawn to the surface, Interstitials created and move into the bulk silicon (causing other effects?! OED and ORD)
Oxidation - Chapter 6
Oxidation Enhanced/Retarded Diffusion• The connection between oxidation and other processes can then be
modeled as shown below. O2
G R
SurfaceRecombination
I
Inert Diffusion
OED
ons
0
0.5
Si 3N4SiO 2
Buried Dopant Marker Layer
Bulk Recombination *
OEDInert
Diffusion
I
Mic
ro
1.0
1.5
Microns0 1 2-1-2
Example - ATHENA simulation of OED.
• Oxidation injects interstitials to create “free volume” for the oxidation process. Oxidation can also consume vacancies for the same reason.
• These processes increase I concentrations and decrease V concentrations in nearby silicon regions.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
33
concentrations in nearby silicon regions.• Any process (diffusion etc) which occurs via I and V will be affected.
Oxidation - Chapter 6
Substrate Doping Effects
NDopant P -> oxide growth by B/A not by B; especially @ low T about
5x fasterdue to dopant 2x faster
Concentration Enhanced Oxidation (CEO)
not by B; especially @ low T about 3-4X due to concentrations
Properties of oxide do not change for P but change for BP but change for B
Oxidation needs V for volume expansion so for dopant concentrations charged V
Low T
High Tconcentrations, charged V (V-, V= - N+-type; V+ - P+ -type) ->
B/A
Dopant segregation N+ > to SiCEO stronger for N+ than P+ (B/A grows, B does not)
Dopant segregation N+ -> to SiP+ -> SiO2
Interface changes during oxidation > growth rate changes
CEO for Boron changes B but not B/A due to incorporation in the oxide
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ34
-> growth rate changes
Oxidation - Chapter 6
Complete Process Simulation of Oxidation• Many of these models (and others in Chapter 6), have been implemented in
programs like SUPREM• Simulation of an advanced
.
0
0 4cron
s
isolation structure (the SWAMI process originally developed by Hewlett-Packard), using SSUPREM IV0.4
0.8
Mic SSUPREM IV.
• The structure prior to oxidation is on the top left. A 450 min H2O oxidation at 1000 ˚C is then
0
ns
performed which results in the structure on the top right. An experimental structure fabricated with a similar
0.4
0.8
Mic
ron fabricated with a similar
process flow is shown on the bottom right.
• The stress levels in the growing
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
35
Microns1-1 0 SiO2 are shown at the end of
the oxidation on the bottom left.
Oxidation - Chapter 6
Recessed LOCOS – ATHENA Simulation
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ36
Oxidation - Chapter 6
Summary of Key Ideas• Thermal oxidation has been a key element of silicon technology since its
inception.
• Thermally, chemically, mechanically and electrically stable SiO2 layers on silicon distinguish silicon from other possible semiconductors.
• The basic growth kinetics of SiO2 on silicon are controlled by oxidant diffusion and Si/SiO2 interface chemical reaction.
• This simple Deal-Grove model has been extended to include 2D effects highThis simple Deal Grove model has been extended to include 2D effects, high dopant concentrations, mixed ambients and thin oxides.
• Oxidation can also have long range effects on dopant diffusion (OED or ORD) hi h d l d th h i t d f t i t tiORD) which are modeled through point defect interactions.
• Process simulators today include all these physical effects (and more) and are quite powerful in predicting oxidation geometry and properties.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
37
are quite powerful in predicting oxidation geometry and properties.
top related