synopsys class 1 - המחלקה להנדסת חשמל ומחשביםdigivlsi/slides/synopsys_class_1_4_1.pdf2->1 MUX cond out1_d • According to evaluation done in Design2 the timing
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Logic Synthesis
Page 1
Introduction to Digital VLSI
Logic Synthesis
Logic Synthesis
Page 2
Introduction to Digital VLSI
Course Outline
• Design Compiler Overview
• Some Words about Physical Compiler
• Coding Styles
• Partitioning
• Design Compiler Commands
• Additional Commands for Physical Compiler
• Timing Analysis
• Interaction with Layout Tools
• Speed/Area Optimization
• Logic Structure in High Level Code
• Physical Compiler Overview
Logic Synthesis
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Introduction to Digital VLSI
Constraints
(timing, area ...)
Design Compiler Overview
DesignCompiler
or mapped Gate Level
Cell Libraries
Mapped Netlist
HDL Code (RTL)
(xxx.lib -> xxx.db)
(timing and function)
Logic Synthesis
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Introduction to Digital VLSI
Constraintsy)
Floorplan
(timing & physical)
Physical Compiler Overview
PhysicalCompiler
or mapped Gate Level
Cell Libraries
Placed Netlist
HDL Code (RTL) Physical Libraries(cells and technolog
(xxx.lib -> xxx.db) (xxx.plib -> xxx.pdb)(timing and function)
Logic Synthesis
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Introduction to Digital VLSI
ly by varying
• synthesis = mapping + optimization
Speed
Area
Large
Small
Fast Slow
• Design Compiler is constraint-driven
• Designer explores area vs. speed trade-offs simpconstraints
Logic Synthesis
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Introduction to Digital VLSI
constraints to meet
edges”
Few Synopsys rules of Thumb
• “There is no ‘golden’ script for synthesis”
• “The random setting of optimization switches andyour speed goals is NOT a credible methodology”
• “Physics dictates what will fit between two clock
Logic Synthesis
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Introduction to Digital VLSI
ntifyblem
ode RTL
Analyze and ElaborateRTL codeApply Constraints
Synthesize
ConstraintsMet?
End
IdePro
Re-c
Floorplan
CreateCustomWireload
General Synopsys Synthesis Flow
No
Yes
Synthesis tricks
Logic Synthesis
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Introduction to Digital VLSI
ntifyblem
ode RTL
Flow (mpc)
Analyze and ElaborateRTL code
Apply Constraints
compile_physical
ConstraintsMet?
End
IdePro
Re-c
“Floorplan”
General Synopsys Physical Synthesis
NoYes
including simefloorplan requirements
Create Floorplan
Synthesis tricksor physopt
Logic Synthesis
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Introduction to Digital VLSI
ntifyblem
ode RTL
flooplan based)
Analyze and ElaborateRTL code
Apply Constraints
compile_physical
ConstraintsMet?
End
IdePro
Re-c
Update floorplan
General Synopsys Physical Synthesis Flow (
No
Yes
including simefloorplan requirements
Synthesis tricksor physopt
(can be basedon mpc run)
Resize up/down, relocate pins etc.
mpc runresults
Logic Synthesis
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Introduction to Digital VLSI
vel Compile
cks
ons)
Integrate Blocks
Design
End
Top-Le
Integration with Structures and other Blo
RuleProblems?
• Integration may cause transition problems (violati
• Top-level compile to fix any problem
• Best way is to model the structures
Yes
No
Logic Synthesis
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Introduction to Digital VLSI
Coding Style
• Inferring Sequential Devices
• Three-State Inference
• Combinational Logic
• case vs. if synthesis
• Finite State Machines TBD? (Exists)?
Logic Synthesis
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Introduction to Digital VLSI
es:
nce of: Bus, AsyncToggle.
eset:
ntation.
uxedDFF JKFF MS
latch
+ + +
R SS ST
N N
Inferring Sequential Devices
• Synopsys can infer a broad range of FF’s and latch
• An inference report indicates type, width, and preseReset, Async Set, Sync Reset, Sync Set and Sync
Example: Inference Report for D Flipflop with Async R
• For more details refer to Synopsys on-line docume
LatchLatch
w/Async
Latchw/DualAsync
Latchw/
SyncDFF
DFFw/
Async
DFFw/DualAsync
DFFw/
Sync
M
+ + + + + + + +
Register Name Type Width Bus AR AS S
Q1_reg Flip-Flop 1 - Y N N
Logic Synthesis
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Introduction to Digital VLSI
D-Flip-Flopsmodule dffs (clk, in1, in2, cond, rst_b, out1, out2);input clk, in1, in2, cond, rst_b;output out1, out2;reg out1, out2;
always @(posedge clk) begin out1 <= in1;end
always @(posedge clk or negedge rst_b) begin if (!rst_b) out2 <= 1’b0; else out2 <= in2;end
endmodule
Always use non-blocking assignments for flip-flops.
module dffs ( clk, in1, in2, cond, rst_b, out1, out2);input clk, in1, in2, cond, rst_b;output out1, out2; dffrpc out2_reg ( .C(clk), .D(in2), .RB(rst_b), .Q(out2) ); dffpc out1_reg ( .C(clk), .D(in1), .Q(out1) );endmodule
Logic Synthesis
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Introduction to Digital VLSI
Transparent Latches
module latches ( clk, in1, in2, rst_b, out1, out2);input clk, in1, in2, rst_b;output out1, out2;reg out1, out2;
always @(in1 or clk) begin if (clk) out1 <= in1;end
always @(in2 or rst_b or clk) begin if (!rst_b) out2 <= 1’b0; else if (clk) out2 <= in2;end
endmodule
Use non-blocking assignments for latches as well
Logic Synthesis
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Introduction to Digital VLSI
nthesis
==============
==============
==============
==============
==============
==============
Transparent latches (cont.) - result of sy
Inferred memory devices in processin routine latches line 7 in file kuku
=================================================================| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=================================================================| out1_reg | Latch | 1 | - | - | N | N | - | - | - |=================================================================
Inferred memory devices in processin routine latches line 12 in file kuku
=================================================================| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=================================================================| out2_reg | Latch | 1 | - | - | Y | N | - | - | - |=================================================================
Logic Synthesis
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Introduction to Digital VLSI
nthesis
rived from the HDL
Transparent latches (cont.) - result of sy
module latches ( clk, in1, in2, rst_b, out1, out2 );input clk, in1, in2, rst_b;output out1, out2; itlrpc out2_reg ( .C(clk), .D(in2), .RB(rst_b), .Q(out2) ); itlpc out1_reg ( .C(clk), .D(in1), .Q(out1) );endmodule
• Note that the instance names of the latches are dereg names.
Logic Synthesis
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Introduction to Digital VLSI
clock should havee is a possibility for
g gated clocks.ibraries.
em into the clock
lem exists fors.
s enable manualool inference. UserL and include a
y should be usedct the sharedsaving).
Gated Clocks
• DC doesn’t understand that condition of the gatedsetup time with regard to the clock. As a result therfalse select.
• There is a danger of hold time violation when usinChecking hold time violations requires best case l
• Refrain from using gated clocks unless you put thgenerator block.
• From below you will see that the gated clocks probmultiple-clock flip-flops and for transparent latche
Exception
• New power compiler and clock tree synthesis flowinstatiation of gatded clcoks as well as automatic tgated clocks in RTL source should be INTENTIONAlatch and and AND function (glithless design). TheONLY where Power Compiler has no ability to deteclocking condition (e.g: stop/idle for global power
Logic Synthesis
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Introduction to Digital VLSI
*/
module gated_clock (clk1, clk2, in1, in2, cond, rst_b, out1, out2, out3);input clk1, clk2, in1, in2, cond, rst_b;output out1, out2, out3;reg out1, out2, out3;wire clk;
/* conditional flip-flop - no problem */always @(posedge clk1 or negedge rst_b) begin if (!rst_b) out1 <= 1’b0; else if (cond) out1 <= in1;end
/* conditional latch - refrain from using it */always @(clk1 or rst_b or in1 or cond) begin if (!rst_b) out2 <= 1’b0; else if (cond & clk1) out2 <= in1;end
/* multiple clocks flip-flop - refrain from using itassign clk = clk1 || clk2;always @(posedge clk or negedge rst_b) begin if (!rst_b) out3 <= 1’b0; else out3 <= in2;endendmodule
Logic Synthesis
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Introduction to Digital VLSI
s
out3_reg.
Gated Clocks (cont.) - result of synthesi
module gated_clock ( clk1, clk2, in1, in2, cond, rst_b, out1, out2, out3 );input clk1, clk2, in1, in2, cond, rst_b;output out1, out2, out3; wire clk, n56, n164;
mux21b z52 ( .A(out1), .B(in2), .S0(cond), .OUT(n164) ); dffrpb out1_reg ( .C(clk1), .D(n164), .RB(rst_b), .Q(out1) );
iand2b z51 ( .INPUT1(clk1), .INPUT2(cond), .OUTPUT1(n56) ); itlrpc out2_reg ( .C(n56), .D(in1), .RB(rst_b), .Q(out2) );
ior2b z50 ( .INPUT1(clk1), .INPUT2(clk2), .OUTPUT1(clk) ); dffrpc out3_reg ( .C(clk), .D(in2), .RB(rst_b), .Q(out3) );
endmodule
• Note that gated clocks exist only on out2_reg and
Logic Synthesis
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Introduction to Digital VLSI
em
llowing way:
out1
out1_d
Gated Clocks (cont.) - how to prevent th
• Don’t use multiple clocked flip-flops
• Conditional latches could be implemented in the fo
CD Q
TL
in1 out1
clk && cond
CD Q
TL
in1
CQ D
TL
clk_b
clk
2->1MUX
cond
• According to evaluation done inDesign2 the timing and area of thealternative implementation is onlyslightly worse than of the originalone.
• Explicit (“manual”) clock gating isalso possible if multiple latchesshared one condition (powersaving issue)
Logic Synthesis
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Introduction to Digital VLSI
cks
clk_gated
// in the “clock generator”output clk_gated;reg cond_latched;always @(clk or cond) if (~clk) cond_latched <= cond;assign clk_gated = (cond_latched | scan_enable) & clk;...// In the moduleinput clk_gated;reg out;
always @(posedge clk_gated or negedge rst_b) begin if (!rst_b) out <= 1’b0; else out <= in;end...
Gated Clocks (cont.) - explicit gated clo
c_bd q
TL
clk
cond
scan_enable
Logic Synthesis
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Introduction to Digital VLSI
assigned to a
lock.
Three-State Inference
• A three-state driver is inferred when the value z is
module ff_3state (data1, data2, clk, three_state, out1, out2);input data1, data2, clk, three_state;output out1;output out2;
reg out1;reg out2_data;
always @ (posedge clk) begin if (three_state) out1 = 1’bz; else out1 = data1; end
always @ (posedge clk) out2_data = data2;
assign out2 = three_state ? 1’bz : out2_data;endmodule
• Do not use tristate buffers internal to a block.
• DO not define bidirectinal ports for a synthesized b
Logic Synthesis
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Introduction to Digital VLSI
===========
===========
===========
module ff_3state ( data1, data2, clk, three_state, out1, out2 );
input data1, data2, clk, three_state;
output out1, out2;
wire n98, n99, n100, n101;
trinvc out2_tri ( .INPUT1(n98), .INPUT2(n99), .OUTPUT1(out2) );
iinve U21 ( .INPUT1(three_state), .OUTPUT1(n99) );
trinvc out1_tri ( .INPUT1(n100), .INPUT2(n101), .OUTPUT1(out1) );
dffpb out1_reg ( .C(clk), .D(data1), .QB(n100) );
dffpb out1_tri_enable_reg ( .C(clk), .D(three_state), .QB(n101) );
dffpb out2_data_reg ( .C(clk), .D(data2), .QB(n98) );
endmodule
Inferred THREE-STATE control devices in processin routine ff_3state line 11
in file kuku.=================================================================| Three-state Device Name | Type | MB |=================================================================| out1_tri | Three-state Buffer | N || out1_tri_enable_reg | Flip-flop (width 1) | N |=================================================================
Logic Synthesis
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Introduction to Digital VLSI
ays loop
ent parameters
Combinational Logic
Use combinational logic for:
• Intermediate variables for clarity
• Complex logic that becomes unwieldy in the FF alw
• Functions that are used more than once with differ
• Resource Sharing
Logic Synthesis
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Introduction to Digital VLSI
ot a real register
r C or D)
| (B != ‘GO))yy = D;
yy = D & !A;
e clk) (count < 17))y <= yy;
wire yy = (A & C | (B != ‘GO)) ? D : (D & !A);wire start_count = start & (count < 17);
reg y;
always @(posedge clk)if (start_count)
y <= yy;
reg y;
always @(posedge clk)if (start & (count < 17)) begin
if (A & C | (B != ‘GO))y <= D;
elsey <= D & !A;
end
reg yy; // n
always @(A or B obegin
if (A & C
else
end
reg y;
always @(posedgif (start &
Logic Synthesis
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Introduction to Digital VLSI
lly generates the logic to
ppropriate
lk)
= a + b;
DesignWare Resources
HDL Compiler understands some operators and automaticaimplement them:
• +/- will use inc, dec, incdec, add, sub, addsub as a
• > >= < <= will generate a comparator
reg [7:0] a, b;reg [7:0] y;
always @(posedge cif (a > b)
y <
comparator
adder
Logic Synthesis
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Introduction to Digital VLSI
OUTC
d might not be a 4->1 MUX
Case Synthesis
• case statements infer "tall and skinny" muxes.
always @(SEL or A or B or C or D)
begin
case (SEL)
2’b00 : OUTC = A;
2’b01 : OUTC = B;
2’b10 : OUTC = C;
default : OUTC = D;
endcase
end
A
B
C
D
SEL2
00
01
10
11
Note: Actual gates synthesize
Logic Synthesis
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Introduction to Digital VLSI
Case Synthesis (cont.)
Statistics for case statements in always block at line 8 in file kuku===============================================| Line | full/ parallel |===============================================| 11 | auto/auto |===============================================Current design is now{"try1"}
Logic Synthesis
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Introduction to Digital VLSI
ase statement HDL
ches are parallel, itder.
Case Synthesis (cont.) - WARNINGS!!!
• If you do not specify all possible branches of the cCompiler will synthesize a latch.
• If HDL Compiler can’t statically determine that bransynthesizes hardware that includes a priority enco
Logic Synthesis
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Introduction to Digital VLSI
anches
fy allpsysssion if
ot Full
Case Synthesis - “full case”
• A case statement is called full case if all possible brare specified.
• Synopsys will synthesize a latch if you don’t specipossible branches of a case statement. Use // synofull_case directive immediately after the case expre
always @(sel or a or b or c)begin case (sel) 2'b00 : outc <= a; 2'b01 : outc <= b; 2'b10 : outc <= c; endcaseend
A case statement that isParallel but n
And what is wrong here ?
Logic Synthesis
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Introduction to Digital VLSI
===========
===========
===========
Case Synthesis - “full case” (cont.) Synopsys statistics WITHOUT // synopsys full_case directive
Statistics for case statements in always block at line 8 in file kuku
===============================================| Line | full/ parallel |===============================================| 11 | no/auto |===============================================
Inferred memory devices in processin routine try2 line 8 in file kuku
====================================================================| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |====================================================================| outc_reg | Latch | 1 | - | - | N | N | - | - | - |====================================================================
Current design is now try2
Logic Synthesis
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Introduction to Digital VLSI
W all casesa
S=| =| =C
a recomended style !tion of the case.
Case Synthesis - “full case” (cont.)always @(sel or a or b or c)begin case (sel) // synopsys full_case 2'b00 : outc = a; 2'b01 : outc = b; 2'b10 : outc = c; endcaseend
Synopsys statistics WITH // synopsys full_case directive
arning: You are using the full_case directive with a case statement in which notre covered. (HDL-370)
tatistics for case statements in always block at line 8 in file kuku============================================== Line | full/ parallel |============================================== 11 | user/auto |==============================================urrent design is now try2
Note : This is not
Blocking assignment
Prefer full descrip
Logic Synthesis
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Introduction to Digital VLSI
piler can
// synopsys
llel
Case Synthesis - “parallel case”
• A case statement is called parallel case if HDL Comdetermine that no cases overlap.
• Synopsys will synthesize a priority encoder unlessparallel_case directive is used.
always @(w or x)begin case (1'b1) w : b = 0; x : b = 1; endcaseend
A case statement that is NotFull or Para
Logic Synthesis
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Introduction to Digital VLSI
===========
===========
===========
Case Synthesis - “parallel case” (cont.) Synopsys statistics WITHOUT // synopsys parallel_case full_case directive
Statistics for case statements in always block at line 7 in file kuku===============================================| Line | full/ parallel |===============================================| 10 | no/no |===============================================
Inferred memory devices in processin routine try3 line 7 in file kuku
====================================================================| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |====================================================================| b_reg | Latch | 1 | - | - | N | N | - | - | - |====================================================================
Logic Synthesis
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Introduction to Digital VLSI
Case Synthesis - “parallel case” (cont.) Synopsys statistics WITH // synopsys parallel_case full_case directive
Warning: You are using the full_case directive with a case statement in which not allcases are covered. (HDL-370)Warning: You are using the parallel_case directive with a case statement in which somecase-items may overlap. (HDL-371)
Statistics for case statements in always block at line 7 in file kuku
===============================================| Line | full/ parallel |===============================================| 10 | user/user |===============================================Current design is now try3
Logic Synthesis
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Introduction to Digital VLSI
cading" MUXs.
0
1
0
1OUTC
ght not match those shown above.
if-then-else Synthesis
• if-then-else statements infer priority-encoded "cas
always @(SEL or A or B or C or D)
begin
if (SEL == 2’b00)
OUTC = A;
else if (SEL == 2’b01)
OUTC = B;
else if (SEL == 2’b10)
OUTC = C;
else
OUTC = D;
end
D
C
0
1
SEL == 2’b10SEL
B
SEL == 2’b01
SEL == 2’b00
A
Note: Actual gates synthesized mi
Logic Synthesis
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Introduction to Digital VLSI
without priority
always @(. . .)
begin
case (. .)
A: . . . ;
B: . . . ;
C: . . . ;
endcase
end
case vs if statements
• Note that only case statement may be implemented
always @(. . .)
begin
if (. .)
. . . ;
else if (. .)
. . . ;
else if (. .)
. . . ;
else
. . . ;
end
toppriority always @(. . .)
begin
if (. .)
. . . ;
if (. .)
. . . ;
if (. .)
. . . ;
end
toppriority
toppriority
Logic Synthesis
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Introduction to Digital VLSI
igh-level) simula-
A
B
C
Gate-LevelSimulation
Safe Coding Rules
Sensitivity Lists
Use complete sensitivity lists for combinational always statements. Otherwise, pre-synthesis (htion might not match post-synthesis (gate-level) simulation results.
Elaboration will detect incomplete sensitivity lists and generate a warning.
Aalways @(A)begin C = A || B;end
BC
A
B
C
High-LevelSimulation
SynthesizedNetlist
Logic Synthesis
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Introduction to Digital VLSI
f statement.
ach case or if
s to be synthesized.
gnments
on-blocking
Safe Coding Rules (cont.)
case and if Statements (part 1)
• Completely specify all clauses for every case and i
• Completely specify all outputs for every clause of estatement.
• Failure to do so will cause extra latches or flip-flop
• In combinational always blocks - use blocking assi
always @(D)begin case (D) 2’b00: Z <= 1’b1; 2’b01: Z <= 1’b0; 2’b10: Z <= 1’b1; S <= 1’b1; endcaseend
MissingClause
S Output
What’s wrong with this code?
n
Logic Synthesis
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Introduction to Digital VLSI
ult (rather
Safe Coding Rules (cont.)
case and if Statements (part 2)
• Whenever possible, use a case statement with defathan an if statement).
always @(SEL or INNER)
case (SEL) 2’b00: Z = 2’b00; 2’b01: case (INNER) 2’b00: Z = 2’b11; 2’b01: Z = 2’b01; default: Z = 2’b00; endcase 2’b10: Z = 2’b11; default: Z = 2’b10;endcase
case within a case
Logic Synthesis
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Introduction to Digital VLSI
nthesize correct
MAIN;
DDR_CNTL;
DDR_INT;
ADDR_BUS
Implication Example
• Good style takes advantage of if-else priority to sy
Bad Style
case (STATE) IDLE: if (LATE == 1’b1) ADDR_BUS = ADDR_MAIN; else ADDR_BUS = ADDR_CNTL; INTERRUPT: if (LATE == 1’b1) ADDR_BUS = ADDR_MAIN; else ADDR_BUS = ADDR_INT;endcase
if (LATE == 1’b1)ADDR_BUS = ADDR_else case (STATE) IDLE: ADDR_BUS = A INTERRUPT: ADDR_BUS = A endcase
Good Style
COMBO
LATE
ADDR_MAIN
ADDR_BUSCOMBO
LATE
ADDR_MAIN
Logic Synthesis
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Introduction to Digital VLSI
ign?
/or the Design
Partitioning
What is Partitioning? vs. SOG !
• Partitioning is dividing a design into smaller parts.
• How do you decide on the partitioning of your des• By functionality• By designer’s skill• For optimal synthesis result• All of the above
• Partitioning is done within the HDL description and
Logic Synthesis
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Introduction to Digital VLSI
INST
OK
EC
OK
ks.
do not create
BLK
Partitioning Within the HDL Description
module ADR_BLK (. . .DEC U1 (ADR, CLK, INST);OK U2 (ADR, CLK, AS, OK);endmodule;
CLK
AS
ADR D
• Module statements create hierarchical design bloc
• Continuous assignments and always@ statements
ADR_
Logic Synthesis
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Introduction to Digital VLSI
en entered into
Partitioning Within Design Compiler
• A designer can re-partition a design after it has beDesign Compiler.
group ungroup
Logic Synthesis
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Introduction to Digital VLSI
cified cells.
l name” for
U10
DECODE
DEC1
U5
The group command
U1
• Creates a new hierarchical block containing the spe
• The designer provides a “design name” and a “celthe new block.
U2
U3
U4U5
U6
U7
U8
U9U10
group -logic -design DECODE-cell DEC1
Logic Synthesis
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Introduction to Digital VLSI
es. Very
he extra
DEC/U2
DEC/U3
DEC/U4
DEC/U5
U6
U7
U8
U9U10
DEC/U1
The ungroup command
• Removes levels of hierarchy of the named instancimportant command.
• -simple_names option should be used to remove t
ungroup {DEC1}U6
U7
U8
U9U10
DECODE
DEC1
Logic Synthesis
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Introduction to Digital VLSI
Why Partition for Synthesis?
• Required less resources. (Tool, Designers)
• Less timing constraints to deal with.
• Further placement optimization is allowed.
Why SOG (Sea Of Gates) for Synthesis?
• Produce the best synthesis results.
• Speed up optimization run times.
• Simplify the synthesis process.
Logic Synthesis
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Introduction to Digital VLSI
ble
Partitioning Rules for Synthesis
• No hierarchy in combinational paths.
• Register all outputs.
• No glue logic between blocks.
• Separate designs with different goals.
• Maintain a reasonable block size.
• Separate logic, pads, clocks and non-synthesizastructures.
Logic Synthesis
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Introduction to Digital VLSI
etween three
d
ries prevent
EG
No Hierarchy in Combinational Paths
Bad Example
REG
COMBLOGIC A
The path between two REG’s is divided b
ifferent blocks.
• Optimization is limited because hierarchical boundasharing of common terms.
COMBLOGIC B
COMBLOGIC C R
Logic Synthesis
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Introduction to Digital VLSI
ont.)
to one block;
t e same level
o
No Hierarchy in Combinational Paths (c
Better Example
REG
COMBLOGIC
Related combinational logic is grouped in
hus. all related combinational logic is at th
f hierarchy.
REGA & B & C
Logic Synthesis
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Introduction to Digital VLSI
ont.)
nto the same
b for the
c
No Hierarchy in Combinational Paths (c
Best Example
REG
COMBLOGIC
Related combinational logic is grouped i
lock that contains the destination register
ombinational logic path.
REGA & B & C
Logic Synthesis
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Introduction to Digital VLSI
REGC
l block
d d lower-level
b
No Glue Logic Between Blocks
Bad Example
REG
CLK
COMBOLOGIC A
A
CLK
COMBOLOGIC C
A C
TOP
A NAND gate was added to the TOP leve
escription, to “bridge” the two instantiate
locks
Logic Synthesis
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Introduction to Digital VLSI
REGC
ational logic
d statements.
No Glue Logic Between Blocks (cont.)
Good Example
REG
CLK
COMBOLOGIC A
A
CLK
A C
TOP
Merge glue logic into the related combin
escription of the lower-level architectural
• The merged glue logic can now be optimized away.
GLUE +COMBOLOGIC C
Logic Synthesis
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Introduction to Digital VLSI
s not.
t isolate parts of a.
Separate Designs with Different Goals
Bad Example
REG
CLK
CRITICALPATHS
A
REG
CLK
C
TOP
REG A is in the critical path, but REG C i
• Optimization is limited because the designer cannoblock and optimize them solely for area or for speed
NOCRITICALLOGIC
Logic Synthesis
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Introduction to Digital VLSI
cont.)
sign into
Separate Designs with Different Goals (
Good Example
REG
CLK
CRITICALPATHS
A
REG
CLK
C
Use different modules to partition the de
NOCRITICALLOGIC
Logic Synthesis
Page 56
Introduction to Digital VLSI
ing optimization
g; quick iterations
s
Maintain a Reasonable Block Size
Bad Example
10 gates
• If blocks are too small, the designer may be restrictwith artificial boundaries.
• If blocks are too big, compile run times are very lon
40,000 gates
10,000 gates
30,000 gate
top related