Sprinkler Buddy Presentation #6: “Optimized Schematics and Component Layout” 2/28/2007 Team M3 Devesh Nema Kalyan Kommineni Kartik Murthy Panchalam Ramanujan.

Sprinkler Buddy

Presentation #6:

“Optimized Schematics

and Component Layout”

2/28/2007

Team M3Devesh Nema

Kalyan KommineniKartik Murthy

Panchalam RamanujanSasidhar Uppuluri

Design Manager: Bowei Gai

“Low Cost Irrigation Management For Everyone ! ”

Current Status Determine Project Develop Project Specifications Plan Architectural Design

Determination of all components in design Detailed logical flowchart

Design a Floor Plan Create Structural Verilog Make Transistor Level Schematic Layout (big comp. finished…~ 40 % of whole done) Testing (Extraction, LVS, and Analog Sim.) (ongoing…)

Last Week’s Floor Plan

Current Floor Plan

Individual Modules:

Block Metal Layers That Have Been Used

40:20 Muxes M1 & M2

60:20 Muxes M1 & M2

Counters M1 & M2

KC ROM M1 & M2 & M3 & M4

P ROM M1 & M2 & M3 & M4

Metric Storage SRAMS M1 & M2 & M3 & M4

Constant Storage ROM M1 & M2 & M3 & M4

Floating Point Adders M1 & M2 & M3

Floating Point Multipliers M1 & M2 & M3 & M4

10 Bit Registers M1 & M2 & M3

Transistor Count …

Block (# used) Old TC New TC

40:20 Muxes (6) ~480 362

60:20 Muxes (2) ~720 644

Counter (2) ~250 220

KC ROM (1) ~778 1256

P ROM (1) ~82 122

Metric Storage SRAMS (2)

~2522 2430

Constant Storage ROM (1)

~202 428

Floating Point Adder (4)

~3000 3210

Floating Point Multiplier (2)

~2800 1398

10 Bit Registers (9)

~140 210

Datapath Logic / Misc.

~2000 2305

Total =

30,397

New Design SizeBlock (# used) Size Estimate (um)

40:20 Muxes (4) 20 x 80

60:20 Muxes (2) 20 x 120

Counter (2) 12 x 17

KC ROM (4 parts) 181 x 8

P ROM (1) 70 x 8

Metric Storage SRAMS (2)

181 x 60

Constant Storage ROM (1)

181 x 8

Floating Point Adder (4)

96x151

Floating Point Multiplier (2)

130 x 60

10 Bit Registers (8) 50 x 10

• 464um x 416 um• ~ 1 : 1.11 aspect ratio• .193 mm^2 area• .16 Transistor Density

FSM Logic in Schematic

Schematics: Read to SRAM

Schematics: Write to SRAM

Layout : SRAM

Layout : Adders and Multipliers

14 T Full Adder

Multiplier

Layout : Flip Flops

Folding of Transistors

Design Challenges and Implementation

DecisionsFor The Past Week

Design Challenge

Translation to HW

Low Power Design

• Finalized 14 T Full Adder Design• Optimally Sized All Gates• Minimal Usage of OR/NOR Gates

Problems/QuestionsWe need to generate an XOR which

matches the width of a Full Adder Need to finalize the layout of control

logic around other blocks

For Next WeekLots and Lots of Layout

Wiring inside main components (FP units) FSMs Global Routing