Transcript
8/22/2019 Signal Integrity Basics
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-Design Trends and Challenges
Vladimir Sto anovi
Integrated Systems Group
Massachusetts Institute of Technology
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Backbone router lots of high-speed links
source: Juniper Networks
source: Alcatel, Tyco
State-of-the art up to 1 Tb/s throughput
Lots of linecards power constrained system
Integrated Systems Group 2
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Inside the router
Line Cards:
8 to 16 per System
Switch Cards:
2 to 4 per System
Passive
Backplane
SerDes
SerDes Crossbar
CrossbarMEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MAC
MAC Fabric
IF
Fabric
IF
NPU
NPUOptics
Optics
SerDes
SerDes
SerDes
SerDes
4x3.125 Gb/s
XAUI Serial LinksOC-192 3.125-12.5Gb/s
(chip-to-chip).
Laser driver link
Regardless of where the links are, there is a constant desire to signal
Integrated Systems Group 3
faster and with less power
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Scaling the throughput to 100 Tb/s
Electrical I/O Challenges
100 Tb/s I/O throughput
With 10Gb/s er link
10000 transceivers
20000 high-speed I/O pairs2 .
Power 4kW
40 mW/Gb/s energy cost per bit
Integrated Systems Group 4
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Scaling the throughput to 100 Tb/s
Density issues
Connectors 50 diff pairs/inch
Trace routing
50mils pitch
250 wide 4-signal layer line-card
Backplane less critical
Package
Package/Chip ball pitch (1mm / 200um)
4000 mm2 / 160mm2
Integrated Systems Group 5
source: Teradyne, Rambus
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Design challenge
Fit 100 Tb/s on a 100 W crossbar chip
Reasonable s stem/rack size
Need
Power
Reduce energy/bit to 1mW/Gb/s
Density Increase data rate per link by 10-15x
Integrated Systems Group 6
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What makes it challenging
High speed
> 2 GHz signals
Integrated Systems Group 7
Now, the bandwidth limit is in wires
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High-speed link efficiency energy cost per bit
1000000
5.5
12
14
16
18
bit[mW/Gb/s]
PAM4
PAM2
How efficient are high-speed links?
10000
100000
stperbit
b/s)
12.2
8
11
1.5
5.9
0.45
0
2
4
6
8
Energycostper
10
100
Energyc
mW/( 0.3
TxTap RxTap RxSamp PLL CDR
100
120
140
[mW
/Gb/s]
1
56Kb/s V.92
modem
12x12Mb/s
ADSL
modem
Gigabit
Ethernet
10Gb/s
High-speed
link
20
40
60
80PAM2 Tx5 Rx20
PAM2 Tx5 Rx1+20
PAM2 Tx50 Rx80
PAM4 Tx5 Rx20
PAM4 Tx50 Rx80
ergycostperbi
2-3 orders more energy-efficient Than traditional wireline systems
0 2 4 6 8 10 12 14 16 18 200
Data rate [Gb/s]
E
Integrated Systems Group 8
ar ng o pay e pr ce or an - m e c anne s
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Outline
Look at all aspects of system design
High-speed link environment Improving the channel
What can chi s do?
Integrated Systems Group 9
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Backplane environment
PackagePackage
Line card trace
On-chip parasit ic(termination resistance anddevice loading capacitance)
PackageviaLine card trace
On-chip parasit ic(termination resistance anddevice loading capacitance)
Packagevia
Back plane connector Line card
via
Back plane trace Back plane connector Line card
via
Back plane trace
Backplane viaBackplane via
Line attenuation
Reflections from stubs (vias)
Integrated Systems Group 10
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Backplane channel
Loss is variable Same back lane
0B]
Different lengths Different stubs
To vs. Bot
-20
-10
nuatio
n[
9" FR4
Attenuation is large>
-40
-30Att
9" FR4,
26" FR4
But is that bad?-60
- v a s u
26" FR4,v ia stub
set by noise0 2 4 6 8 10
frequency [GHz]
Integrated Systems Group 11
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Interference
-20
-10
0
uation[dB]
THROUGH
0.8
1
sponse
-40
-30A
tten
NEXT
0.4
0.6pus
er
Tsymbol=160ps
0 2 4 6 8 10
-60
-
0
0.2
requency zns
Inter-symbol interference
Dis ersion skin-effect dielectric loss - short latenc
Reflections (impedance mismatches connectors, via stubs, device
parasitics, package) long latency
Co-channel interference Far-End & Near-End Crosstalk
Integrated Systems Group 12
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Reflections and Crosstalk
Dont just receive the signal you want Get versions of signals close to you
Vertical connections have worst coupling Close in these vertical connection regions
Far-end XTALK (FEXT)
Desired si nal
Sercu, DesignCon03
Reflections
Near-end XTALK (NEXT)
Integrated Systems Group 13
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A complex system
PCB only
PCB, Connectors,
Via stubs & Devices
Integrated Systems Group 14
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Outline
Look at all aspects of system design
High-speed link environment Improving the channel
What can chi s do?
Integrated Systems Group 15
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Dispersion: material loss
FR4 dielectric, 8 mil w ide and 1m long 50 Ohm strip line1
0.6
0.8
uation
Total loss
Conductor loss
0.2
0.4
Atten
Dielectric loss
1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10
Frequency, Hz Kollipara DesignCon03
PCB Loss : skin & dielectric loss Skin Loss f
Integrated Systems Group 16
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Better dielectric
Rogers
FR4
FR4+stubs
source: Alcatel, Tyco
Integrated Systems Group 17
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Minimizing reflections - the vias
Minimizin via stubs
Thinner PCBs are betterbut sometimes impossible
-
Blind vias
SMT technology
plated through hole
All are costly
1.1x - 2x
Integrated Systems Group 18
counter-boredblind via
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Connector technologies
LC
microvia trace
Standard - Press-Fit Side-Interface (Tyco) Orthogonal - Teradyne(Differential Plated Through Hole)
Surface-mount + microvia
- Side-Interface eliminates DC stubs and diff-pair length mismatch
Orthogonal interconnect DPTH eliminates the backplane
Integrated Systems Group 19
Surface-mount
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Eliminating the backplane - orthogonal interconnect
source: Teradyne
No backplane trace No backplane via-stub
Coax-like shielding and diff-pair matching in DPTH mid-plane
Integrated Systems Group 20
M. Cartier et al Optimized Signal Path for Orthogonal System Architectures, DesignCon 2005.
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DPTH connector performance
No shared vias (non-DPTH) Shared vias (DPTH)
Insertion Loss of DPTH very small Reflections minimized
Integrated Systems Group 21
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Outline
Look at all aspects of system design
High-speed link environment Improving the channel
What can chi s do?
Integrated Systems Group 22
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New link design
Dealing with bandwidth limited channels
This is an old research area Textbooks on digital communications
n mo ems,
But cant directly apply their solutions -
signal processing
20Gs/s A/Ds are expensive
(Un)fortunately need to rethink issues
Integrated Systems Group 23
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Baseline Channels
-20
0
Short ATCA BP, 3
-40
[dB] N6K BP, 26
-80
-60S21
Legacy FR4 BP
26 , via stub
0 5 10 15-100
frequency [GHz]
Legacy (FR4) - lots of reflections
Microwave engineered (N6K)
Integrated Systems Group 24
Emerging standards (IEEE 802.3ap, ATCA)
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Capacity and MT data rates the impact of noise
200
220
200
220
Capacity thermal and phase noise Uncoded MT thermal and phase noise
120
140
160
180
[Gb/s]
120
140
160
180
[Gb/s]
N6K BP
Short ATCA BP
40
60
80
100
Datarat
40
60
80
100
Capacit
Legacy FR4 BP
N6K BP
0 5 10 15 200
20
Noise factor [dB]
0 5 10 15 200
20
Noise factor [dB]
Legacy FR4 BP
Much higher than data rates intodays links
Noise-
Half the capacity
BER target of 10-15
Peak-power constraint
Integrated Systems Group 25
Phase noise best LC PLL(0.14%UI rms)
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Removing ISI baseband link
Linear transmit equalizer
Sampled Deadband Feedback tapsTxAnticausal taps
Data
Channel
Decision-feedback equalizer
LogicCausaltaps
d
outN
outP
d
5050
Transmit and Receive Equalization
0eq
Often easier to work at transmitter
DACs easier than ADCs
Integrated Systems Group 26
J. Zerbe et al, "Design, Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplane
Transceiver Cell," IEEE Journal Solid-State Circui ts, Dec. 2003.
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Pulse amplitude modulation
Binary (NRZ) 1 bit / symbol
Symbol rate = bit rate
2 bits / symbol Symbol rate = bit rate/2
00
011
10
110
Integrated Systems Group 27
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Multi-level: offset and jitter are crucial
thermal noise +
thermal noise +
offset+
o se er
25
30
e[Gb/s]
PAM825
30
e[Gb/s]
35
40
45
e[Gb/s]
erma no se
15
20
Datara
PAM16
PAM4
PAM2
15
20
Datarat
PAM2
PAM4
20
25
30
Datarat
PAM4
PAM8
0 2 4 6 8 10 12 14 16 18 200
5
0 2 4 6 8 10 12 14 16 18 200
5PAM8
0 2 4 6 8 10 12 14 16 18 200
5
10PAM2
To make better use of available bandwidth, need better circuits
Symbol rate [Gs/s] Symbol rate [Gs/s]ym o ra e s s
Integrated Systems Group 28
PAM2/PAM4 robust candidate for next generation links
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Full ISI compensation too costly
thermal noise
thermal noise
+ offset
thermal noise
+ offset+ jitter
14
1618
20
rae
s
14
1618
20
rate[Gb
/s]
PAM4
14
16
18
20
rate[Gb/s]
8
10
12aa
PAM16PAM4
PAM2PAM8
8
10
12Data PAM8
PAM28
10
12Data
PAM2
PAM4
PAM8
0
2
4
0
2
4
0
2
4
6
Symbol rate [Gs/s]Symbol rate [Gs/s] Symbol rate [Gs/s]
Todays links cannot afford to compensate all ISI
Integrated Systems Group 29
Limits todays maximum achievable data rates
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Capacity Bit Loading
7
8
4
4.5Excess Noise factor 0dB Excess Noise factor 20dB
Short ATCA BP
4
5
6
rdimension
2.5
3
3.5
rdimension
N6K BP
1
2
3
#bitspe
1
1.5
2
#bitspe
0 5 10 150
Frequency [GHz]0 5 10 15
0
.
Frequency [GHz]
Legacy FR4 BP
an w s m e y a enua on an no se Cant just keep increasing the signaling frequency
Need to focus on available bandwidth (at most 10-20GHz)
Integrated Systems Group 30
Need circuits that can create/sense 4-8 bits/dim
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Uncoded Multi-tone Bit Loading
1.8
2
4.5
5
Short ATCA BP
Excess Noise factor 0dB Excess Noise factor 20dB
1.2
1.4
1.6
imension
3
3.5
4
imension N6K BP
0.4
0.6
0.8
#bitsperd
1
1.5
2
.
#bitsperd
0 5 10 150
0.2
Frequency [GHz]0 5 10 15
0
0.5
Frequency [GHz]
Legacy FR4 BP
Integer constellations and target BER=10-15
Bandwidth not affected much (still 10-20GHz)
In hi h-noise case - less advanta e over baseband
Integrated Systems Group 31
With coding can improve by up to 2x closer to capacity
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Impact of jitter on baseband
-2
0
-2
0Legacy FR4 BP Short ATCA BP
12Gb/s
-6
-4
BER
-6
-4
BER
8Gb/s10Gb/s25Gb/s
-12
-10
-8
log10
-12
-10
-8
log10
15Gb/s
20Gb/s
0 5 10 15 20
-14
Jitter Factor [dB ]
0 5 10 15 20
-14
Jitter Factor [dB ]
6Gb/s10Gb/s
With proper coding Increase data rate
Integrated Systems Group 32
Original jitter rms = 1.4%UI (ring oscillator based PLL)
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BER vs. hardware complexity
00
Legacy FR4 BP Short ATCA BP
-5
ER
-5
ER
-10
log10
B
25Gb/s-10
log10
B
10Gb/s
0 10 20 30 40-15
# feedback e ta s
15Gb/s 20Gb/s
0 10 20 30 40 50 60 70 80-15
# feedback e ta s
6Gb/s 8Gb/s
Partially eliminate ISI (leave most of the reflections) Let simple code take care of the rest
-
Integrated Systems Group 33
And save up to 50 feedback taps - up to 15mW/Gb/s in 0.13m
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But, need to be careful
Always now what youre optimizing
Powerful coders/encoders often costly
Example - fastest RS (255,239) implementation
Energy cost - 12mW/Gb/s
50x area of the high-speed link (extensive parallelism)
Need to include the energy cost per bit in the
co e es gn spec
Integrated Systems Group 34
L. Song, M-L Yu, M.S. Shaffer, 10- and 40-Gb/s Forward Error Correction Devices for Optical Communications,
IEEE Journal of Solid-State Circuits, vol. 37, no. 11, Nov. 2002.
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Opportunity for coding
Break the coding/equalization/modulation hierarchy
Goal to minimize overall energy cost per bit
Proper coding can be more energy-efficient in achieving thelow BER than modulation/equalization
Need new paradigms in code development to specification -
Circuit non-idealities
Crosstalk and residual channel memory (ISI)
Integrated Systems Group 35
nergy cos cons ra n on co e per ormance
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Bridging the gap: Multi-tone link
10
Multi-tone data rates with thermal noise
8 Nelco 64Gb/s
FR4 38Gb/s
z
4#bits/
2
0 2 4 6 8 10 12 14frequency [GHz]
Integrated Systems Group 36
A. Amirkhany, V. Stojanovic, M.A. Horowi tz, Multi -tone Signaling for High-speed Backplane
Electrical Links, IEEE Global Telecommunications Conference, November 2004.
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Bridging the gap: Multi-tone link
6
8
Multi-tone data rates with thermal noise
Nelco 64Gb/s
FR4 38Gb/s
s/Hz
data0
0
2
4#bit
LPF LPFdata0
ls
a a0 2 4 6 8 10 12 14frequency [GHz]BPF BPF
ejw1t ejw1t
LPF LPF
#leve
dataNBPFBPFLPF
dataN
LPF
f Challenge balancing the inter-symbol and
inter-channel interference
ejwNt
ejwNt
Integrated Systems Group 37
Microwave filter techniques
Custom signal processing
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Conclusions
Interfaces are challenging system designs
Good space to explore system level optimization
Better backplanes are around the corner 2-3x improvement in data rate possible
State-of-the-art baseband links (chips)
Far from utilizing the capacity of the channels
-
Looking into multi-tone and coding to bridge the gap
Useful channel bandwidth 10-20 GHz
ocus on ower-spee prec s on c rcu s or g er or er cons e a ons
Coding
If careful can lower the ener cost er bit for the whole s stem
Integrated Systems Group 38
Problem formulation different in so many ways
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Acknowledgments
MARCO Interconnect Focus Center
Jared Zerbe and Ravi Kollipara - Rambus
John DAmbrosia Tyco
IEEE 802.3a ATCA forum Alcatel, Teradyne, Juniper Networks
Integrated Systems Group 39
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