Semiconductor memory utilization. Memories 2/20 Main memory map Timings Power supplying.
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Semiconductor memory utilization
Memories 2/20
Main memory map
Timings
Power supplying
Memories - utilization 3/20
Standard cases:
Ucc A8 A9 /WE /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4
A7A6A5A4A3A2A1A0
I/O1I/O2I/O3
GND
SRAM
6116(2kB)
Ucc A8 A9 /WE /OE A10 /CS D7 D6 D5 D4 D3
A7A6A5A4A3A2A1A0D0D1D2
GND
EPROM
2716(2kB)
DRAM
1Mb1
256kb4
GND DO /CAS A9 A8 A7 A6 A5 A4
DI/WE
/RASTFA0A1A2A3
Ucc
GND D3 D2 /CAS /OE A8 A7 A6 A5 A4
D0D1
/WE/RAS
A0A1A2A3
Ucc
Ucc /WE CE2 A8 A9 A11 /OE A10 /CE1 D7 D6 D5 D4 D3
A12A7A6A5A4A3A2A1A0D0D1D2
GND
SRAM
8464(8kB)
Ucc /PGM A8 A9 A11 /OE A10 /CE D7 D6 D5 D4 D3
UppA12
A7A6A5A4A3A2A1A0D0D1D2
GND
EPROM
2764(8kB)
Ucc /WE A13 A8 A9 A11 /OE A10 /CE D7 D6 D5 D4 D3
A14A12
A7A6A5A4A3A2A1A0D0D1D2
GND
PSRAM
TC51832(32kB)
Memories - utilization 4/20
timersRTC
addressdecoders
MM serv. devices
interruptcontrollers
secondarymemories
processor
programmememory(ROM)
datamemory(RAM)
operatordevices
commu-nicationdevices
processdevices
Semiconductor memories in system:
main memory
video memory
semiconductor disksconfig
memory
databufferingmemories
Problems: • connecting different memory chips to bus• differentiating the types of memory in system
Memories - utilization 5/20
Connecting memory chips to bus
‘245 B0B1B2
A0 B3: B4
A7 B5B6B7
/G DIR
D0 D1 D2 D3 D4 D5 D6 D7
RAM
/OE /WE /CE
A0 : An
/MREQ/RD
/WR/CS
ADDR
DATA
Dx DI DO RAM R/W /CE
A0 : An
/WR/CS
/RD
ADDR
Memories - memory map 6/20
Memory map
It’s defined as assignment of different types and sizes of memories to address
windows in microprocessor (microprocessor system) address space.
0000h
0800h
1000h
1800h
FFFFh
4kBEPROM
2kBRAM
0000h
1000h
8000h
9000h
FFFFh
4kBEPROM
4kBRAM
0000h
0800h
1000h
1800h
2000h
FFFFh
2kB
EPROM
2kB
RAM
2kB
RAM
2kB
RAM
0000h
0800h
1000h
1800h
2000hFFFFh
2kB
EPROM
2kB
EPROM
2kB
EPROM
2kB
RAM
Memories - memory map 7/20
Example of memory map:
precise realisation: EPROM 2764 - 8kB: 0000h..1FFFhSRAM 6164 - 8kB: 2000h..3FFFhnot used: - 48kB: 4000h..0FFFFh
A1B2C3
E14E25E36
Y0 15Y1 14Y2 13Y3 12Y4 11Y5 10Y6 9Y7 7
U1
74LS138
A010A19A28A37A46A55A64A73A825A924A1021A1123A122
20262722
D0 11D1 12D2 13D3 15D4 16D5 17D6 18D7 19
U2
6164
A010
A19
A28
A37
A46
A55
A64
A73
A825
A924
A1021
A1123
A122
2022271
D0 11
D1 12
D2 13
D3 15
D4 16
D5 17
D6 18
D7 19
U3
2764
A13A14A15
Vcc
Vcc Vcc
D[0..7]
A[0..15]
/MRQ
/WR
/RD
OEWECS2CS1
CEOEPGMVPP
Memories - memory map 8/20
Example of memory map - simplified realisation:
access addresses:to EPROM:xx00000000000000b..xx01111111111111bto SRAM:xx10000000000000b..xx11111111111111b
A13
/MREQ
/CS0
/CS1
Effect:
the same byte of memory is visible, accessible through 4 addresses,differentiating in A15 & A14 bits
Faults:
• the whole memory space is used;
• there is no space to additional memory chips;
Memories - timings 9/20
reading
ADR
CE
R/W
D0..D7
tRC
tACE tHAD
tAA
tARWtHDA
tHDC
Timings during reading from the memory:
read cycle time - time between the begin of read cycle and the begin of the
next cycle (read or write) tRC = tAA + tHAD
address hold time after data valid begin
data hold time after /CE signal end
data hold time after address change
tAx - data valid time after the change of chosen control signal, when other signals are stable:
tAA - address to data valid; tACE - /CE low to data valid; tARW - after the change of R/W;
tA - access time - the greatest time from tAx
Memories - timings 10/20
writing
ADR
CE
R/W
D0..D7
tWC
tWR
tW
tHDW
Timings during writing to the memory:
address hold time after write pulse end - time between the write pulse end
and the begin of next access to memory
minimal write pulse time
write cycle time - time between the begin of write cycle and the begin of
the next cycle (read or write)
data hold time after write end
Memories - timings 11/20
DATA
ADDRESSES
CONTROL SIGN.tB2
tB4
CPU module
P
tR tRAD
RAM module
localdecoder
tD1
memory blocktAA tACS tARW
/CS
tB1
tB3
Example of signals flow during memory reading:
Memories - timings 12/20
tA
ADRP
ADRMAG
CS
RDP
RDMAG
DPAM
DMAG
DP tRAD
tB3 tB4tAA
tACS
tARW
tR
tB2
tD1tB1
Example of time dependencies during memory reading:
Memories - timings 13/20
Correct reading conditions:
C1: tRAD tA1 = tB1 + tAA + tB3 + tB4
C2: tRAD tA2 = tB1 + tD1 + tACS + tB3 + tB4
C3: tRAD tA3 = tR + tB2 + tARW + tB3 + tB4
Example of timing analysis:
Ass.: EPROM with: tAA = 200ns , tACS = 200ns , tAOE = 75ns (tARW)
P Z80 with clock = 2.5MHz tR = 150ns , tRAD = 800ns
tB1 , tB2 , tB3 , tB4 = 10ns , tD1 = 20ns
C1: tA1 = tA1 = tB1 + tAA + tB3 + tB4 = 10+200+10+10 = 230ns
C2: tA2 = tA2 = tB1 + tD1 + tACS + tB3 + tB4 = 10+20+200+10+10 = 250ns
C3: tA3 = tA3 = tR + tB2 + tARW + tB3 + tB4 = 150+10+75+10+10 = 255ns
( tA1 , tA2 , tA3 ) tA = 255ns < tRAD
Even at = 6MHz the given EPROM should be read correctly.
Memories - timings 14/20
DATA
ADDRESSES
CONTROL SIGN.tB2
tB4
CPU module
P
tR tRAD
RAM module
local decoder
tD1
memory block
/CS
tB1
tB3
Example of signals flow during memory writing:
MRQ
WR
Memories - timings 15/20
Example of time dependencies during memory writing:
tB1+tB3tDuP1
tB3
tB1
tWuPtB2
tD1tB1
tDuP2
tWPuP
ADRP
ADRMAG
CS
WRP
WRMAG
D P
DMAG
D PAM
tDHW*
tWP*
tDBW*
tCSBW*
tWR*
tABW*
Memories - timings 16/20
In the case of RAM writing cycle following should be checked:
write pulse duration generated by P;
resultant (in designed system) times: address to write pulse begin,
data to write pulse begin, chip enable to write pulse begin
in comparison with memory chip datasheets;
data hold time after write pulse.
Correct writing conditions :
C1: tWPuP > tWP*
C2: tWuP + tB2 + tWPuP - tB1 > tABW*
C3: tWuP + tB2 + tWPuP - tB1 - tD1 > tCSBW*
C4: tWuP + tB2 + tWPuP - tDuP1 - tB1 - tB3 > tDBW*
C5: tDuP2 + tB1 + tB3 - tWuP - tB2 - tWPuP > tDHW*
Memories - supplying 17/20
During work memory chip can use 3 values of supply current:
• operating current ICC - during access to chip (reading or writing);
• stand-by current ISB - without access to chip supplied defined operating voltage UCC;
• data retention current IDR - supplies memory chip at decreasing voltage to
data retention voltage UDR.
Memories - supplying 18/20
Currents ICC (operating current) & ISB (stand-by current):
UCC
ICC
ISB
CE
CE
opera-ting
ISUP
tI Q=tI
CE
opera-ting
ISUP
„far”charge source- supplier
„near”charge source- capacitor
Memories - supplying 19/20
The supply of memory chips should be blocked near theirs supply pins
by non-inductive capacitors to achieve:
• reducing current peaks on supply lines;
• increasing operation speed.
Data retention in CMOS-SRAM in power-down mode:
UDD
VDR VDR » 2V UCE > VDR-0,2V UCE
0V
ISB
IDR
Memories - supplying 20/20
Example of supply controlling and switching IC:
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