Performance estimates for the various types of emerging memory devices Victor Zhirnov (SRC) and Ramachandran Muralidhar (Freescale)

Performance estimates for the various types of emerging memory devices

Victor Zhirnov (SRC) and Ramachandran Muralidhar (Freescale)

2

Rationale

We seek to identify fundamental physical limits for various types of memory devices Best projections for scaling

e.g. “no consolidated theory has been developed for Flash scaling

Flash Memories, P. Cappelletti et al (Eds), Kluwer 2001

3

Attributes of an ideal memory

Nonvolatility with long retention (e.g.. > 10 years) High density Low power In-system rewrittability Fast read/write High endurance (the number of erase/write/read cycles) Integration with CMOS logic:

Matching operational voltage Matching time (speed)

Focus of this talk

4

Three Components of Memory Device

Three equally important components of memory systems:

Memory cell (Physics of of Write/Erase/Program) Sensing (Physics of Read/Sense) “Wires” (implication of the physics of Write and Read to

accessibility) The key of a cell’s usefulness is whether the cell can be written

to and read from without affecting the surrounding cells.

Focus of this analysis

5

ERD ITWG Memory Discussion

10:45 Quantitative estimates of performance for the various types of memories

Engineered barrier Muralidhar and ZhirnovFerroelectric WaserNanoelectromechanical ZhirnovFuse/Antifuse Waser and Akinaga

12:00-12:30 Lunch

Ionic Waser and AkinagaElectronic Effects Waser and ZhirnovMacromolecular ZhirnovMolecular Waser

1:30 Break - Adjourn Memory Discussion

6

Charge-based Memories

A Be-

Control

Requirements:

1) Efficient charge injection during programming

2) Suppressed back-flow of charge in store/read modes

3) Efficient erase

4) Min. charge/bit: q=e=1.6x10-19 Q

DRAM/SRAM

Floating Gate Memory

SONOS

7

Barrier-less Ohmic Transport: The most efficient injection, but…

VI AB ~WriteStore

… difficult retention

Eb

What is the minimum barrier height for the charge-based NVM?

Example: DRAM

Charge-based memory is a two-barrier system

8

What is the minimum barrier height for the charge-based NVM?

Store

Problem: In Si devices Ebmax<Eg=1.1 eV

Eb

kT

EJJ bthth exp0

Thermionic leakage current (ideal case):

EbminMin. barrier height for NVM

Eb, eV Max. retention0.7 80 ms0.9 28 s1.1 2.5 h1.3 1 month1.5 31 years

High-barrier are needed for Non-volatile memory

9

Charge injection problem in high-barrier systems

BUT: Barrier formed by an insulating material (large Eb) cannot be suppressed) – charge transport in the presence of barriers: Non-ohmic charge transport

High-barriers are needed for Non-volatile memory

Tunneling

Hot-electron injection

Newly proposed nanomechanical DRAM addresses this problem

10

Two-barrier charge-based NVM

C. Y. Chang, S. M. Sze (Eds.), “ULSI Devices” (John Wiley & sons 2000)

Floating gate memory

M. H. White,Y. Yang, A. Purwar, and M. L. French, IEEE Trans. Compon. Packag. and Manufact. Technol.—Pt A 20 (1997) 190

SONOS memory

11

Floating gate memory: WRITE and STORE modes

V

I

VC

I

qtw

Control gate

Floating gate

FET channel

‘0’

V

I

VC

I

qtret

leakage

WRITE

STORE

12

V

V

EaC

Tt b

NF

23

1exp~1

~

Floating gate cell: Write – triangle barrier Retention – trapezoidal barrier

We need to create an asymmetry in charge transport through the gate dielectric to maximize the Iwrite/Iret ratio

bDT

ret EaCT

t 2exp~1

~

The asymmetry in charge transport between WRITE and STORE modes is achieved through different shape of barrier (triangle vs. trapezoidal)

13

Floating Gate Cell Retention and WRITE characteristics

Ideal case

Retention: direct tunneling kBT/e <Vstored<Eb

a

The retention time strongly depends on thickness

VF-N

VW

Eb

Write: F-N tunneling: VF-N>Eb

bNFW EVV 22min

Si/SiO2: Eb=3.1 V, VWSiO2>6.2 V

For lower WRITE voltage Eb should be decreased:

Ebmin=1.5 eV Vmin>3 V

Barrier Eb V WR a t WR

Si/SiO2 3.1 eV 6.8 V 5.4 nm 1hSi/SiO2 3.1 eV 12 V 5.4 nm 30ms

Min. barrier 1.5 eV 4 V 6.3 nm 5ms

Barrier Eb V Ret a t Ret

Si/SiO2 3.1 eV 2 V 4 nm 4.35 minSi/SiO2 3.1 eV 2V 5.4 nm 20 y

Min. barrier 1.5 eV 0.025 V 6.3 nm 11 y

14

The Industry Standard Flash Memory Cell

Flash Memories, P. Cappelletti et al (Eds), Kluwer 2001

15

Parameters Projections for n-FG

This Analisis SiO2, Eb=3.1eV Vmin>6.8 V (slow operation) V~12 V (ms operation) amin>5.4 nm (reliability issue) Lmin>15 nm (gate stack AR,

FET issues…)

‘Optimized’ FG memory cell Eb=1.5 eV HfO2 Vmin>3 V (slow operation) V~4 V (ms operation) amin~6.3 nm Lmin~12 nm

Standard FLASH SiO2

Eb=3.1eV - 10-20 V ~6 nm ~18 nm

Flash Memories, P. Cappelletti et al (Eds), Kluwer 2001

Nanocrystals, Charge trapping

High-K !

16

Parameters Projections for n-FG

a

LC

20

min2

~

e

ECCVQ b

FGFG 2~

e

QNel

bel ENE ~min

SiO2 HfO2

~2x10-18 F ~6x10-18 F

30 30

1.43x10-17 J 7.2x10-18 J

Lower bound (slow operation)

3x10-16 JV~12 V (ms operation)

Statistical issue

17

Materials Challenges of symmetrically graded

barrier : vs. K

22

21 11

C

E

CK

g

goffsetB EE =0.2-0.5

Kramers-Kronig relation

0

10

20

30

40

50

60

70

80

90

100

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Bandgap, Eg (eV)

Die

lect

ric

con

stan

t, K

Al2O3

TiO2

LiFCaF2

HfO2

BaZrO3

SiO2

Gd2O3

BaF2MgO

SrF2GdF2

Diamond

Si3N4

Ta2O3

ZrO2

ZrSiO2

Sc2O3

La2O3

Y2O3

K1 <K2

18

Symmetrically graded (crested) barrier

-0.5

0

0.5

1

1.5

2

2.5

-6 -4 -2 0 2 4 6

X

j(x

)

V=0 Eb=2 V-1.5

-1

-0.5

0

0.5

1

1.5

2

-6 -4 -2 0 2 4 6

X

j(x

)

V=1 V Eb=1.5 V-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

-6 -4 -2 0 2 4 6

X

j(x

)

Eb=1 VV=2 V-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

-6 -4 -2 0 2 4 6

X

j(x

)

V=2*Eb=4 V Eb=0 Likharev, K.K., Single-electron devices and their applications, Proc. IEEE 87 (1999) 606-632

Uses a stack of insulating materials to create a special shape of barrier enabling effective transport into/from the storage node

Vw~8 V

19

Engineered tunnel barrier memory

Likharev

20

Charge injection problem in high-barrier systems

Hot-electron injection

eVEEhei14

min 102~/4~

More accurate estimates based on Shockley’s lucky electron model TBD

21

Summary on Floating Gate Memory

Operation voltage cannot be small (e.g. V>6 V for Si/SiO2)

V-t dilemma

Question: How to reduce the write voltage for the tunneling based memories?

Answer:

To perform write operation in direct tunneling mode

In principle, the voltage can be as small as wished

There are two problems though:

1) Very slow writing

2) Very small retention

22

SONOS

M. H. White,Y. Yang, A. Purwar, and M. L. French, IEEE Trans. Compon. Packag. and Manufact. Technol.—Pt A 20 (1997) 190

For lower voltage operation of floating charge memory, direct tunneling needs to be used for charge injection.

Tunnel insulator must be very thin for reasonably small WRITE time

We now have a problem of of how to create the asymmetry between WRITE and STORE charge transport paths

23

SONOS : Write and Retention

Write: Direct tunneling: Vtun<3.1 V, awrite=d1

aret

d1

d2

d3

aret>awrite

btd

EaCT

t

2exp~1

~

The asymmetry between WRITE and STORE charge transport paths is achieved by different path length

X. Wang, et al, IEEE Trans. El. Dev. 51 (2004) 597

Retention:

BUT: We now have a problem of of how to create the symmetry between WRITE and ERASE operations

Barrier Eb V tun d1 d2 d3 V write t write

Si/SiO2 3.1 eV 2 V 2 nm 10 nm 4 nm 11 V >1 s"Minimum barrier" 1.5 eV 1 V 2 nm 10 nm 4 nm 5.5 V >2 ns

tunNSiSiO

tunw Vd

KKdddVV

5

)/(

1

231 432 Retention???

Erase???

24

Solutions to improve characteristics of charge-trapping memory?

Alternative dielectrics, e.g. with lower barrier height, high K

Is it possible to control/engineer the trap sites in silicon nitride: concentration, distribution, position, energy levels?

X. Wang, et al, IEEE Trans. El. Dev. 51 (2004) 597

HfO2

HfO2

Ta2O5

ERM

25

Conclusion on ultimate charge-based memories All charge-based memories suffer from the “barrier”

issue: High barriers needed for long retention do not allow fast

charge injection It is difficult (impossible?) to match their speed and voltages

to logic

Voltage-Time Dilemma

Non-charge-based NVMs?

Electronic Effects

27

Electronic Effects Memory

1) Charge injection and trapping Simmons and Verderber, “New conduction and reversible

memory phenomena in thin insulating films” 2) Mott transition 3) Ferroelectric polarization effects.

28

Simmons-Verderber theory

Unipolar/non-polar switching Charging trapes in insulator

‘Forming process’ is critical Strongly suggestive of positive ion injection into insulator

2 ns

100 ns

Write Erase

I

29

Energy Diagram, V=0

30

Energy Diagram, V>0

V<0 (energy of localized levels)

V>0 (energy of localized levels)

31

Memory effect: Charge injection

32

Memory effect: Charge travel

33

Memory effect: Charge storing

34

Memory effect: Charge erase

11 ~ s

Ltsw 2

~ 1

35

Switching (Erase) time estimate

Quantum harmonic Oscillator

h

ms24

EEs

mtrap

22exp~

2~

3

1

Ns

2

2

8ms

hE

N~1019 cm-3

s~2 nm

Etrap~1 eV

36

Switrching time

nsd

Ltsw 130~

2~ 1

ns30~~ 11

3

1

3

22 exp~)exp(~ bNaNbsast

37

Thickness scaling

eN

02~

2min L

N~1019 cm-3

~9 nm

Lmin~20nm

L

38

Scaling limits depend on materials properties

2~

3

1

Ns N~1019 cm-3

s~2 nm Etrap~1 eV

eN

02~

~9 nm

2min L

Lmin~20nm

3

1

3

2

exp~ bNaNLt

tmin~60ns

39

Macromolecular Memory

Polymer memory Organic memory

Different mechanisms proposed Filaments Ionic Charged traps in polymer etc

Verbakel et al. “Reproducible resistive switching in nonvolatile organic memories”, APL 91 (2007) “Resistive switching in organic memories can be due to the

presence of a native oxide layer at an aluminum electrode”