Next Generation Wireless Communication System · Next Generation Wireless Communication System - Cognitive System and High Speed Wireless - Yoshikazu Miyanaga Distinguished Lecturer,
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All right reserved. Copyright ©2011- Yoshikazu Miyanaga
Next Generation Wireless Communication System
- Cognitive System and High Speed Wireless -
Yoshikazu MiyanagaDistinguished Lecturer, IEEE Circuits and Systems Society
Hokkaido UniversityLaboratory of Information Communication Networks
Graduate School of Information Science and TechnologySapporo 060-0814, Hokkaido Japan
All right reserved. Copyright ©2011- Yoshikazu Miyanaga
Key Technologies
OFDM (Orthogonal Frequency Division Multiplexing)Wireless LAN
54MBPS (IEEE 802.11a, .11g)300MBPS – 600MBPS (IEEE 802.11n)
Digital TV broadcastingWiMAXNext Generation Mobile Phone
3G LTE (super 3G, - 2010 in JP), 4G ( - 2015 in JP)
MIMO (Multiple Input Multiple Output Communication Channels )Wireless LAN
300MBPS – 600MBPS (IEEE 802.11n)Over 1GBPS (IEEE802.11ac)
Advanced WiMAXNext Generation Mobile Phone
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Basic OFDM System
Input Data
Output Data
Mapping
S/P
IFFT
channel
Dem
apping
P/S
Delete G
I
S/P
FFT
Equalizer
P/S
D/A
Guard Interval
A/D
All right reserved. Copyright ©2011- Yoshikazu Miyanaga
Basic OFDM System
Input Data
Output Data
Mapping
S/P
IFFT
channel
Dem
apping
P/S
Delete G
I
S/P
FFT
Equalizer
P/S
D/A
Guard Interval
A/D
Coder:cov, blk
De-Coder:Viterbi,LDPC
512 – 1024 p FFT within several nanosecond
512 – 1024 p FFT within several nanosecond
Low Power Design
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MIMO System
Transmitter
Receiver
Mapper
Mapper
IFFT
IFFTTX
Encoder
Encoder
FFT
FFT
MIM
O
Detector
De-Mapper
De-MapperRX
Decoder
Decoder
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MIMO Decoding Circuit
The mode when the receiver gets the training symbolsThe estimation of channel and the inverse matrix calculation should be completed.
The mode when the receiver gets data symbolsMIMO decoding should be applied.
from FFT ΒA,
H
(from 1st and 2nd training symbols)
G
1−Η=G
y s
Channel Estimation
Inverse Matrix Memory
MIMO Detector
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MIMO Decoding Circuit
from FFT ΒA,
H
(from 1st and 2nd training symbols)
G
1−Η=G
y s
Channel Estimation
Inverse Matrix Memory
MIMO Detector
Matrix Inversionwithin several nanosecond
Low Power Design
High speed & Low power ….
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Low Power Consumption Design
Smaller number of GatesSwitching power reductionLeak current reduction
Parallel/Pipelined CalculationLower Clock Rate
Power ControlGated clockDynamic Power Suspension of Module Block
8
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and MORE …
Lower Voltage Input SupplySub-threshold designDynamic voltage control
New Algorithm DesignLower calculation costComplete Parallel/Pipelined Processing
New Architecture DesignDynamic Architecture
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COGNITIVE RADIO SYSTEM FOR THE NEXT GENERATION WIRELESS NETWORK
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WHAT IS COGNITIVE RADIO ?!?
In 2000, FCC introduced a “Cognitive Radio System” which used efficiently frequency bands.
In 2005, IEEE 802 Committee introduced an advance system, i.e., a cognitive radio system, in which an occupied frequency band is automatically selected and dynamically changed.
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Conventional Radio Mode
All available frequency bands are fixed. Accordingly, the frequency band possibly used for the system has been assigned as a prior information.
ch1 for system A
ch2 for system B
ch3 for system C
Freq.ch1 ch2 ch3
A B C
A
A
B
C
C
time : t1
time : t2
time : t3
time : t4 B
FCC reports over 80% bands are not used at the specific location and time.
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Cognitive Radio Mode
ch1 for system A
ch2 for system B
ch3 for system C
Freq.ch1 ch2 ch3
A B C
A
A
B C
C
time : t1
time : t2
time : t3
time : t4 B
C
C
• The system finds out the available bands and then select some of suitable bands dynamically by itself.
System C is a cognitive radio.
System A and B are conventional radio.
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Cognitive Radio Mode
• It changes the frequency bandwidths depending on communication environment.
The resources of frequency bands are fully and optimally used.
• It has many communication modes.The high throughput is usually kept.
• The complexity of a system becomes high compared to a fixed radio system.
High power-consumption and circuit size become considerably large.
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Our cognitive system
Our design of new cognitive system is based on MIMO-OFDM system.
All parts of our system behaves as cognitive systems !!!
15
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Cognitive MIMO-OFDM
RF8x4 MIMO
.11a OFDM 2x2 MIMO
450M VHT OFDM
4x4 MIMO
4x2 MIMO300M OFDM
MAC
.11n OFDM
Con Sensor Processor
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Cognitive MIMO-OFDM
RF アンテナ8x4 MIMO
.11a OFDM 2x2 MIMO
1.8G New OFDM
4x4 MIMO
4x2 MIMOCognitive OFDM
MAC
.11n OFDM
Con Sensor Processor
Intelligent Sensor is designed. A sensor tries to find out the information of current communication environment.
450M New OFDM
The AI controller determines the optimum communication mode with suitable parameters in which lowest BER/PER can be designed. From its decision, a specific mode and a suitable band are selected automatically.
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Cognitive MIMO-OFDM
RF
.11a OFDM 2x2 MIMO
450M VHT OFDM
4x4 MIMO
4x2 MIMO300M OFDM
MAC
.11n OFDM
Con Sensor Processor
8x4 MIMO
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Cognitive MIMO-OFDM
RF
.11a OFDM 2x2 MIMO
450M VHT OFDM
4x4 MIMO
4x2 MIMO300M OFDM
MAC
.11n OFDM
Con Sensor Processor
8x4 MIMO
Cognitive MIMO-OFDM is designed. Its features are given as follows
•20~100MHz band is determined dynamically.•Minimum PER can be achieved.•The optimum throughput is selected among 54M~1.8Gbps.
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Modes in Cognitive MIMO-OFDM
HU-VHT
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Number of Butterfly Blocks
HU-VHT
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Required data paths for all FFTs
Array of Butterfly blocks
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Evaluation
Hardware description language
Verilog HDL
Logic synthesis Design AnalyzerClock frequency 100MHz
technology 90nmCMOS
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Evaluation(consumption power)
75.8HU-VHT 2x2 MIMO
48.0802.11n 2x3 MIMO
802.11n 4x4 MIMO
IEEE802.16eSISO
802.11n SISO
System
24.338.163.440.7
16.1
Conventional(mW)
512128
256512102464
128
FFT length
76.148.5
24.538.263.841.3
16.2
Proposed(mW)
802.11a/n SISO 10.3128 10.4
“Conventional” means each power consumption is given from a corresponding sub-module only. It does not means the power consumption of the total system.
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Evaluation(circuit area)
Conventional ProposedNo. of gates
Area 1.79 1.16
51096.5 × 51087.3 ×
Proposed structure can reduce a circuit scale by about 35%.
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HIGH SPEED WIRELESS COMMUNICATION
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All right reserved. Copyright ©2011- Yoshikazu Miyanaga
Current Trend of MIMO-OFDM SystemsIEEE802.11 Standards
Development by Hokkaido Univ.(Only Baseband)
IEEE802.11a (2002) 54Mbps
IEEE802.11n Draft (2007) 300Mbps
IEEE802.11n Optional (2009) 600Mbps
IEEE802.11ac[2012] 3.0 Gbps Hokkaido Univ.
4x4 MIMO-OFDM (2008) 1.5 Gbps
Hokkaido Univ. 2x2 MIMO-OFDM (2006) 600 Mbps
Hokkaido Univ. SISO-OFDM
(2005) 300 Mbps
Hokkaido Univ. 8x8 MIMO-OFDM
(2010) 3.0 Gbps
Tran
smit
Spee
d
Bandwidth20MHz 40MHz 60MHz 80MHz
500Mbps
1Gbps
2Gbps
3Gbps
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Xilinx・Gigabit Ethernet MAC・STARC MAC
Altera・STARC PHY
Output
Gigabit Ethernet PHY
FPGA Board for Evaluation
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Dynamic Architecture of Low Power
OFDM BBTransmitter
OFDM BBReceiver
OFDM BBTransmitter
OFDM BBReceiver
Sensor SensorMonitering
Realization of High Throughput and Low Power
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Block Diagram of 4x4 MIMO-OFDM Circuit
Transmitter
Scrambler Encoder Mapper Pilot Insertion
IFFT Re-order & GI Insertion
Preamble Insertion
Interleave& Puncture
Receiver
Frame & Freq. Synchronization
FFT Re-order & Pilot Remove
MIMO Channel Est. & Decoding
Demapper Viterbi Decoding
De-scramblerDe-interleave & Dummy Data
Insertion
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Matrix Operations
Use of 2x2 SubmatricesConjugate Symmetry in Non Diagonal Submatrices
11P
21P12P 13P
22P
33P 34P
43P 44P
14P
24P 23P
31P 32P
42P41PConjugate Symmetry
Hermitian Transpose
IHHP 2kk
Hkk σ+=
⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛=
DBBA
DCBA
H
Complexity ReductionStrassen’s Matrix Multiplication and InversionUse of Conjugate Symmetry Submatrices
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Performance Comparison
Reference [2] [3] [4] ProposedMatrix 2 x 2 4 x 4 4 x 4 4 x 4
Detection Algorithm ZF ZF MMSE MMSE
Hardware Configuration
DSPTMS3206713
ASIC 90 nm43 k gates
ASIC 0.25 µm89 k gates
ASIC 90 nm1.86 M gates
Operating Freq. 225 MHz 500 MHz 167 MHz 160 MHz
Latency Time 104 x K (µs) 180 x K (ns) 600 x K (ns) 187.5 (ns)
K: No. of OFDM Subcarriers
[2] V. Jungnickel, A. Forck, T. Haustein, et al., “1 Gbit/s MIMO-OFDM transmission experiments,'' IEEE Vehicular Technology Conference (VTC), 2005.
[3] Johan Eilert, Di Wu, and Dake Liu, “Efficient complex matrix inversion for MIMO software defined radio,” IEEE ISCAS, 2007.
[4] A. Burg, S. Haene, D. Perels, P. Luethi, N. Felber, and W. Fichtner, “Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems,” IEEE ISCAS, 2006.
All right reserved. Copyright ©2011- Yoshikazu Miyanaga
Available Data Speed
Necessary ConditionsClock Frequency ≥ Baseband BandwidthProcessing Latency ≤ GI Duration (400 ns)
Bandwidth (MHz)
Max
imum
Tra
nsm
issi
on S
peed
(M
bps)
A 2.6-Gbps MIMO-OFDM receiver is available by the proposed MMSE detector.
5/6 Coding Rate
64-QAM
400-ns GI Duration
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4x4 MIMO-OFDM with 512 SUBCARRIERS
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Design Challenge of 8x8 MIMO-OFDM
Task group of IEEE802.11ac mentions use of more than four antennas.
The maximum number of spatial streams is eight.
8x8 MIMO-OFDM1.2 Gbps at 40-MHz Channel3.0 Gbps at 80-MHz Channel6.0 Gbps at 160-MHz Channel (Use of two transceivers)
High Speed and Low-Power Architecture for 8x8 MIMO-OFDM
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Current Activities in Our Project
Total design of 8x8 MIMO-OFDM transceiverIntegrated design for multiple data streamsReal-time processing for MIMO detectionLow power design by intelligent power control
Prototype fabrication of wireless systemIntegration of baseband, RF, antenna units
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Block Diagram
Scrambler Encoder Interleave & Puncture
Pilot Insertion
IFFT Re-order & GI Insertion
Preamble Insertion
Mapper
Viterbi Decoding
Frame & Freq .Synchronization
FFT
Re-order & Pilot Remove
MIMO Channel Est. &Decoding
Demapper
De-interleave & Dummy Data Insertion
De-Scrambler
Transmitter
Receiver
Blocks in FFT/IFFT, Viterbi decoding, MIMO decoding are dominant in circuit scale.
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Integrated DesignDuplicate design
Deploy identical circuit blocks for the number of spatial data streamsIncrease power and area in proportion to spatial data streams
Integrated designA circuit block supports multiple-input and multiple-output data paths.Reduce power and area by resource sharing
FFT
FFT
FFT
FFT
FFT
FFT
MIMO FFT
SISO FFT processorsMIMO FFT processor
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Multi-Path Delay FFT ProcessorR8MDC (Radix-8 multiple path delay communicator)
Based on 8-input and 8-output butterfly unitsReduction of multipliers by FFT radix-8 algorithm
A 8x8 MIMO FFT processor only needs 1/3 circuit area compared with eight SISO FFT processors.
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Implementation of 8x8 MIMO-OFDMCircuit performance (100MHz clock, w/o MIMO decoding)
Transmitter
Receiver
No. of logic gates Power Dissipation (mW)
IFFT 573,400 91.2
Interleave* 104,000 15.0
Pilot assignment* 219,000 32.2
Others* 348,500 47.3
Total 1,244,900 185.7
No. of logic gates Power Dissipation (mW)
FFT 573,700 117.0
Synchronization 24,900 2.8
Channel Estimation 19,600 1.7
Viterbi decoding 2,724,300 251.6
Deinterleave* 677,200 73.4
Others* 219,500 33.4
Total 4,239,200 479.9
* memory buffer included
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MIMO Detection
Strassen’s algorithmSystematic matrix operation based on 2x2 matricesExtension of square matrix operations
8x8 matrix inversion
8
8
4x4 matrix inversion
4x4 matrix multiplication
2x2 matrix inversion
2x2 matrix multiplication
Division of submatrices in matrix inversion
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Timing ChartReceived signals in frequency domain after FFT
Preprocessing (matrix inversion)
)()()( ttt kkkk nsHy +=
Hkkk
Hkk HIHHG 12 )( −+= σ
MIMO decoding)()(ˆ tt kkk yGs =
k: OFDM subcarrier index
t: OFDM symbol index
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Implementation of MIMO Detector8x8 MIMO detection can complete within guard interval (800 ns) duration.
Complete real-time processing in MIMO detection, which is tolerant of time varying fading.
8x8 FullPipeline
4x4 Full Pipeline*
Wordlength (bits) 26 20
Operating Frequency 80MHz 160MHz
Total cell area (μm2) 61,570,100 8,813,200
Number of logic gates 15,392,500 2,203,300
Processing Latency 780 ns 190 ns
Power Consumption 1.42 W 701.2mW
*Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga, ``VLSI Implementation of a Complete Pipeline MMSE Detector for a 4x4 MIMO-OFDM Receiver,'' IEICE Transactions on Fundamentals, Vol.E91-A, No.7, pp.1757-1762, July 2008.
All right reserved. Copyright ©2011- Yoshikazu Miyanaga
Prototype FabricationWireless transceiver
2x2 MIMO-OFDM transmitter and receiverFPGA baseband unitsRF transceiver (5150 - 5250 MHz frequency band)*
*Shingo Yoshizawa, Shinya Odagiri, Yasuhiro Asai, Takashi Gunji, Takashi Saito, Yoshikazu Miyanaga,``Development and Outdoor Evaluation of an Experimental Platform in an 80-MHz Bandwidth 2x2 MIMO-OFDM System at 5.2-GHz Band,''IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Sep. 2010.
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FPGA Board2x2 MIMO-OFDM Transceiver
400 M samples/s by 4x over samplingMMSE and MLD algorithms in MIMO detection
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Summary
New Trend of Wireless CommunicationsMIMO-OFDM
802.16 WiMAX3G LTE (super 3G, - 2010 in JP), 4G (- 2015 in JP)
LTE : Long Term Evolution
802.11ac ( over 1GBPS wireless LAN)
Cognitive Wireless SystemUltra High Speed Wireless System
4x4 MIMO-OFDM8x8 MIMO-OFDM
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All right reserved. Copyright ©2011- Yoshikazu Miyanaga
Who ?
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Yoshikazu MiyanagaHe is a professor in Graduate School of Information Science and Technology, Hokkaido University. He is an associate editor of Journal of Signal Processing, RISP Japan (2005-present). He was a chair of Technical Group on Smart Info-Media System, IEICE(IEICE TG-SIS) (2004-2006) and now a member of the advisorycommittee, IEICE TG-SIS (2006-present). He is also vice-President,IEICE Engineering Science (ES) Society. He is a fellow member ofIEICE. He is also vice-President, Asia-Pacific Signal and Information Processing Association (APSIPA). He is a distinguished lecture (DL) of IEEE CAS Society (2010-2011) and now a Board of Governor (BoG) of IEEE CAS Society (2011-present).
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